1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include "../ops.h" 20 #include "acp.h" 21 #include "acp-dsp-offset.h" 22 23 static bool enable_fw_debug; 24 module_param(enable_fw_debug, bool, 0444); 25 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 26 27 static struct acp_quirk_entry quirk_valve_galileo = { 28 .signed_fw_image = true, 29 .skip_iram_dram_size_mod = true, 30 }; 31 32 const struct dmi_system_id acp_sof_quirk_table[] = { 33 { 34 /* Steam Deck OLED device */ 35 .matches = { 36 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 37 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 38 }, 39 .driver_data = &quirk_valve_galileo, 40 }, 41 {} 42 }; 43 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 44 45 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data) 46 { 47 pci_write_config_dword(dev, 0x60, smn_addr); 48 pci_write_config_dword(dev, 0x64, data); 49 50 return 0; 51 } 52 53 static int smn_read(struct pci_dev *dev, u32 smn_addr) 54 { 55 u32 data = 0; 56 57 pci_write_config_dword(dev, 0x60, smn_addr); 58 pci_read_config_dword(dev, 0x64, &data); 59 60 return data; 61 } 62 63 static void init_dma_descriptor(struct acp_dev_data *adata) 64 { 65 struct snd_sof_dev *sdev = adata->dev; 66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 67 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 68 unsigned int addr; 69 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 70 71 addr = desc->sram_pte_offset + sdev->debug_box.offset + 72 offsetof(struct scratch_reg_conf, dma_desc); 73 74 switch (acp_data->pci_rev) { 75 case ACP70_PCI_ID: 76 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 77 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 78 break; 79 default: 80 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 81 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 82 } 83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 85 } 86 87 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 88 struct dma_descriptor *dscr_info) 89 { 90 struct snd_sof_dev *sdev = adata->dev; 91 unsigned int offset; 92 93 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 94 offsetof(struct scratch_reg_conf, dma_desc) + 95 idx * sizeof(struct dma_descriptor); 96 97 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 100 } 101 102 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 103 unsigned int idx, unsigned int dscr_count) 104 { 105 struct snd_sof_dev *sdev = adata->dev; 106 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 107 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 108 unsigned int val, status; 109 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 110 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 111 int ret; 112 113 switch (acp_data->pci_rev) { 114 case ACP70_PCI_ID: 115 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 116 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 117 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 118 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 119 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 120 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 121 break; 122 default: 123 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 124 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 125 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 126 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 127 acp_dma_prio_0 = ACP_DMA_PRIO_0; 128 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 129 } 130 131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 132 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 133 134 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 135 val & (1 << ch), ACP_REG_POLL_INTERVAL, 136 ACP_REG_POLL_TIMEOUT_US); 137 if (ret < 0) { 138 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 139 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 140 ch * sizeof(u32)); 141 142 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 143 return ret; 144 } 145 146 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 149 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 150 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 151 152 return ret; 153 } 154 155 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 156 unsigned int dscr_count, struct dma_descriptor *dscr_info) 157 { 158 struct snd_sof_dev *sdev = adata->dev; 159 int ret; 160 u16 dscr; 161 162 if (!dscr_info || !dscr_count) 163 return -EINVAL; 164 165 for (dscr = 0; dscr < dscr_count; dscr++) 166 configure_dma_descriptor(adata, dscr, dscr_info++); 167 168 ret = config_dma_channel(adata, ch, 0, dscr_count); 169 if (ret < 0) 170 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 171 172 return ret; 173 } 174 175 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 176 unsigned int dest_addr, int dsp_data_size) 177 { 178 struct snd_sof_dev *sdev = adata->dev; 179 unsigned int desc_count, index; 180 int ret; 181 182 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 183 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 184 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 185 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 186 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 187 if (dsp_data_size < ACP_PAGE_SIZE) 188 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 189 } 190 191 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 192 if (ret) 193 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 194 195 /* Clear descriptor array */ 196 for (index = 0; index < desc_count; index++) 197 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 198 199 return ret; 200 } 201 202 /* 203 * psp_mbox_ready- function to poll ready bit of psp mbox 204 * @adata: acp device data 205 * @ack: bool variable to check ready bit status or psp ack 206 */ 207 208 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 209 { 210 struct snd_sof_dev *sdev = adata->dev; 211 int ret; 212 u32 data; 213 214 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US, 215 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG); 216 if (!ret) 217 return 0; 218 219 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 220 221 if (ack) 222 return -ETIMEDOUT; 223 224 return -EBUSY; 225 } 226 227 /* 228 * psp_send_cmd - function to send psp command over mbox 229 * @adata: acp device data 230 * @cmd: non zero integer value for command type 231 */ 232 233 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 234 { 235 struct snd_sof_dev *sdev = adata->dev; 236 int ret; 237 u32 data; 238 239 if (!cmd) 240 return -EINVAL; 241 242 /* Get a non-zero Doorbell value from PSP */ 243 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, 244 adata->smn_dev, MP0_C2PMSG_73_REG); 245 246 if (ret) { 247 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 248 return ret; 249 } 250 251 /* Check if PSP is ready for new command */ 252 ret = psp_mbox_ready(adata, 0); 253 if (ret) 254 return ret; 255 256 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd); 257 258 /* Ring the Doorbell for PSP */ 259 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data); 260 261 /* Check MBOX ready as PSP ack */ 262 ret = psp_mbox_ready(adata, 1); 263 264 return ret; 265 } 266 267 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 268 unsigned int start_addr, unsigned int dest_addr, 269 unsigned int image_length) 270 { 271 struct snd_sof_dev *sdev = adata->dev; 272 unsigned int tx_count, fw_qualifier, val; 273 int ret; 274 275 if (!image_addr) { 276 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 277 return -EINVAL; 278 } 279 280 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 281 if (val & ACP_SHA_RUN) { 282 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 283 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 284 val, val & ACP_SHA_RESET, 285 ACP_REG_POLL_INTERVAL, 286 ACP_REG_POLL_TIMEOUT_US); 287 if (ret < 0) { 288 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 289 return ret; 290 } 291 } 292 293 if (adata->quirks && adata->quirks->signed_fw_image) 294 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 295 296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 297 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 298 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 299 300 /* psp_send_cmd only required for vangogh platform */ 301 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 302 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 303 /* Modify IRAM and DRAM size */ 304 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 305 if (ret) 306 return ret; 307 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 308 if (ret) 309 return ret; 310 } 311 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 312 313 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 314 tx_count, tx_count == image_length, 315 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 316 if (ret < 0) { 317 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 318 return ret; 319 } 320 321 /* psp_send_cmd only required for renoir platform*/ 322 if (adata->pci_rev == ACP_RN_PCI_ID) { 323 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 324 if (ret) 325 return ret; 326 } 327 328 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 329 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 330 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 331 if (ret < 0) { 332 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK); 333 dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n", 334 fw_qualifier, val); 335 return ret; 336 } 337 338 return 0; 339 } 340 341 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 342 { 343 struct snd_sof_dev *sdev = adata->dev; 344 unsigned int val; 345 int ret = 0; 346 347 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 348 if (val & ACP_DMA_CH_RUN) { 349 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val, 350 ACP_REG_POLL_INTERVAL, 351 ACP_DMA_COMPLETE_TIMEOUT_US); 352 if (ret < 0) 353 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 354 } 355 356 return ret; 357 } 358 359 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 360 { 361 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 362 int i, j; 363 364 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 365 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 366 } 367 368 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 369 { 370 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 371 int i, j; 372 373 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 374 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 375 } 376 377 static int acp_memory_init(struct snd_sof_dev *sdev) 378 { 379 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 380 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 381 382 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 383 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 384 init_dma_descriptor(adata); 385 386 return 0; 387 } 388 389 static irqreturn_t acp_irq_thread(int irq, void *context) 390 { 391 struct snd_sof_dev *sdev = context; 392 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 393 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 394 395 spin_lock_irq(&sdev->ipc_lock); 396 /* Wait until acquired HW Semaphore lock or timeout */ 397 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 398 ; 399 spin_unlock_irq(&sdev->ipc_lock); 400 401 if (!count) { 402 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 403 return IRQ_NONE; 404 } 405 406 sof_ops(sdev)->irq_thread(irq, sdev); 407 /* Unlock or Release HW Semaphore */ 408 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 409 410 return IRQ_HANDLED; 411 }; 412 413 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 414 { 415 struct amd_sdw_manager *amd_manager; 416 struct snd_sof_dev *sdev = dev_id; 417 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 418 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 419 unsigned int base = desc->dsp_intr_base; 420 unsigned int val; 421 int irq_flag = 0; 422 423 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 424 if (val & ACP_DSP_TO_HOST_IRQ) { 425 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 426 ACP_DSP_TO_HOST_IRQ); 427 return IRQ_WAKE_THREAD; 428 } 429 430 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 431 if (val & ACP_SDW0_IRQ_MASK) { 432 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 433 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 434 if (amd_manager) 435 schedule_work(&amd_manager->amd_sdw_irq_thread); 436 irq_flag = 1; 437 } 438 439 if (val & ACP_ERROR_IRQ_MASK) { 440 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 441 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 442 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 443 if (adata->pci_rev >= ACP_RMB_PCI_ID) 444 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 445 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 446 irq_flag = 1; 447 } 448 449 if (desc->ext_intr_stat1) { 450 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 451 if (val & ACP_SDW1_IRQ_MASK) { 452 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 453 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 454 ACP_SDW1_IRQ_MASK); 455 if (amd_manager) 456 schedule_work(&amd_manager->amd_sdw_irq_thread); 457 irq_flag = 1; 458 } 459 } 460 if (irq_flag) 461 return IRQ_HANDLED; 462 else 463 return IRQ_NONE; 464 } 465 466 static int acp_power_on(struct snd_sof_dev *sdev) 467 { 468 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 469 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 470 unsigned int base = desc->pgfsm_base; 471 unsigned int val; 472 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 473 int ret; 474 475 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 476 477 if (val == ACP_POWERED_ON) 478 return 0; 479 480 switch (adata->pci_rev) { 481 case ACP_RN_PCI_ID: 482 case ACP_VANGOGH_PCI_ID: 483 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 484 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 485 break; 486 case ACP_RMB_PCI_ID: 487 case ACP63_PCI_ID: 488 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 489 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 490 break; 491 case ACP70_PCI_ID: 492 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 493 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 494 break; 495 default: 496 return -EINVAL; 497 } 498 499 if (val & acp_pgfsm_status_mask) 500 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 501 acp_pgfsm_cntl_mask); 502 503 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 504 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 505 if (ret < 0) 506 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 507 508 return ret; 509 } 510 511 static int acp_reset(struct snd_sof_dev *sdev) 512 { 513 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 514 unsigned int val; 515 int ret; 516 517 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 518 519 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 520 val & ACP_SOFT_RESET_DONE_MASK, 521 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 522 if (ret < 0) { 523 dev_err(sdev->dev, "timeout asserting reset\n"); 524 return ret; 525 } 526 527 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 528 529 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 530 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 531 if (ret < 0) 532 dev_err(sdev->dev, "timeout in releasing reset\n"); 533 534 if (desc->acp_clkmux_sel) 535 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 536 537 if (desc->ext_intr_enb) 538 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 539 540 if (desc->ext_intr_cntl) 541 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 542 return ret; 543 } 544 545 static int acp_dsp_reset(struct snd_sof_dev *sdev) 546 { 547 unsigned int val; 548 int ret; 549 550 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 551 552 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 553 val & ACP_DSP_SOFT_RESET_DONE_MASK, 554 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 555 if (ret < 0) { 556 dev_err(sdev->dev, "timeout asserting reset\n"); 557 return ret; 558 } 559 560 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 561 562 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 563 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 564 if (ret < 0) 565 dev_err(sdev->dev, "timeout in releasing reset\n"); 566 567 return ret; 568 } 569 570 static int acp_init(struct snd_sof_dev *sdev) 571 { 572 int ret; 573 574 /* power on */ 575 ret = acp_power_on(sdev); 576 if (ret) { 577 dev_err(sdev->dev, "ACP power on failed\n"); 578 return ret; 579 } 580 581 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 582 /* Reset */ 583 return acp_reset(sdev); 584 } 585 586 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 587 { 588 struct acp_dev_data *acp_data; 589 u32 sdw0_en, sdw1_en; 590 591 acp_data = sdev->pdata->hw_pdata; 592 if (!acp_data->sdw) 593 return false; 594 595 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 596 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 597 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 598 return acp_data->sdw_en_stat; 599 } 600 601 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 602 { 603 struct acp_dev_data *acp_data; 604 int ret; 605 bool enable = false; 606 607 acp_data = sdev->pdata->hw_pdata; 608 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 609 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 610 * be reset to default values which will break the ClockStop Mode functionality. 611 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 612 * is selected. For the rest of the scenarios, apply acp reset sequence. 613 */ 614 if (check_acp_sdw_enable_status(sdev)) 615 return acp_dsp_reset(sdev); 616 617 ret = acp_reset(sdev); 618 if (ret) { 619 dev_err(sdev->dev, "ACP Reset failed\n"); 620 return ret; 621 } 622 if (acp_data->pci_rev == ACP70_PCI_ID) 623 enable = true; 624 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 625 626 return 0; 627 } 628 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON); 629 630 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 631 { 632 int ret; 633 struct acp_dev_data *acp_data; 634 635 acp_data = sdev->pdata->hw_pdata; 636 if (!acp_data->sdw_en_stat) { 637 ret = acp_init(sdev); 638 if (ret) { 639 dev_err(sdev->dev, "ACP Init failed\n"); 640 return ret; 641 } 642 return acp_memory_init(sdev); 643 } else { 644 return acp_dsp_reset(sdev); 645 } 646 } 647 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON); 648 649 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 650 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 651 { 652 struct acpi_device *sdw_dev; 653 struct acp_dev_data *acp_data; 654 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 655 656 if (!addr) 657 return -ENODEV; 658 659 acp_data = sdev->pdata->hw_pdata; 660 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 661 if (!sdw_dev) 662 return -ENODEV; 663 664 acp_data->info.handle = sdw_dev->handle; 665 acp_data->info.count = desc->sdw_max_link_count; 666 667 return amd_sdw_scan_controller(&acp_data->info); 668 } 669 670 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 671 { 672 struct acp_dev_data *acp_data; 673 struct sdw_amd_res sdw_res; 674 int ret; 675 676 acp_data = sdev->pdata->hw_pdata; 677 678 memset(&sdw_res, 0, sizeof(sdw_res)); 679 sdw_res.addr = acp_data->addr; 680 sdw_res.reg_range = acp_data->reg_range; 681 sdw_res.handle = acp_data->info.handle; 682 sdw_res.parent = sdev->dev; 683 sdw_res.dev = sdev->dev; 684 sdw_res.acp_lock = &acp_data->acp_lock; 685 sdw_res.count = acp_data->info.count; 686 sdw_res.link_mask = acp_data->info.link_mask; 687 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 688 689 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 690 if (ret) 691 dev_err(sdev->dev, "SoundWire probe failed\n"); 692 return ret; 693 } 694 695 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 696 { 697 struct acp_dev_data *acp_data; 698 699 acp_data = sdev->pdata->hw_pdata; 700 if (acp_data->sdw) 701 sdw_amd_exit(acp_data->sdw); 702 acp_data->sdw = NULL; 703 704 return 0; 705 } 706 707 #else 708 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 709 { 710 return 0; 711 } 712 713 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 714 { 715 return 0; 716 } 717 718 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 719 { 720 return 0; 721 } 722 #endif 723 724 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 725 { 726 struct pci_dev *pci = to_pci_dev(sdev->dev); 727 struct acp_dev_data *adata; 728 const struct sof_amd_acp_desc *chip; 729 const struct dmi_system_id *dmi_id; 730 unsigned int addr; 731 int ret; 732 733 chip = get_chip_info(sdev->pdata); 734 if (!chip) { 735 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 736 return -EIO; 737 } 738 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 739 GFP_KERNEL); 740 if (!adata) 741 return -ENOMEM; 742 743 adata->dev = sdev; 744 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 745 PLATFORM_DEVID_NONE, NULL, 0); 746 if (IS_ERR(adata->dmic_dev)) { 747 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 748 return PTR_ERR(adata->dmic_dev); 749 } 750 addr = pci_resource_start(pci, ACP_DSP_BAR); 751 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 752 if (!sdev->bar[ACP_DSP_BAR]) { 753 dev_err(sdev->dev, "ioremap error\n"); 754 ret = -ENXIO; 755 goto unregister_dev; 756 } 757 758 pci_set_master(pci); 759 adata->addr = addr; 760 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 761 adata->pci_rev = pci->revision; 762 mutex_init(&adata->acp_lock); 763 sdev->pdata->hw_pdata = adata; 764 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL); 765 if (!adata->smn_dev) { 766 dev_err(sdev->dev, "Failed to get host bridge device\n"); 767 ret = -ENODEV; 768 goto unregister_dev; 769 } 770 771 ret = acp_init(sdev); 772 if (ret < 0) 773 goto free_smn_dev; 774 775 sdev->ipc_irq = pci->irq; 776 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 777 IRQF_SHARED, "AudioDSP", sdev); 778 if (ret < 0) { 779 dev_err(sdev->dev, "failed to register IRQ %d\n", 780 sdev->ipc_irq); 781 goto free_smn_dev; 782 } 783 784 /* scan SoundWire capabilities exposed by DSDT */ 785 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 786 if (ret < 0) { 787 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 788 goto skip_soundwire; 789 } 790 ret = amd_sof_sdw_probe(sdev); 791 if (ret < 0) { 792 dev_err(sdev->dev, "error: SoundWire probe error\n"); 793 free_irq(sdev->ipc_irq, sdev); 794 pci_dev_put(adata->smn_dev); 795 return ret; 796 } 797 798 skip_soundwire: 799 sdev->dsp_box.offset = 0; 800 sdev->dsp_box.size = BOX_SIZE_512; 801 802 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 803 sdev->host_box.size = BOX_SIZE_512; 804 805 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 806 sdev->debug_box.size = BOX_SIZE_1024; 807 808 dmi_id = dmi_first_match(acp_sof_quirk_table); 809 if (dmi_id) { 810 adata->quirks = dmi_id->driver_data; 811 812 if (adata->quirks->signed_fw_image) { 813 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 814 "sof-%s-code.bin", 815 chip->name); 816 if (!adata->fw_code_bin) { 817 ret = -ENOMEM; 818 goto free_ipc_irq; 819 } 820 821 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 822 "sof-%s-data.bin", 823 chip->name); 824 if (!adata->fw_data_bin) { 825 ret = -ENOMEM; 826 goto free_ipc_irq; 827 } 828 } 829 } 830 831 adata->enable_fw_debug = enable_fw_debug; 832 acp_memory_init(sdev); 833 834 acp_dsp_stream_init(sdev); 835 836 return 0; 837 838 free_ipc_irq: 839 free_irq(sdev->ipc_irq, sdev); 840 free_smn_dev: 841 pci_dev_put(adata->smn_dev); 842 unregister_dev: 843 platform_device_unregister(adata->dmic_dev); 844 return ret; 845 } 846 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON); 847 848 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 849 { 850 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 851 852 if (adata->smn_dev) 853 pci_dev_put(adata->smn_dev); 854 855 if (adata->sdw) 856 amd_sof_sdw_exit(sdev); 857 858 if (sdev->ipc_irq) 859 free_irq(sdev->ipc_irq, sdev); 860 861 if (adata->dmic_dev) 862 platform_device_unregister(adata->dmic_dev); 863 864 acp_reset(sdev); 865 } 866 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); 867 868 MODULE_LICENSE("Dual BSD/GPL"); 869 MODULE_DESCRIPTION("AMD ACP sof driver"); 870 MODULE_IMPORT_NS(SOUNDWIRE_AMD_INIT); 871 MODULE_IMPORT_NS(SND_AMD_SOUNDWIRE_ACPI); 872