1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 // 3 // This file is provided under a dual BSD/GPLv2 license. When using or 4 // redistributing this file, you may do so under either license. 5 // 6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved. 7 // 8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com> 9 // Ajit Kumar Pandey <AjitKumar.Pandey@amd.com> 10 11 /* 12 * Hardware interface for generic AMD ACP processor 13 */ 14 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include "../ops.h" 20 #include "acp.h" 21 #include "acp-dsp-offset.h" 22 23 static bool enable_fw_debug; 24 module_param(enable_fw_debug, bool, 0444); 25 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug"); 26 27 static struct acp_quirk_entry quirk_valve_galileo = { 28 .signed_fw_image = true, 29 .skip_iram_dram_size_mod = true, 30 }; 31 32 const struct dmi_system_id acp_sof_quirk_table[] = { 33 { 34 /* Steam Deck OLED device */ 35 .matches = { 36 DMI_MATCH(DMI_SYS_VENDOR, "Valve"), 37 DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"), 38 }, 39 .driver_data = &quirk_valve_galileo, 40 }, 41 {} 42 }; 43 EXPORT_SYMBOL_GPL(acp_sof_quirk_table); 44 45 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data) 46 { 47 pci_write_config_dword(dev, 0x60, smn_addr); 48 pci_write_config_dword(dev, 0x64, data); 49 50 return 0; 51 } 52 53 static int smn_read(struct pci_dev *dev, u32 smn_addr) 54 { 55 u32 data = 0; 56 57 pci_write_config_dword(dev, 0x60, smn_addr); 58 pci_read_config_dword(dev, 0x64, &data); 59 60 return data; 61 } 62 63 static void init_dma_descriptor(struct acp_dev_data *adata) 64 { 65 struct snd_sof_dev *sdev = adata->dev; 66 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 67 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 68 unsigned int addr; 69 unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr; 70 71 addr = desc->sram_pte_offset + sdev->debug_box.offset + 72 offsetof(struct scratch_reg_conf, dma_desc); 73 74 switch (acp_data->pci_rev) { 75 case ACP70_PCI_ID: 76 acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR; 77 acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR; 78 break; 79 default: 80 acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR; 81 acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR; 82 } 83 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr); 84 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT); 85 } 86 87 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx, 88 struct dma_descriptor *dscr_info) 89 { 90 struct snd_sof_dev *sdev = adata->dev; 91 unsigned int offset; 92 93 offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset + 94 offsetof(struct scratch_reg_conf, dma_desc) + 95 idx * sizeof(struct dma_descriptor); 96 97 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr); 98 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr); 99 snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all); 100 } 101 102 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 103 unsigned int idx, unsigned int dscr_count) 104 { 105 struct snd_sof_dev *sdev = adata->dev; 106 struct acp_dev_data *acp_data = sdev->pdata->hw_pdata; 107 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 108 unsigned int val, status; 109 unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0; 110 unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0; 111 int ret; 112 113 switch (acp_data->pci_rev) { 114 case ACP70_PCI_ID: 115 acp_dma_cntl_0 = ACP70_DMA_CNTL_0; 116 acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS; 117 acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0; 118 acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0; 119 acp_dma_prio_0 = ACP70_DMA_PRIO_0; 120 acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0; 121 break; 122 default: 123 acp_dma_cntl_0 = ACP_DMA_CNTL_0; 124 acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS; 125 acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0; 126 acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0; 127 acp_dma_prio_0 = ACP_DMA_PRIO_0; 128 acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0; 129 } 130 131 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), 132 ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN); 133 134 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val, 135 val & (1 << ch), ACP_REG_POLL_INTERVAL, 136 ACP_REG_POLL_TIMEOUT_US); 137 if (ret < 0) { 138 status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat); 139 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 + 140 ch * sizeof(u32)); 141 142 dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status); 143 return ret; 144 } 145 146 snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0); 147 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count); 148 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx); 149 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0); 150 snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN); 151 152 return ret; 153 } 154 155 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch, 156 unsigned int dscr_count, struct dma_descriptor *dscr_info) 157 { 158 struct snd_sof_dev *sdev = adata->dev; 159 int ret; 160 u16 dscr; 161 162 if (!dscr_info || !dscr_count) 163 return -EINVAL; 164 165 for (dscr = 0; dscr < dscr_count; dscr++) 166 configure_dma_descriptor(adata, dscr, dscr_info++); 167 168 ret = config_dma_channel(adata, ch, 0, dscr_count); 169 if (ret < 0) 170 dev_err(sdev->dev, "config dma ch failed:%d\n", ret); 171 172 return ret; 173 } 174 175 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr, 176 unsigned int dest_addr, int dsp_data_size) 177 { 178 struct snd_sof_dev *sdev = adata->dev; 179 unsigned int desc_count, index; 180 int ret; 181 182 for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0; 183 desc_count++, dsp_data_size -= ACP_PAGE_SIZE) { 184 adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE; 185 adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE; 186 adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE; 187 if (dsp_data_size < ACP_PAGE_SIZE) 188 adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size; 189 } 190 191 ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info); 192 if (ret) 193 dev_err(sdev->dev, "acpbus_dma_start failed\n"); 194 195 /* Clear descriptor array */ 196 for (index = 0; index < desc_count; index++) 197 memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor)); 198 199 return ret; 200 } 201 202 /* 203 * psp_mbox_ready- function to poll ready bit of psp mbox 204 * @adata: acp device data 205 * @ack: bool variable to check ready bit status or psp ack 206 */ 207 208 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack) 209 { 210 struct snd_sof_dev *sdev = adata->dev; 211 int ret; 212 u32 data; 213 214 ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US, 215 ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG); 216 if (!ret) 217 return 0; 218 219 dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK); 220 221 if (ack) 222 return -ETIMEDOUT; 223 224 return -EBUSY; 225 } 226 227 /* 228 * psp_send_cmd - function to send psp command over mbox 229 * @adata: acp device data 230 * @cmd: non zero integer value for command type 231 */ 232 233 static int psp_send_cmd(struct acp_dev_data *adata, int cmd) 234 { 235 struct snd_sof_dev *sdev = adata->dev; 236 int ret; 237 u32 data; 238 239 if (!cmd) 240 return -EINVAL; 241 242 /* Get a non-zero Doorbell value from PSP */ 243 ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false, 244 adata->smn_dev, MP0_C2PMSG_73_REG); 245 246 if (ret) { 247 dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG); 248 return ret; 249 } 250 251 /* Check if PSP is ready for new command */ 252 ret = psp_mbox_ready(adata, 0); 253 if (ret) 254 return ret; 255 256 smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd); 257 258 /* Ring the Doorbell for PSP */ 259 smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data); 260 261 /* Check MBOX ready as PSP ack */ 262 ret = psp_mbox_ready(adata, 1); 263 264 return ret; 265 } 266 267 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr, 268 unsigned int start_addr, unsigned int dest_addr, 269 unsigned int image_length) 270 { 271 struct snd_sof_dev *sdev = adata->dev; 272 unsigned int tx_count, fw_qualifier, val; 273 int ret; 274 275 if (!image_addr) { 276 dev_err(sdev->dev, "SHA DMA image address is NULL\n"); 277 return -EINVAL; 278 } 279 280 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD); 281 if (val & ACP_SHA_RUN) { 282 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET); 283 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS, 284 val, val & ACP_SHA_RESET, 285 ACP_REG_POLL_INTERVAL, 286 ACP_REG_POLL_TIMEOUT_US); 287 if (ret < 0) { 288 dev_err(sdev->dev, "SHA DMA Failed to Reset\n"); 289 return ret; 290 } 291 } 292 293 if (adata->quirks && adata->quirks->signed_fw_image) 294 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER); 295 296 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr); 297 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr); 298 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length); 299 300 /* psp_send_cmd only required for vangogh platform */ 301 if (adata->pci_rev == ACP_VANGOGH_PCI_ID && 302 !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) { 303 /* Modify IRAM and DRAM size */ 304 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2); 305 if (ret) 306 return ret; 307 ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG); 308 if (ret) 309 return ret; 310 } 311 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN); 312 313 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT, 314 tx_count, tx_count == image_length, 315 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 316 if (ret < 0) { 317 dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count); 318 return ret; 319 } 320 321 /* psp_send_cmd only required for renoir platform*/ 322 if (adata->pci_rev == ACP_RN_PCI_ID) { 323 ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND); 324 if (ret) 325 return ret; 326 } 327 328 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER, 329 fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE, 330 ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US); 331 if (ret < 0) { 332 dev_err(sdev->dev, "PSP validation failed\n"); 333 return ret; 334 } 335 336 return 0; 337 } 338 339 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch) 340 { 341 struct snd_sof_dev *sdev = adata->dev; 342 unsigned int val; 343 int ret = 0; 344 345 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32)); 346 if (val & ACP_DMA_CH_RUN) { 347 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_STS, val, !val, 348 ACP_REG_POLL_INTERVAL, 349 ACP_DMA_COMPLETE_TIMEOUT_US); 350 if (ret < 0) 351 dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch); 352 } 353 354 return ret; 355 } 356 357 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes) 358 { 359 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 360 int i, j; 361 362 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 363 dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i); 364 } 365 366 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes) 367 { 368 unsigned int reg_offset = offset + ACP_SCRATCH_REG_0; 369 int i, j; 370 371 for (i = 0, j = 0; i < bytes; i = i + 4, j++) 372 snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]); 373 } 374 375 static int acp_memory_init(struct snd_sof_dev *sdev) 376 { 377 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 378 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 379 380 snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET, 381 ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK); 382 init_dma_descriptor(adata); 383 384 return 0; 385 } 386 387 static irqreturn_t acp_irq_thread(int irq, void *context) 388 { 389 struct snd_sof_dev *sdev = context; 390 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 391 unsigned int count = ACP_HW_SEM_RETRY_COUNT; 392 393 spin_lock_irq(&sdev->ipc_lock); 394 /* Wait until acquired HW Semaphore lock or timeout */ 395 while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count) 396 ; 397 spin_unlock_irq(&sdev->ipc_lock); 398 399 if (!count) { 400 dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__); 401 return IRQ_NONE; 402 } 403 404 sof_ops(sdev)->irq_thread(irq, sdev); 405 /* Unlock or Release HW Semaphore */ 406 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0); 407 408 return IRQ_HANDLED; 409 }; 410 411 static irqreturn_t acp_irq_handler(int irq, void *dev_id) 412 { 413 struct amd_sdw_manager *amd_manager; 414 struct snd_sof_dev *sdev = dev_id; 415 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 416 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 417 unsigned int base = desc->dsp_intr_base; 418 unsigned int val; 419 int irq_flag = 0; 420 421 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET); 422 if (val & ACP_DSP_TO_HOST_IRQ) { 423 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET, 424 ACP_DSP_TO_HOST_IRQ); 425 return IRQ_WAKE_THREAD; 426 } 427 428 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat); 429 if (val & ACP_SDW0_IRQ_MASK) { 430 amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev); 431 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK); 432 if (amd_manager) 433 schedule_work(&amd_manager->amd_sdw_irq_thread); 434 irq_flag = 1; 435 } 436 437 if (val & ACP_ERROR_IRQ_MASK) { 438 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK); 439 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0); 440 /* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */ 441 if (adata->pci_rev >= ACP_RMB_PCI_ID) 442 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0); 443 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0); 444 irq_flag = 1; 445 } 446 447 if (desc->ext_intr_stat1) { 448 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1); 449 if (val & ACP_SDW1_IRQ_MASK) { 450 amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev); 451 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1, 452 ACP_SDW1_IRQ_MASK); 453 if (amd_manager) 454 schedule_work(&amd_manager->amd_sdw_irq_thread); 455 irq_flag = 1; 456 } 457 } 458 if (irq_flag) 459 return IRQ_HANDLED; 460 else 461 return IRQ_NONE; 462 } 463 464 static int acp_power_on(struct snd_sof_dev *sdev) 465 { 466 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 467 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 468 unsigned int base = desc->pgfsm_base; 469 unsigned int val; 470 unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask; 471 int ret; 472 473 val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET); 474 475 if (val == ACP_POWERED_ON) 476 return 0; 477 478 switch (adata->pci_rev) { 479 case ACP_RN_PCI_ID: 480 case ACP_VANGOGH_PCI_ID: 481 acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK; 482 acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK; 483 break; 484 case ACP_RMB_PCI_ID: 485 case ACP63_PCI_ID: 486 acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK; 487 acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK; 488 break; 489 case ACP70_PCI_ID: 490 acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK; 491 acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK; 492 break; 493 default: 494 return -EINVAL; 495 } 496 497 if (val & acp_pgfsm_status_mask) 498 snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET, 499 acp_pgfsm_cntl_mask); 500 501 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val, 502 !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 503 if (ret < 0) 504 dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n"); 505 506 return ret; 507 } 508 509 static int acp_reset(struct snd_sof_dev *sdev) 510 { 511 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 512 unsigned int val; 513 int ret; 514 515 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET); 516 517 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 518 val & ACP_SOFT_RESET_DONE_MASK, 519 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 520 if (ret < 0) { 521 dev_err(sdev->dev, "timeout asserting reset\n"); 522 return ret; 523 } 524 525 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET); 526 527 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 528 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 529 if (ret < 0) 530 dev_err(sdev->dev, "timeout in releasing reset\n"); 531 532 if (desc->acp_clkmux_sel) 533 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK); 534 535 if (desc->ext_intr_enb) 536 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01); 537 538 if (desc->ext_intr_cntl) 539 snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK); 540 return ret; 541 } 542 543 static int acp_dsp_reset(struct snd_sof_dev *sdev) 544 { 545 unsigned int val; 546 int ret; 547 548 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET); 549 550 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, 551 val & ACP_DSP_SOFT_RESET_DONE_MASK, 552 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 553 if (ret < 0) { 554 dev_err(sdev->dev, "timeout asserting reset\n"); 555 return ret; 556 } 557 558 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET); 559 560 ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val, 561 ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US); 562 if (ret < 0) 563 dev_err(sdev->dev, "timeout in releasing reset\n"); 564 565 return ret; 566 } 567 568 static int acp_init(struct snd_sof_dev *sdev) 569 { 570 int ret; 571 572 /* power on */ 573 ret = acp_power_on(sdev); 574 if (ret) { 575 dev_err(sdev->dev, "ACP power on failed\n"); 576 return ret; 577 } 578 579 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01); 580 /* Reset */ 581 return acp_reset(sdev); 582 } 583 584 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 585 { 586 struct acp_dev_data *acp_data; 587 u32 sdw0_en, sdw1_en; 588 589 acp_data = sdev->pdata->hw_pdata; 590 if (!acp_data->sdw) 591 return false; 592 593 sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN); 594 sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN); 595 acp_data->sdw_en_stat = sdw0_en || sdw1_en; 596 return acp_data->sdw_en_stat; 597 } 598 599 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 600 { 601 struct acp_dev_data *acp_data; 602 int ret; 603 bool enable = false; 604 605 acp_data = sdev->pdata->hw_pdata; 606 /* When acp_reset() function is invoked, it will apply ACP SOFT reset and 607 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will 608 * be reset to default values which will break the ClockStop Mode functionality. 609 * Add a condition check to apply DSP reset when SoundWire ClockStop mode 610 * is selected. For the rest of the scenarios, apply acp reset sequence. 611 */ 612 if (check_acp_sdw_enable_status(sdev)) 613 return acp_dsp_reset(sdev); 614 615 ret = acp_reset(sdev); 616 if (ret) { 617 dev_err(sdev->dev, "ACP Reset failed\n"); 618 return ret; 619 } 620 if (acp_data->pci_rev == ACP70_PCI_ID) 621 enable = true; 622 snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable); 623 624 return 0; 625 } 626 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, SND_SOC_SOF_AMD_COMMON); 627 628 int amd_sof_acp_resume(struct snd_sof_dev *sdev) 629 { 630 int ret; 631 struct acp_dev_data *acp_data; 632 633 acp_data = sdev->pdata->hw_pdata; 634 if (!acp_data->sdw_en_stat) { 635 ret = acp_init(sdev); 636 if (ret) { 637 dev_err(sdev->dev, "ACP Init failed\n"); 638 return ret; 639 } 640 return acp_memory_init(sdev); 641 } else { 642 return acp_dsp_reset(sdev); 643 } 644 } 645 EXPORT_SYMBOL_NS(amd_sof_acp_resume, SND_SOC_SOF_AMD_COMMON); 646 647 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE) 648 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 649 { 650 struct acpi_device *sdw_dev; 651 struct acp_dev_data *acp_data; 652 const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); 653 654 if (!addr) 655 return -ENODEV; 656 657 acp_data = sdev->pdata->hw_pdata; 658 sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0); 659 if (!sdw_dev) 660 return -ENODEV; 661 662 acp_data->info.handle = sdw_dev->handle; 663 acp_data->info.count = desc->sdw_max_link_count; 664 665 return amd_sdw_scan_controller(&acp_data->info); 666 } 667 668 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 669 { 670 struct acp_dev_data *acp_data; 671 struct sdw_amd_res sdw_res; 672 int ret; 673 674 acp_data = sdev->pdata->hw_pdata; 675 676 memset(&sdw_res, 0, sizeof(sdw_res)); 677 sdw_res.addr = acp_data->addr; 678 sdw_res.reg_range = acp_data->reg_range; 679 sdw_res.handle = acp_data->info.handle; 680 sdw_res.parent = sdev->dev; 681 sdw_res.dev = sdev->dev; 682 sdw_res.acp_lock = &acp_data->acp_lock; 683 sdw_res.count = acp_data->info.count; 684 sdw_res.link_mask = acp_data->info.link_mask; 685 sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR]; 686 687 ret = sdw_amd_probe(&sdw_res, &acp_data->sdw); 688 if (ret) 689 dev_err(sdev->dev, "SoundWire probe failed\n"); 690 return ret; 691 } 692 693 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 694 { 695 struct acp_dev_data *acp_data; 696 697 acp_data = sdev->pdata->hw_pdata; 698 if (acp_data->sdw) 699 sdw_amd_exit(acp_data->sdw); 700 acp_data->sdw = NULL; 701 702 return 0; 703 } 704 705 #else 706 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr) 707 { 708 return 0; 709 } 710 711 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev) 712 { 713 return 0; 714 } 715 716 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev) 717 { 718 return 0; 719 } 720 #endif 721 722 int amd_sof_acp_probe(struct snd_sof_dev *sdev) 723 { 724 struct pci_dev *pci = to_pci_dev(sdev->dev); 725 struct acp_dev_data *adata; 726 const struct sof_amd_acp_desc *chip; 727 const struct dmi_system_id *dmi_id; 728 unsigned int addr; 729 int ret; 730 731 chip = get_chip_info(sdev->pdata); 732 if (!chip) { 733 dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device); 734 return -EIO; 735 } 736 adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data), 737 GFP_KERNEL); 738 if (!adata) 739 return -ENOMEM; 740 741 adata->dev = sdev; 742 adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec", 743 PLATFORM_DEVID_NONE, NULL, 0); 744 if (IS_ERR(adata->dmic_dev)) { 745 dev_err(sdev->dev, "failed to register platform for dmic codec\n"); 746 return PTR_ERR(adata->dmic_dev); 747 } 748 addr = pci_resource_start(pci, ACP_DSP_BAR); 749 sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR)); 750 if (!sdev->bar[ACP_DSP_BAR]) { 751 dev_err(sdev->dev, "ioremap error\n"); 752 ret = -ENXIO; 753 goto unregister_dev; 754 } 755 756 pci_set_master(pci); 757 adata->addr = addr; 758 adata->reg_range = chip->reg_end_addr - chip->reg_start_addr; 759 adata->pci_rev = pci->revision; 760 mutex_init(&adata->acp_lock); 761 sdev->pdata->hw_pdata = adata; 762 adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL); 763 if (!adata->smn_dev) { 764 dev_err(sdev->dev, "Failed to get host bridge device\n"); 765 ret = -ENODEV; 766 goto unregister_dev; 767 } 768 769 ret = acp_init(sdev); 770 if (ret < 0) 771 goto free_smn_dev; 772 773 sdev->ipc_irq = pci->irq; 774 ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread, 775 IRQF_SHARED, "AudioDSP", sdev); 776 if (ret < 0) { 777 dev_err(sdev->dev, "failed to register IRQ %d\n", 778 sdev->ipc_irq); 779 goto free_smn_dev; 780 } 781 782 /* scan SoundWire capabilities exposed by DSDT */ 783 ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr); 784 if (ret < 0) { 785 dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n"); 786 goto skip_soundwire; 787 } 788 ret = amd_sof_sdw_probe(sdev); 789 if (ret < 0) { 790 dev_err(sdev->dev, "error: SoundWire probe error\n"); 791 free_irq(sdev->ipc_irq, sdev); 792 pci_dev_put(adata->smn_dev); 793 return ret; 794 } 795 796 skip_soundwire: 797 sdev->dsp_box.offset = 0; 798 sdev->dsp_box.size = BOX_SIZE_512; 799 800 sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size; 801 sdev->host_box.size = BOX_SIZE_512; 802 803 sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size; 804 sdev->debug_box.size = BOX_SIZE_1024; 805 806 dmi_id = dmi_first_match(acp_sof_quirk_table); 807 if (dmi_id) { 808 adata->quirks = dmi_id->driver_data; 809 810 if (adata->quirks->signed_fw_image) { 811 adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 812 "sof-%s-code.bin", 813 chip->name); 814 if (!adata->fw_code_bin) { 815 ret = -ENOMEM; 816 goto free_ipc_irq; 817 } 818 819 adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL, 820 "sof-%s-data.bin", 821 chip->name); 822 if (!adata->fw_data_bin) { 823 ret = -ENOMEM; 824 goto free_ipc_irq; 825 } 826 } 827 } 828 829 adata->enable_fw_debug = enable_fw_debug; 830 acp_memory_init(sdev); 831 832 acp_dsp_stream_init(sdev); 833 834 return 0; 835 836 free_ipc_irq: 837 free_irq(sdev->ipc_irq, sdev); 838 free_smn_dev: 839 pci_dev_put(adata->smn_dev); 840 unregister_dev: 841 platform_device_unregister(adata->dmic_dev); 842 return ret; 843 } 844 EXPORT_SYMBOL_NS(amd_sof_acp_probe, SND_SOC_SOF_AMD_COMMON); 845 846 void amd_sof_acp_remove(struct snd_sof_dev *sdev) 847 { 848 struct acp_dev_data *adata = sdev->pdata->hw_pdata; 849 850 if (adata->smn_dev) 851 pci_dev_put(adata->smn_dev); 852 853 if (adata->sdw) 854 amd_sof_sdw_exit(sdev); 855 856 if (sdev->ipc_irq) 857 free_irq(sdev->ipc_irq, sdev); 858 859 if (adata->dmic_dev) 860 platform_device_unregister(adata->dmic_dev); 861 862 acp_reset(sdev); 863 } 864 EXPORT_SYMBOL_NS(amd_sof_acp_remove, SND_SOC_SOF_AMD_COMMON); 865 866 MODULE_LICENSE("Dual BSD/GPL"); 867 MODULE_DESCRIPTION("AMD ACP sof driver"); 868 MODULE_IMPORT_NS(SOUNDWIRE_AMD_INIT); 869 MODULE_IMPORT_NS(SND_AMD_SOUNDWIRE_ACPI); 870