1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Helper routines for R-Car sound ADG. 4 // 5 // Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> 6 7 #include <linux/clk-provider.h> 8 #include "rsnd.h" 9 10 #define CLKA 0 11 #define CLKB 1 12 #define CLKC 2 13 #define CLKI 3 14 #define CLKMAX 4 15 16 #define CLKOUT 0 17 #define CLKOUT1 1 18 #define CLKOUT2 2 19 #define CLKOUT3 3 20 #define CLKOUTMAX 4 21 22 #define BRRx_MASK(x) (0x3FF & x) 23 24 static struct rsnd_mod_ops adg_ops = { 25 .name = "adg", 26 }; 27 28 struct rsnd_adg { 29 struct clk *clk[CLKMAX]; 30 struct clk *clkout[CLKOUTMAX]; 31 struct clk_onecell_data onecell; 32 struct rsnd_mod mod; 33 int clk_rate[CLKMAX]; 34 u32 flags; 35 u32 ckr; 36 u32 rbga; 37 u32 rbgb; 38 39 int rbga_rate_for_441khz; /* RBGA */ 40 int rbgb_rate_for_48khz; /* RBGB */ 41 }; 42 43 #define LRCLK_ASYNC (1 << 0) 44 #define AUDIO_OUT_48 (1 << 1) 45 46 #define for_each_rsnd_clk(pos, adg, i) \ 47 for (i = 0; \ 48 (i < CLKMAX) && \ 49 ((pos) = adg->clk[i]); \ 50 i++) 51 #define for_each_rsnd_clkout(pos, adg, i) \ 52 for (i = 0; \ 53 (i < CLKOUTMAX) && \ 54 ((pos) = adg->clkout[i]); \ 55 i++) 56 #define rsnd_priv_to_adg(priv) ((struct rsnd_adg *)(priv)->adg) 57 58 static const char * const clk_name[] = { 59 [CLKA] = "clk_a", 60 [CLKB] = "clk_b", 61 [CLKC] = "clk_c", 62 [CLKI] = "clk_i", 63 }; 64 65 static u32 rsnd_adg_calculate_rbgx(unsigned long div) 66 { 67 int i; 68 69 if (!div) 70 return 0; 71 72 for (i = 3; i >= 0; i--) { 73 int ratio = 2 << (i * 2); 74 if (0 == (div % ratio)) 75 return (u32)((i << 8) | ((div / ratio) - 1)); 76 } 77 78 return ~0; 79 } 80 81 static u32 rsnd_adg_ssi_ws_timing_gen2(struct rsnd_dai_stream *io) 82 { 83 struct rsnd_mod *ssi_mod = rsnd_io_to_mod_ssi(io); 84 int id = rsnd_mod_id(ssi_mod); 85 int ws = id; 86 87 if (rsnd_ssi_is_pin_sharing(io)) { 88 switch (id) { 89 case 1: 90 case 2: 91 case 9: 92 ws = 0; 93 break; 94 case 4: 95 ws = 3; 96 break; 97 case 8: 98 ws = 7; 99 break; 100 } 101 } 102 103 return (0x6 + ws) << 8; 104 } 105 106 static void __rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 107 struct rsnd_dai_stream *io, 108 unsigned int target_rate, 109 unsigned int *target_val, 110 unsigned int *target_en) 111 { 112 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 113 struct device *dev = rsnd_priv_to_dev(priv); 114 int sel; 115 unsigned int val, en; 116 unsigned int min, diff; 117 unsigned int sel_rate[] = { 118 adg->clk_rate[CLKA], /* 0000: CLKA */ 119 adg->clk_rate[CLKB], /* 0001: CLKB */ 120 adg->clk_rate[CLKC], /* 0010: CLKC */ 121 adg->rbga_rate_for_441khz, /* 0011: RBGA */ 122 adg->rbgb_rate_for_48khz, /* 0100: RBGB */ 123 }; 124 125 min = ~0; 126 val = 0; 127 en = 0; 128 for (sel = 0; sel < ARRAY_SIZE(sel_rate); sel++) { 129 int idx = 0; 130 int step = 2; 131 int div; 132 133 if (!sel_rate[sel]) 134 continue; 135 136 for (div = 2; div <= 98304; div += step) { 137 diff = abs(target_rate - sel_rate[sel] / div); 138 if (min > diff) { 139 val = (sel << 8) | idx; 140 min = diff; 141 en = 1 << (sel + 1); /* fixme */ 142 } 143 144 /* 145 * step of 0_0000 / 0_0001 / 0_1101 146 * are out of order 147 */ 148 if ((idx > 2) && (idx % 2)) 149 step *= 2; 150 if (idx == 0x1c) { 151 div += step; 152 step *= 2; 153 } 154 idx++; 155 } 156 } 157 158 if (min == ~0) { 159 dev_err(dev, "no Input clock\n"); 160 return; 161 } 162 163 *target_val = val; 164 if (target_en) 165 *target_en = en; 166 } 167 168 static void rsnd_adg_get_timesel_ratio(struct rsnd_priv *priv, 169 struct rsnd_dai_stream *io, 170 unsigned int in_rate, 171 unsigned int out_rate, 172 u32 *in, u32 *out, u32 *en) 173 { 174 struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io); 175 unsigned int target_rate; 176 u32 *target_val; 177 u32 _in; 178 u32 _out; 179 u32 _en; 180 181 /* default = SSI WS */ 182 _in = 183 _out = rsnd_adg_ssi_ws_timing_gen2(io); 184 185 target_rate = 0; 186 target_val = NULL; 187 _en = 0; 188 if (runtime->rate != in_rate) { 189 target_rate = out_rate; 190 target_val = &_out; 191 } else if (runtime->rate != out_rate) { 192 target_rate = in_rate; 193 target_val = &_in; 194 } 195 196 if (target_rate) 197 __rsnd_adg_get_timesel_ratio(priv, io, 198 target_rate, 199 target_val, &_en); 200 201 if (in) 202 *in = _in; 203 if (out) 204 *out = _out; 205 if (en) 206 *en = _en; 207 } 208 209 int rsnd_adg_set_cmd_timsel_gen2(struct rsnd_mod *cmd_mod, 210 struct rsnd_dai_stream *io) 211 { 212 struct rsnd_priv *priv = rsnd_mod_to_priv(cmd_mod); 213 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 214 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 215 int id = rsnd_mod_id(cmd_mod); 216 int shift = (id % 2) ? 16 : 0; 217 u32 mask, val; 218 219 rsnd_adg_get_timesel_ratio(priv, io, 220 rsnd_src_get_in_rate(priv, io), 221 rsnd_src_get_out_rate(priv, io), 222 NULL, &val, NULL); 223 224 val = val << shift; 225 mask = 0x0f1f << shift; 226 227 rsnd_mod_bset(adg_mod, CMDOUT_TIMSEL, mask, val); 228 229 return 0; 230 } 231 232 int rsnd_adg_set_src_timesel_gen2(struct rsnd_mod *src_mod, 233 struct rsnd_dai_stream *io, 234 unsigned int in_rate, 235 unsigned int out_rate) 236 { 237 struct rsnd_priv *priv = rsnd_mod_to_priv(src_mod); 238 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 239 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 240 u32 in, out; 241 u32 mask, en; 242 int id = rsnd_mod_id(src_mod); 243 int shift = (id % 2) ? 16 : 0; 244 245 rsnd_mod_confirm_src(src_mod); 246 247 rsnd_adg_get_timesel_ratio(priv, io, 248 in_rate, out_rate, 249 &in, &out, &en); 250 251 in = in << shift; 252 out = out << shift; 253 mask = 0x0f1f << shift; 254 255 rsnd_mod_bset(adg_mod, SRCIN_TIMSEL(id / 2), mask, in); 256 rsnd_mod_bset(adg_mod, SRCOUT_TIMSEL(id / 2), mask, out); 257 258 if (en) 259 rsnd_mod_bset(adg_mod, DIV_EN, en, en); 260 261 return 0; 262 } 263 264 static void rsnd_adg_set_ssi_clk(struct rsnd_mod *ssi_mod, u32 val) 265 { 266 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 267 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 268 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 269 struct device *dev = rsnd_priv_to_dev(priv); 270 int id = rsnd_mod_id(ssi_mod); 271 int shift = (id % 4) * 8; 272 u32 mask = 0xFF << shift; 273 274 rsnd_mod_confirm_ssi(ssi_mod); 275 276 val = val << shift; 277 278 /* 279 * SSI 8 is not connected to ADG. 280 * it works with SSI 7 281 */ 282 if (id == 8) 283 return; 284 285 rsnd_mod_bset(adg_mod, AUDIO_CLK_SEL(id / 4), mask, val); 286 287 dev_dbg(dev, "AUDIO_CLK_SEL is 0x%x\n", val); 288 } 289 290 int rsnd_adg_clk_query(struct rsnd_priv *priv, unsigned int rate) 291 { 292 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 293 struct clk *clk; 294 int i; 295 int sel_table[] = { 296 [CLKA] = 0x1, 297 [CLKB] = 0x2, 298 [CLKC] = 0x3, 299 [CLKI] = 0x0, 300 }; 301 302 /* 303 * find suitable clock from 304 * AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC/AUDIO_CLKI. 305 */ 306 for_each_rsnd_clk(clk, adg, i) { 307 if (rate == adg->clk_rate[i]) 308 return sel_table[i]; 309 } 310 311 /* 312 * find divided clock from BRGA/BRGB 313 */ 314 if (rate == adg->rbga_rate_for_441khz) 315 return 0x10; 316 317 if (rate == adg->rbgb_rate_for_48khz) 318 return 0x20; 319 320 return -EIO; 321 } 322 323 int rsnd_adg_ssi_clk_stop(struct rsnd_mod *ssi_mod) 324 { 325 rsnd_adg_set_ssi_clk(ssi_mod, 0); 326 327 return 0; 328 } 329 330 int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) 331 { 332 struct rsnd_priv *priv = rsnd_mod_to_priv(ssi_mod); 333 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 334 struct device *dev = rsnd_priv_to_dev(priv); 335 struct rsnd_mod *adg_mod = rsnd_mod_get(adg); 336 int data; 337 u32 ckr = 0; 338 339 data = rsnd_adg_clk_query(priv, rate); 340 if (data < 0) 341 return data; 342 343 rsnd_adg_set_ssi_clk(ssi_mod, data); 344 345 if (rsnd_flags_has(adg, LRCLK_ASYNC)) { 346 if (rsnd_flags_has(adg, AUDIO_OUT_48)) 347 ckr = 0x80000000; 348 } else { 349 if (0 == (rate % 8000)) 350 ckr = 0x80000000; 351 } 352 353 rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); 354 rsnd_mod_write(adg_mod, BRRA, adg->rbga); 355 rsnd_mod_write(adg_mod, BRRB, adg->rbgb); 356 357 dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", 358 (ckr) ? 'B' : 'A', 359 (ckr) ? adg->rbgb_rate_for_48khz : 360 adg->rbga_rate_for_441khz); 361 362 return 0; 363 } 364 365 void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) 366 { 367 struct rsnd_adg *adg = rsnd_priv_to_adg(priv); 368 struct device *dev = rsnd_priv_to_dev(priv); 369 struct clk *clk; 370 int i; 371 372 for_each_rsnd_clk(clk, adg, i) { 373 if (enable) { 374 int ret = clk_prepare_enable(clk); 375 376 /* 377 * We shouldn't use clk_get_rate() under 378 * atomic context. Let's keep it when 379 * rsnd_adg_clk_enable() was called 380 */ 381 adg->clk_rate[i] = 0; 382 if (ret < 0) 383 dev_warn(dev, "can't use clk %d\n", i); 384 else 385 adg->clk_rate[i] = clk_get_rate(clk); 386 } else { 387 if (adg->clk_rate[i]) 388 clk_disable_unprepare(clk); 389 adg->clk_rate[i] = 0; 390 } 391 } 392 } 393 394 static void rsnd_adg_get_clkin(struct rsnd_priv *priv, 395 struct rsnd_adg *adg) 396 { 397 struct device *dev = rsnd_priv_to_dev(priv); 398 int i; 399 400 for (i = 0; i < CLKMAX; i++) { 401 struct clk *clk = devm_clk_get(dev, clk_name[i]); 402 403 adg->clk[i] = IS_ERR(clk) ? NULL : clk; 404 } 405 } 406 407 static void rsnd_adg_get_clkout(struct rsnd_priv *priv, 408 struct rsnd_adg *adg) 409 { 410 struct clk *clk; 411 struct device *dev = rsnd_priv_to_dev(priv); 412 struct device_node *np = dev->of_node; 413 struct property *prop; 414 u32 ckr, rbgx, rbga, rbgb; 415 u32 rate, div; 416 #define REQ_SIZE 2 417 u32 req_rate[REQ_SIZE] = {}; 418 uint32_t count = 0; 419 unsigned long req_48kHz_rate, req_441kHz_rate; 420 int i, req_size; 421 const char *parent_clk_name = NULL; 422 static const char * const clkout_name[] = { 423 [CLKOUT] = "audio_clkout", 424 [CLKOUT1] = "audio_clkout1", 425 [CLKOUT2] = "audio_clkout2", 426 [CLKOUT3] = "audio_clkout3", 427 }; 428 int brg_table[] = { 429 [CLKA] = 0x0, 430 [CLKB] = 0x1, 431 [CLKC] = 0x4, 432 [CLKI] = 0x2, 433 }; 434 435 ckr = 0; 436 rbga = 2; /* default 1/6 */ 437 rbgb = 2; /* default 1/6 */ 438 439 /* 440 * ADG supports BRRA/BRRB output only 441 * this means all clkout0/1/2/3 will be same rate 442 */ 443 prop = of_find_property(np, "clock-frequency", NULL); 444 if (!prop) 445 goto rsnd_adg_get_clkout_end; 446 447 req_size = prop->length / sizeof(u32); 448 if (req_size > REQ_SIZE) { 449 dev_err(dev, 450 "too many clock-frequency, use top %d\n", REQ_SIZE); 451 req_size = REQ_SIZE; 452 } 453 454 of_property_read_u32_array(np, "clock-frequency", req_rate, req_size); 455 req_48kHz_rate = 0; 456 req_441kHz_rate = 0; 457 for (i = 0; i < req_size; i++) { 458 if (0 == (req_rate[i] % 44100)) 459 req_441kHz_rate = req_rate[i]; 460 if (0 == (req_rate[i] % 48000)) 461 req_48kHz_rate = req_rate[i]; 462 } 463 464 if (req_rate[0] % 48000 == 0) 465 rsnd_flags_set(adg, AUDIO_OUT_48); 466 467 if (of_get_property(np, "clkout-lr-asynchronous", NULL)) 468 rsnd_flags_set(adg, LRCLK_ASYNC); 469 470 /* 471 * This driver is assuming that AUDIO_CLKA/AUDIO_CLKB/AUDIO_CLKC 472 * have 44.1kHz or 48kHz base clocks for now. 473 * 474 * SSI itself can divide parent clock by 1/1 - 1/16 475 * see 476 * rsnd_adg_ssi_clk_try_start() 477 * rsnd_ssi_master_clk_start() 478 */ 479 adg->rbga_rate_for_441khz = 0; 480 adg->rbgb_rate_for_48khz = 0; 481 for_each_rsnd_clk(clk, adg, i) { 482 rate = clk_get_rate(clk); 483 484 if (0 == rate) /* not used */ 485 continue; 486 487 /* RBGA */ 488 if (!adg->rbga_rate_for_441khz && (0 == rate % 44100)) { 489 div = 6; 490 if (req_441kHz_rate) 491 div = rate / req_441kHz_rate; 492 rbgx = rsnd_adg_calculate_rbgx(div); 493 if (BRRx_MASK(rbgx) == rbgx) { 494 rbga = rbgx; 495 adg->rbga_rate_for_441khz = rate / div; 496 ckr |= brg_table[i] << 20; 497 if (req_441kHz_rate && 498 !rsnd_flags_has(adg, AUDIO_OUT_48)) 499 parent_clk_name = __clk_get_name(clk); 500 } 501 } 502 503 /* RBGB */ 504 if (!adg->rbgb_rate_for_48khz && (0 == rate % 48000)) { 505 div = 6; 506 if (req_48kHz_rate) 507 div = rate / req_48kHz_rate; 508 rbgx = rsnd_adg_calculate_rbgx(div); 509 if (BRRx_MASK(rbgx) == rbgx) { 510 rbgb = rbgx; 511 adg->rbgb_rate_for_48khz = rate / div; 512 ckr |= brg_table[i] << 16; 513 if (req_48kHz_rate && 514 rsnd_flags_has(adg, AUDIO_OUT_48)) 515 parent_clk_name = __clk_get_name(clk); 516 } 517 } 518 } 519 520 /* 521 * ADG supports BRRA/BRRB output only. 522 * this means all clkout0/1/2/3 will be * same rate 523 */ 524 525 of_property_read_u32(np, "#clock-cells", &count); 526 /* 527 * for clkout 528 */ 529 if (!count) { 530 clk = clk_register_fixed_rate(dev, clkout_name[CLKOUT], 531 parent_clk_name, 0, req_rate[0]); 532 if (!IS_ERR(clk)) { 533 adg->clkout[CLKOUT] = clk; 534 of_clk_add_provider(np, of_clk_src_simple_get, clk); 535 } 536 } 537 /* 538 * for clkout0/1/2/3 539 */ 540 else { 541 for (i = 0; i < CLKOUTMAX; i++) { 542 clk = clk_register_fixed_rate(dev, clkout_name[i], 543 parent_clk_name, 0, 544 req_rate[0]); 545 if (!IS_ERR(clk)) 546 adg->clkout[i] = clk; 547 } 548 adg->onecell.clks = adg->clkout; 549 adg->onecell.clk_num = CLKOUTMAX; 550 of_clk_add_provider(np, of_clk_src_onecell_get, 551 &adg->onecell); 552 } 553 554 rsnd_adg_get_clkout_end: 555 adg->ckr = ckr; 556 adg->rbga = rbga; 557 adg->rbgb = rbgb; 558 } 559 560 #ifdef DEBUG 561 static void rsnd_adg_clk_dbg_info(struct rsnd_priv *priv, struct rsnd_adg *adg) 562 { 563 struct device *dev = rsnd_priv_to_dev(priv); 564 struct clk *clk; 565 int i; 566 567 for_each_rsnd_clk(clk, adg, i) 568 dev_dbg(dev, "%s : %pa : %ld\n", 569 clk_name[i], clk, clk_get_rate(clk)); 570 571 dev_dbg(dev, "BRGCKR = 0x%08x, BRRA/BRRB = 0x%x/0x%x\n", 572 adg->ckr, adg->rbga, adg->rbgb); 573 dev_dbg(dev, "BRGA (for 44100 base) = %d\n", adg->rbga_rate_for_441khz); 574 dev_dbg(dev, "BRGB (for 48000 base) = %d\n", adg->rbgb_rate_for_48khz); 575 576 /* 577 * Actual CLKOUT will be exchanged in rsnd_adg_ssi_clk_try_start() 578 * by BRGCKR::BRGCKR_31 579 */ 580 for_each_rsnd_clkout(clk, adg, i) 581 dev_dbg(dev, "clkout %d : %pa : %ld\n", i, 582 clk, clk_get_rate(clk)); 583 } 584 #else 585 #define rsnd_adg_clk_dbg_info(priv, adg) 586 #endif 587 588 int rsnd_adg_probe(struct rsnd_priv *priv) 589 { 590 struct rsnd_adg *adg; 591 struct device *dev = rsnd_priv_to_dev(priv); 592 int ret; 593 594 adg = devm_kzalloc(dev, sizeof(*adg), GFP_KERNEL); 595 if (!adg) 596 return -ENOMEM; 597 598 ret = rsnd_mod_init(priv, &adg->mod, &adg_ops, 599 NULL, 0, 0); 600 if (ret) 601 return ret; 602 603 rsnd_adg_get_clkin(priv, adg); 604 rsnd_adg_get_clkout(priv, adg); 605 rsnd_adg_clk_dbg_info(priv, adg); 606 607 priv->adg = adg; 608 609 rsnd_adg_clk_enable(priv); 610 611 return 0; 612 } 613 614 void rsnd_adg_remove(struct rsnd_priv *priv) 615 { 616 struct device *dev = rsnd_priv_to_dev(priv); 617 struct device_node *np = dev->of_node; 618 struct rsnd_adg *adg = priv->adg; 619 struct clk *clk; 620 int i; 621 622 for_each_rsnd_clkout(clk, adg, i) 623 if (adg->clkout[i]) 624 clk_unregister_fixed_rate(adg->clkout[i]); 625 626 of_clk_del_provider(np); 627 628 rsnd_adg_clk_disable(priv); 629 } 630