1 /* 2 * Fifo-attached Serial Interface (FSI) support for SH7724 3 * 4 * Copyright (C) 2009 Renesas Solutions Corp. 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 6 * 7 * Based on ssi.c 8 * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/delay.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/of_device.h> 21 #include <linux/scatterlist.h> 22 #include <linux/sh_dma.h> 23 #include <linux/slab.h> 24 #include <linux/module.h> 25 #include <linux/workqueue.h> 26 #include <sound/soc.h> 27 #include <sound/pcm_params.h> 28 #include <sound/sh_fsi.h> 29 30 /* PortA/PortB register */ 31 #define REG_DO_FMT 0x0000 32 #define REG_DOFF_CTL 0x0004 33 #define REG_DOFF_ST 0x0008 34 #define REG_DI_FMT 0x000C 35 #define REG_DIFF_CTL 0x0010 36 #define REG_DIFF_ST 0x0014 37 #define REG_CKG1 0x0018 38 #define REG_CKG2 0x001C 39 #define REG_DIDT 0x0020 40 #define REG_DODT 0x0024 41 #define REG_MUTE_ST 0x0028 42 #define REG_OUT_DMAC 0x002C 43 #define REG_OUT_SEL 0x0030 44 #define REG_IN_DMAC 0x0038 45 46 /* master register */ 47 #define MST_CLK_RST 0x0210 48 #define MST_SOFT_RST 0x0214 49 #define MST_FIFO_SZ 0x0218 50 51 /* core register (depend on FSI version) */ 52 #define A_MST_CTLR 0x0180 53 #define B_MST_CTLR 0x01A0 54 #define CPU_INT_ST 0x01F4 55 #define CPU_IEMSK 0x01F8 56 #define CPU_IMSK 0x01FC 57 #define INT_ST 0x0200 58 #define IEMSK 0x0204 59 #define IMSK 0x0208 60 61 /* DO_FMT */ 62 /* DI_FMT */ 63 #define CR_BWS_MASK (0x3 << 20) /* FSI2 */ 64 #define CR_BWS_24 (0x0 << 20) /* FSI2 */ 65 #define CR_BWS_16 (0x1 << 20) /* FSI2 */ 66 #define CR_BWS_20 (0x2 << 20) /* FSI2 */ 67 68 #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */ 69 #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */ 70 #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */ 71 72 #define CR_MONO (0x0 << 4) 73 #define CR_MONO_D (0x1 << 4) 74 #define CR_PCM (0x2 << 4) 75 #define CR_I2S (0x3 << 4) 76 #define CR_TDM (0x4 << 4) 77 #define CR_TDM_D (0x5 << 4) 78 79 /* OUT_DMAC */ 80 /* IN_DMAC */ 81 #define VDMD_MASK (0x3 << 4) 82 #define VDMD_FRONT (0x0 << 4) /* Package in front */ 83 #define VDMD_BACK (0x1 << 4) /* Package in back */ 84 #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */ 85 86 #define DMA_ON (0x1 << 0) 87 88 /* DOFF_CTL */ 89 /* DIFF_CTL */ 90 #define IRQ_HALF 0x00100000 91 #define FIFO_CLR 0x00000001 92 93 /* DOFF_ST */ 94 #define ERR_OVER 0x00000010 95 #define ERR_UNDER 0x00000001 96 #define ST_ERR (ERR_OVER | ERR_UNDER) 97 98 /* CKG1 */ 99 #define ACKMD_MASK 0x00007000 100 #define BPFMD_MASK 0x00000700 101 #define DIMD (1 << 4) 102 #define DOMD (1 << 0) 103 104 /* A/B MST_CTLR */ 105 #define BP (1 << 4) /* Fix the signal of Biphase output */ 106 #define SE (1 << 0) /* Fix the master clock */ 107 108 /* CLK_RST */ 109 #define CRB (1 << 4) 110 #define CRA (1 << 0) 111 112 /* IO SHIFT / MACRO */ 113 #define BI_SHIFT 12 114 #define BO_SHIFT 8 115 #define AI_SHIFT 4 116 #define AO_SHIFT 0 117 #define AB_IO(param, shift) (param << shift) 118 119 /* SOFT_RST */ 120 #define PBSR (1 << 12) /* Port B Software Reset */ 121 #define PASR (1 << 8) /* Port A Software Reset */ 122 #define IR (1 << 4) /* Interrupt Reset */ 123 #define FSISR (1 << 0) /* Software Reset */ 124 125 /* OUT_SEL (FSI2) */ 126 #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */ 127 /* 1: Biphase and serial */ 128 129 /* FIFO_SZ */ 130 #define FIFO_SZ_MASK 0x7 131 132 #define FSI_RATES SNDRV_PCM_RATE_8000_96000 133 134 #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE) 135 136 /* 137 * bus options 138 * 139 * 0x000000BA 140 * 141 * A : sample widtht 16bit setting 142 * B : sample widtht 24bit setting 143 */ 144 145 #define SHIFT_16DATA 0 146 #define SHIFT_24DATA 4 147 148 #define PACKAGE_24BITBUS_BACK 0 149 #define PACKAGE_24BITBUS_FRONT 1 150 #define PACKAGE_16BITBUS_STREAM 2 151 152 #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA) 153 #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF) 154 155 /* 156 * FSI driver use below type name for variable 157 * 158 * xxx_num : number of data 159 * xxx_pos : position of data 160 * xxx_capa : capacity of data 161 */ 162 163 /* 164 * period/frame/sample image 165 * 166 * ex) PCM (2ch) 167 * 168 * period pos period pos 169 * [n] [n + 1] 170 * |<-------------------- period--------------------->| 171 * ==|============================================ ... =|== 172 * | | 173 * ||<----- frame ----->|<------ frame ----->| ... | 174 * |+--------------------+--------------------+- ... | 175 * ||[ sample ][ sample ]|[ sample ][ sample ]| ... | 176 * |+--------------------+--------------------+- ... | 177 * ==|============================================ ... =|== 178 */ 179 180 /* 181 * FSI FIFO image 182 * 183 * | | 184 * | | 185 * | [ sample ] | 186 * | [ sample ] | 187 * | [ sample ] | 188 * | [ sample ] | 189 * --> go to codecs 190 */ 191 192 /* 193 * FSI clock 194 * 195 * FSIxCLK [CPG] (ick) -------> | 196 * |-> FSI_DIV (div)-> FSI2 197 * FSIxCK [external] (xck) ---> | 198 */ 199 200 /* 201 * struct 202 */ 203 204 struct fsi_stream_handler; 205 struct fsi_stream { 206 207 /* 208 * these are initialized by fsi_stream_init() 209 */ 210 struct snd_pcm_substream *substream; 211 int fifo_sample_capa; /* sample capacity of FSI FIFO */ 212 int buff_sample_capa; /* sample capacity of ALSA buffer */ 213 int buff_sample_pos; /* sample position of ALSA buffer */ 214 int period_samples; /* sample number / 1 period */ 215 int period_pos; /* current period position */ 216 int sample_width; /* sample width */ 217 int uerr_num; 218 int oerr_num; 219 220 /* 221 * bus options 222 */ 223 u32 bus_option; 224 225 /* 226 * thse are initialized by fsi_handler_init() 227 */ 228 struct fsi_stream_handler *handler; 229 struct fsi_priv *priv; 230 231 /* 232 * these are for DMAEngine 233 */ 234 struct dma_chan *chan; 235 struct sh_dmae_slave slave; /* see fsi_handler_init() */ 236 struct work_struct work; 237 dma_addr_t dma; 238 }; 239 240 struct fsi_clk { 241 /* see [FSI clock] */ 242 struct clk *own; 243 struct clk *xck; 244 struct clk *ick; 245 struct clk *div; 246 int (*set_rate)(struct device *dev, 247 struct fsi_priv *fsi); 248 249 unsigned long rate; 250 unsigned int count; 251 }; 252 253 struct fsi_priv { 254 void __iomem *base; 255 struct fsi_master *master; 256 257 struct fsi_stream playback; 258 struct fsi_stream capture; 259 260 struct fsi_clk clock; 261 262 u32 fmt; 263 264 int chan_num:16; 265 int clk_master:1; 266 int clk_cpg:1; 267 int spdif:1; 268 int enable_stream:1; 269 int bit_clk_inv:1; 270 int lr_clk_inv:1; 271 }; 272 273 struct fsi_stream_handler { 274 int (*init)(struct fsi_priv *fsi, struct fsi_stream *io); 275 int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io); 276 int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev); 277 int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io); 278 int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io); 279 int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io, 280 int enable); 281 }; 282 #define fsi_stream_handler_call(io, func, args...) \ 283 (!(io) ? -ENODEV : \ 284 !((io)->handler->func) ? 0 : \ 285 (io)->handler->func(args)) 286 287 struct fsi_core { 288 int ver; 289 290 u32 int_st; 291 u32 iemsk; 292 u32 imsk; 293 u32 a_mclk; 294 u32 b_mclk; 295 }; 296 297 struct fsi_master { 298 void __iomem *base; 299 struct fsi_priv fsia; 300 struct fsi_priv fsib; 301 const struct fsi_core *core; 302 spinlock_t lock; 303 }; 304 305 static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io); 306 307 /* 308 * basic read write function 309 */ 310 311 static void __fsi_reg_write(u32 __iomem *reg, u32 data) 312 { 313 /* valid data area is 24bit */ 314 data &= 0x00ffffff; 315 316 __raw_writel(data, reg); 317 } 318 319 static u32 __fsi_reg_read(u32 __iomem *reg) 320 { 321 return __raw_readl(reg); 322 } 323 324 static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data) 325 { 326 u32 val = __fsi_reg_read(reg); 327 328 val &= ~mask; 329 val |= data & mask; 330 331 __fsi_reg_write(reg, val); 332 } 333 334 #define fsi_reg_write(p, r, d)\ 335 __fsi_reg_write((p->base + REG_##r), d) 336 337 #define fsi_reg_read(p, r)\ 338 __fsi_reg_read((p->base + REG_##r)) 339 340 #define fsi_reg_mask_set(p, r, m, d)\ 341 __fsi_reg_mask_set((p->base + REG_##r), m, d) 342 343 #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r) 344 #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r) 345 static u32 _fsi_master_read(struct fsi_master *master, u32 reg) 346 { 347 u32 ret; 348 unsigned long flags; 349 350 spin_lock_irqsave(&master->lock, flags); 351 ret = __fsi_reg_read(master->base + reg); 352 spin_unlock_irqrestore(&master->lock, flags); 353 354 return ret; 355 } 356 357 #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d) 358 #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d) 359 static void _fsi_master_mask_set(struct fsi_master *master, 360 u32 reg, u32 mask, u32 data) 361 { 362 unsigned long flags; 363 364 spin_lock_irqsave(&master->lock, flags); 365 __fsi_reg_mask_set(master->base + reg, mask, data); 366 spin_unlock_irqrestore(&master->lock, flags); 367 } 368 369 /* 370 * basic function 371 */ 372 static int fsi_version(struct fsi_master *master) 373 { 374 return master->core->ver; 375 } 376 377 static struct fsi_master *fsi_get_master(struct fsi_priv *fsi) 378 { 379 return fsi->master; 380 } 381 382 static int fsi_is_clk_master(struct fsi_priv *fsi) 383 { 384 return fsi->clk_master; 385 } 386 387 static int fsi_is_port_a(struct fsi_priv *fsi) 388 { 389 return fsi->master->base == fsi->base; 390 } 391 392 static int fsi_is_spdif(struct fsi_priv *fsi) 393 { 394 return fsi->spdif; 395 } 396 397 static int fsi_is_enable_stream(struct fsi_priv *fsi) 398 { 399 return fsi->enable_stream; 400 } 401 402 static int fsi_is_play(struct snd_pcm_substream *substream) 403 { 404 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 405 } 406 407 static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream) 408 { 409 struct snd_soc_pcm_runtime *rtd = substream->private_data; 410 411 return rtd->cpu_dai; 412 } 413 414 static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai) 415 { 416 struct fsi_master *master = snd_soc_dai_get_drvdata(dai); 417 418 if (dai->id == 0) 419 return &master->fsia; 420 else 421 return &master->fsib; 422 } 423 424 static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream) 425 { 426 return fsi_get_priv_frm_dai(fsi_get_dai(substream)); 427 } 428 429 static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io) 430 { 431 int is_play = fsi_stream_is_play(fsi, io); 432 int is_porta = fsi_is_port_a(fsi); 433 u32 shift; 434 435 if (is_porta) 436 shift = is_play ? AO_SHIFT : AI_SHIFT; 437 else 438 shift = is_play ? BO_SHIFT : BI_SHIFT; 439 440 return shift; 441 } 442 443 static int fsi_frame2sample(struct fsi_priv *fsi, int frames) 444 { 445 return frames * fsi->chan_num; 446 } 447 448 static int fsi_sample2frame(struct fsi_priv *fsi, int samples) 449 { 450 return samples / fsi->chan_num; 451 } 452 453 static int fsi_get_current_fifo_samples(struct fsi_priv *fsi, 454 struct fsi_stream *io) 455 { 456 int is_play = fsi_stream_is_play(fsi, io); 457 u32 status; 458 int frames; 459 460 status = is_play ? 461 fsi_reg_read(fsi, DOFF_ST) : 462 fsi_reg_read(fsi, DIFF_ST); 463 464 frames = 0x1ff & (status >> 8); 465 466 return fsi_frame2sample(fsi, frames); 467 } 468 469 static void fsi_count_fifo_err(struct fsi_priv *fsi) 470 { 471 u32 ostatus = fsi_reg_read(fsi, DOFF_ST); 472 u32 istatus = fsi_reg_read(fsi, DIFF_ST); 473 474 if (ostatus & ERR_OVER) 475 fsi->playback.oerr_num++; 476 477 if (ostatus & ERR_UNDER) 478 fsi->playback.uerr_num++; 479 480 if (istatus & ERR_OVER) 481 fsi->capture.oerr_num++; 482 483 if (istatus & ERR_UNDER) 484 fsi->capture.uerr_num++; 485 486 fsi_reg_write(fsi, DOFF_ST, 0); 487 fsi_reg_write(fsi, DIFF_ST, 0); 488 } 489 490 /* 491 * fsi_stream_xx() function 492 */ 493 static inline int fsi_stream_is_play(struct fsi_priv *fsi, 494 struct fsi_stream *io) 495 { 496 return &fsi->playback == io; 497 } 498 499 static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi, 500 struct snd_pcm_substream *substream) 501 { 502 return fsi_is_play(substream) ? &fsi->playback : &fsi->capture; 503 } 504 505 static int fsi_stream_is_working(struct fsi_priv *fsi, 506 struct fsi_stream *io) 507 { 508 struct fsi_master *master = fsi_get_master(fsi); 509 unsigned long flags; 510 int ret; 511 512 spin_lock_irqsave(&master->lock, flags); 513 ret = !!(io->substream && io->substream->runtime); 514 spin_unlock_irqrestore(&master->lock, flags); 515 516 return ret; 517 } 518 519 static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io) 520 { 521 return io->priv; 522 } 523 524 static void fsi_stream_init(struct fsi_priv *fsi, 525 struct fsi_stream *io, 526 struct snd_pcm_substream *substream) 527 { 528 struct snd_pcm_runtime *runtime = substream->runtime; 529 struct fsi_master *master = fsi_get_master(fsi); 530 unsigned long flags; 531 532 spin_lock_irqsave(&master->lock, flags); 533 io->substream = substream; 534 io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size); 535 io->buff_sample_pos = 0; 536 io->period_samples = fsi_frame2sample(fsi, runtime->period_size); 537 io->period_pos = 0; 538 io->sample_width = samples_to_bytes(runtime, 1); 539 io->bus_option = 0; 540 io->oerr_num = -1; /* ignore 1st err */ 541 io->uerr_num = -1; /* ignore 1st err */ 542 fsi_stream_handler_call(io, init, fsi, io); 543 spin_unlock_irqrestore(&master->lock, flags); 544 } 545 546 static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io) 547 { 548 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 549 struct fsi_master *master = fsi_get_master(fsi); 550 unsigned long flags; 551 552 spin_lock_irqsave(&master->lock, flags); 553 554 if (io->oerr_num > 0) 555 dev_err(dai->dev, "over_run = %d\n", io->oerr_num); 556 557 if (io->uerr_num > 0) 558 dev_err(dai->dev, "under_run = %d\n", io->uerr_num); 559 560 fsi_stream_handler_call(io, quit, fsi, io); 561 io->substream = NULL; 562 io->buff_sample_capa = 0; 563 io->buff_sample_pos = 0; 564 io->period_samples = 0; 565 io->period_pos = 0; 566 io->sample_width = 0; 567 io->bus_option = 0; 568 io->oerr_num = 0; 569 io->uerr_num = 0; 570 spin_unlock_irqrestore(&master->lock, flags); 571 } 572 573 static int fsi_stream_transfer(struct fsi_stream *io) 574 { 575 struct fsi_priv *fsi = fsi_stream_to_priv(io); 576 if (!fsi) 577 return -EIO; 578 579 return fsi_stream_handler_call(io, transfer, fsi, io); 580 } 581 582 #define fsi_stream_start(fsi, io)\ 583 fsi_stream_handler_call(io, start_stop, fsi, io, 1) 584 585 #define fsi_stream_stop(fsi, io)\ 586 fsi_stream_handler_call(io, start_stop, fsi, io, 0) 587 588 static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev) 589 { 590 struct fsi_stream *io; 591 int ret1, ret2; 592 593 io = &fsi->playback; 594 ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev); 595 596 io = &fsi->capture; 597 ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev); 598 599 if (ret1 < 0) 600 return ret1; 601 if (ret2 < 0) 602 return ret2; 603 604 return 0; 605 } 606 607 static int fsi_stream_remove(struct fsi_priv *fsi) 608 { 609 struct fsi_stream *io; 610 int ret1, ret2; 611 612 io = &fsi->playback; 613 ret1 = fsi_stream_handler_call(io, remove, fsi, io); 614 615 io = &fsi->capture; 616 ret2 = fsi_stream_handler_call(io, remove, fsi, io); 617 618 if (ret1 < 0) 619 return ret1; 620 if (ret2 < 0) 621 return ret2; 622 623 return 0; 624 } 625 626 /* 627 * format/bus/dma setting 628 */ 629 static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io, 630 u32 bus, struct device *dev) 631 { 632 struct fsi_master *master = fsi_get_master(fsi); 633 int is_play = fsi_stream_is_play(fsi, io); 634 u32 fmt = fsi->fmt; 635 636 if (fsi_version(master) >= 2) { 637 u32 dma = 0; 638 639 /* 640 * FSI2 needs DMA/Bus setting 641 */ 642 switch (bus) { 643 case PACKAGE_24BITBUS_FRONT: 644 fmt |= CR_BWS_24; 645 dma |= VDMD_FRONT; 646 dev_dbg(dev, "24bit bus / package in front\n"); 647 break; 648 case PACKAGE_16BITBUS_STREAM: 649 fmt |= CR_BWS_16; 650 dma |= VDMD_STREAM; 651 dev_dbg(dev, "16bit bus / stream mode\n"); 652 break; 653 case PACKAGE_24BITBUS_BACK: 654 default: 655 fmt |= CR_BWS_24; 656 dma |= VDMD_BACK; 657 dev_dbg(dev, "24bit bus / package in back\n"); 658 break; 659 } 660 661 if (is_play) 662 fsi_reg_write(fsi, OUT_DMAC, dma); 663 else 664 fsi_reg_write(fsi, IN_DMAC, dma); 665 } 666 667 if (is_play) 668 fsi_reg_write(fsi, DO_FMT, fmt); 669 else 670 fsi_reg_write(fsi, DI_FMT, fmt); 671 } 672 673 /* 674 * irq function 675 */ 676 677 static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io) 678 { 679 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 680 struct fsi_master *master = fsi_get_master(fsi); 681 682 fsi_core_mask_set(master, imsk, data, data); 683 fsi_core_mask_set(master, iemsk, data, data); 684 } 685 686 static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io) 687 { 688 u32 data = AB_IO(1, fsi_get_port_shift(fsi, io)); 689 struct fsi_master *master = fsi_get_master(fsi); 690 691 fsi_core_mask_set(master, imsk, data, 0); 692 fsi_core_mask_set(master, iemsk, data, 0); 693 } 694 695 static u32 fsi_irq_get_status(struct fsi_master *master) 696 { 697 return fsi_core_read(master, int_st); 698 } 699 700 static void fsi_irq_clear_status(struct fsi_priv *fsi) 701 { 702 u32 data = 0; 703 struct fsi_master *master = fsi_get_master(fsi); 704 705 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback)); 706 data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture)); 707 708 /* clear interrupt factor */ 709 fsi_core_mask_set(master, int_st, data, 0); 710 } 711 712 /* 713 * SPDIF master clock function 714 * 715 * These functions are used later FSI2 716 */ 717 static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable) 718 { 719 struct fsi_master *master = fsi_get_master(fsi); 720 u32 mask, val; 721 722 mask = BP | SE; 723 val = enable ? mask : 0; 724 725 fsi_is_port_a(fsi) ? 726 fsi_core_mask_set(master, a_mclk, mask, val) : 727 fsi_core_mask_set(master, b_mclk, mask, val); 728 } 729 730 /* 731 * clock function 732 */ 733 static int fsi_clk_init(struct device *dev, 734 struct fsi_priv *fsi, 735 int xck, 736 int ick, 737 int div, 738 int (*set_rate)(struct device *dev, 739 struct fsi_priv *fsi)) 740 { 741 struct fsi_clk *clock = &fsi->clock; 742 int is_porta = fsi_is_port_a(fsi); 743 744 clock->xck = NULL; 745 clock->ick = NULL; 746 clock->div = NULL; 747 clock->rate = 0; 748 clock->count = 0; 749 clock->set_rate = set_rate; 750 751 clock->own = devm_clk_get(dev, NULL); 752 if (IS_ERR(clock->own)) 753 return -EINVAL; 754 755 /* external clock */ 756 if (xck) { 757 clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb"); 758 if (IS_ERR(clock->xck)) { 759 dev_err(dev, "can't get xck clock\n"); 760 return -EINVAL; 761 } 762 if (clock->xck == clock->own) { 763 dev_err(dev, "cpu doesn't support xck clock\n"); 764 return -EINVAL; 765 } 766 } 767 768 /* FSIACLK/FSIBCLK */ 769 if (ick) { 770 clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb"); 771 if (IS_ERR(clock->ick)) { 772 dev_err(dev, "can't get ick clock\n"); 773 return -EINVAL; 774 } 775 if (clock->ick == clock->own) { 776 dev_err(dev, "cpu doesn't support ick clock\n"); 777 return -EINVAL; 778 } 779 } 780 781 /* FSI-DIV */ 782 if (div) { 783 clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb"); 784 if (IS_ERR(clock->div)) { 785 dev_err(dev, "can't get div clock\n"); 786 return -EINVAL; 787 } 788 if (clock->div == clock->own) { 789 dev_err(dev, "cpu doens't support div clock\n"); 790 return -EINVAL; 791 } 792 } 793 794 return 0; 795 } 796 797 #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0) 798 static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate) 799 { 800 fsi->clock.rate = rate; 801 } 802 803 static int fsi_clk_is_valid(struct fsi_priv *fsi) 804 { 805 return fsi->clock.set_rate && 806 fsi->clock.rate; 807 } 808 809 static int fsi_clk_enable(struct device *dev, 810 struct fsi_priv *fsi) 811 { 812 struct fsi_clk *clock = &fsi->clock; 813 int ret = -EINVAL; 814 815 if (!fsi_clk_is_valid(fsi)) 816 return ret; 817 818 if (0 == clock->count) { 819 ret = clock->set_rate(dev, fsi); 820 if (ret < 0) { 821 fsi_clk_invalid(fsi); 822 return ret; 823 } 824 825 if (clock->xck) 826 clk_enable(clock->xck); 827 if (clock->ick) 828 clk_enable(clock->ick); 829 if (clock->div) 830 clk_enable(clock->div); 831 832 clock->count++; 833 } 834 835 return ret; 836 } 837 838 static int fsi_clk_disable(struct device *dev, 839 struct fsi_priv *fsi) 840 { 841 struct fsi_clk *clock = &fsi->clock; 842 843 if (!fsi_clk_is_valid(fsi)) 844 return -EINVAL; 845 846 if (1 == clock->count--) { 847 if (clock->xck) 848 clk_disable(clock->xck); 849 if (clock->ick) 850 clk_disable(clock->ick); 851 if (clock->div) 852 clk_disable(clock->div); 853 } 854 855 return 0; 856 } 857 858 static int fsi_clk_set_ackbpf(struct device *dev, 859 struct fsi_priv *fsi, 860 int ackmd, int bpfmd) 861 { 862 u32 data = 0; 863 864 /* check ackmd/bpfmd relationship */ 865 if (bpfmd > ackmd) { 866 dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd); 867 return -EINVAL; 868 } 869 870 /* ACKMD */ 871 switch (ackmd) { 872 case 512: 873 data |= (0x0 << 12); 874 break; 875 case 256: 876 data |= (0x1 << 12); 877 break; 878 case 128: 879 data |= (0x2 << 12); 880 break; 881 case 64: 882 data |= (0x3 << 12); 883 break; 884 case 32: 885 data |= (0x4 << 12); 886 break; 887 default: 888 dev_err(dev, "unsupported ackmd (%d)\n", ackmd); 889 return -EINVAL; 890 } 891 892 /* BPFMD */ 893 switch (bpfmd) { 894 case 32: 895 data |= (0x0 << 8); 896 break; 897 case 64: 898 data |= (0x1 << 8); 899 break; 900 case 128: 901 data |= (0x2 << 8); 902 break; 903 case 256: 904 data |= (0x3 << 8); 905 break; 906 case 512: 907 data |= (0x4 << 8); 908 break; 909 case 16: 910 data |= (0x7 << 8); 911 break; 912 default: 913 dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd); 914 return -EINVAL; 915 } 916 917 dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd); 918 919 fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data); 920 udelay(10); 921 922 return 0; 923 } 924 925 static int fsi_clk_set_rate_external(struct device *dev, 926 struct fsi_priv *fsi) 927 { 928 struct clk *xck = fsi->clock.xck; 929 struct clk *ick = fsi->clock.ick; 930 unsigned long rate = fsi->clock.rate; 931 unsigned long xrate; 932 int ackmd, bpfmd; 933 int ret = 0; 934 935 /* check clock rate */ 936 xrate = clk_get_rate(xck); 937 if (xrate % rate) { 938 dev_err(dev, "unsupported clock rate\n"); 939 return -EINVAL; 940 } 941 942 clk_set_parent(ick, xck); 943 clk_set_rate(ick, xrate); 944 945 bpfmd = fsi->chan_num * 32; 946 ackmd = xrate / rate; 947 948 dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate); 949 950 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 951 if (ret < 0) 952 dev_err(dev, "%s failed", __func__); 953 954 return ret; 955 } 956 957 static int fsi_clk_set_rate_cpg(struct device *dev, 958 struct fsi_priv *fsi) 959 { 960 struct clk *ick = fsi->clock.ick; 961 struct clk *div = fsi->clock.div; 962 unsigned long rate = fsi->clock.rate; 963 unsigned long target = 0; /* 12288000 or 11289600 */ 964 unsigned long actual, cout; 965 unsigned long diff, min; 966 unsigned long best_cout, best_act; 967 int adj; 968 int ackmd, bpfmd; 969 int ret = -EINVAL; 970 971 if (!(12288000 % rate)) 972 target = 12288000; 973 if (!(11289600 % rate)) 974 target = 11289600; 975 if (!target) { 976 dev_err(dev, "unsupported rate\n"); 977 return ret; 978 } 979 980 bpfmd = fsi->chan_num * 32; 981 ackmd = target / rate; 982 ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd); 983 if (ret < 0) { 984 dev_err(dev, "%s failed", __func__); 985 return ret; 986 } 987 988 /* 989 * The clock flow is 990 * 991 * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec] 992 * 993 * But, it needs to find best match of CPG and FSI_DIV 994 * combination, since it is difficult to generate correct 995 * frequency of audio clock from ick clock only. 996 * Because ick is created from its parent clock. 997 * 998 * target = rate x [512/256/128/64]fs 999 * cout = round(target x adjustment) 1000 * actual = cout / adjustment (by FSI-DIV) ~= target 1001 * audio = actual 1002 */ 1003 min = ~0; 1004 best_cout = 0; 1005 best_act = 0; 1006 for (adj = 1; adj < 0xffff; adj++) { 1007 1008 cout = target * adj; 1009 if (cout > 100000000) /* max clock = 100MHz */ 1010 break; 1011 1012 /* cout/actual audio clock */ 1013 cout = clk_round_rate(ick, cout); 1014 actual = cout / adj; 1015 1016 /* find best frequency */ 1017 diff = abs(actual - target); 1018 if (diff < min) { 1019 min = diff; 1020 best_cout = cout; 1021 best_act = actual; 1022 } 1023 } 1024 1025 ret = clk_set_rate(ick, best_cout); 1026 if (ret < 0) { 1027 dev_err(dev, "ick clock failed\n"); 1028 return -EIO; 1029 } 1030 1031 ret = clk_set_rate(div, clk_round_rate(div, best_act)); 1032 if (ret < 0) { 1033 dev_err(dev, "div clock failed\n"); 1034 return -EIO; 1035 } 1036 1037 dev_dbg(dev, "ick/div = %ld/%ld\n", 1038 clk_get_rate(ick), clk_get_rate(div)); 1039 1040 return ret; 1041 } 1042 1043 /* 1044 * pio data transfer handler 1045 */ 1046 static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples) 1047 { 1048 int i; 1049 1050 if (fsi_is_enable_stream(fsi)) { 1051 /* 1052 * stream mode 1053 * see 1054 * fsi_pio_push_init() 1055 */ 1056 u32 *buf = (u32 *)_buf; 1057 1058 for (i = 0; i < samples / 2; i++) 1059 fsi_reg_write(fsi, DODT, buf[i]); 1060 } else { 1061 /* normal mode */ 1062 u16 *buf = (u16 *)_buf; 1063 1064 for (i = 0; i < samples; i++) 1065 fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8)); 1066 } 1067 } 1068 1069 static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples) 1070 { 1071 u16 *buf = (u16 *)_buf; 1072 int i; 1073 1074 for (i = 0; i < samples; i++) 1075 *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8); 1076 } 1077 1078 static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples) 1079 { 1080 u32 *buf = (u32 *)_buf; 1081 int i; 1082 1083 for (i = 0; i < samples; i++) 1084 fsi_reg_write(fsi, DODT, *(buf + i)); 1085 } 1086 1087 static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples) 1088 { 1089 u32 *buf = (u32 *)_buf; 1090 int i; 1091 1092 for (i = 0; i < samples; i++) 1093 *(buf + i) = fsi_reg_read(fsi, DIDT); 1094 } 1095 1096 static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io) 1097 { 1098 struct snd_pcm_runtime *runtime = io->substream->runtime; 1099 1100 return runtime->dma_area + 1101 samples_to_bytes(runtime, io->buff_sample_pos); 1102 } 1103 1104 static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io, 1105 void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples), 1106 void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples), 1107 int samples) 1108 { 1109 struct snd_pcm_runtime *runtime; 1110 struct snd_pcm_substream *substream; 1111 u8 *buf; 1112 int over_period; 1113 1114 if (!fsi_stream_is_working(fsi, io)) 1115 return -EINVAL; 1116 1117 over_period = 0; 1118 substream = io->substream; 1119 runtime = substream->runtime; 1120 1121 /* FSI FIFO has limit. 1122 * So, this driver can not send periods data at a time 1123 */ 1124 if (io->buff_sample_pos >= 1125 io->period_samples * (io->period_pos + 1)) { 1126 1127 over_period = 1; 1128 io->period_pos = (io->period_pos + 1) % runtime->periods; 1129 1130 if (0 == io->period_pos) 1131 io->buff_sample_pos = 0; 1132 } 1133 1134 buf = fsi_pio_get_area(fsi, io); 1135 1136 switch (io->sample_width) { 1137 case 2: 1138 run16(fsi, buf, samples); 1139 break; 1140 case 4: 1141 run32(fsi, buf, samples); 1142 break; 1143 default: 1144 return -EINVAL; 1145 } 1146 1147 /* update buff_sample_pos */ 1148 io->buff_sample_pos += samples; 1149 1150 if (over_period) 1151 snd_pcm_period_elapsed(substream); 1152 1153 return 0; 1154 } 1155 1156 static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io) 1157 { 1158 int sample_residues; /* samples in FSI fifo */ 1159 int sample_space; /* ALSA free samples space */ 1160 int samples; 1161 1162 sample_residues = fsi_get_current_fifo_samples(fsi, io); 1163 sample_space = io->buff_sample_capa - io->buff_sample_pos; 1164 1165 samples = min(sample_residues, sample_space); 1166 1167 return fsi_pio_transfer(fsi, io, 1168 fsi_pio_pop16, 1169 fsi_pio_pop32, 1170 samples); 1171 } 1172 1173 static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io) 1174 { 1175 int sample_residues; /* ALSA residue samples */ 1176 int sample_space; /* FSI fifo free samples space */ 1177 int samples; 1178 1179 sample_residues = io->buff_sample_capa - io->buff_sample_pos; 1180 sample_space = io->fifo_sample_capa - 1181 fsi_get_current_fifo_samples(fsi, io); 1182 1183 samples = min(sample_residues, sample_space); 1184 1185 return fsi_pio_transfer(fsi, io, 1186 fsi_pio_push16, 1187 fsi_pio_push32, 1188 samples); 1189 } 1190 1191 static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1192 int enable) 1193 { 1194 struct fsi_master *master = fsi_get_master(fsi); 1195 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1196 1197 if (enable) 1198 fsi_irq_enable(fsi, io); 1199 else 1200 fsi_irq_disable(fsi, io); 1201 1202 if (fsi_is_clk_master(fsi)) 1203 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1204 1205 return 0; 1206 } 1207 1208 static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io) 1209 { 1210 /* 1211 * we can use 16bit stream mode 1212 * when "playback" and "16bit data" 1213 * and platform allows "stream mode" 1214 * see 1215 * fsi_pio_push16() 1216 */ 1217 if (fsi_is_enable_stream(fsi)) 1218 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1219 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1220 else 1221 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1222 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1223 return 0; 1224 } 1225 1226 static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io) 1227 { 1228 /* 1229 * always 24bit bus, package back when "capture" 1230 */ 1231 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1232 BUSOP_SET(16, PACKAGE_24BITBUS_BACK); 1233 return 0; 1234 } 1235 1236 static struct fsi_stream_handler fsi_pio_push_handler = { 1237 .init = fsi_pio_push_init, 1238 .transfer = fsi_pio_push, 1239 .start_stop = fsi_pio_start_stop, 1240 }; 1241 1242 static struct fsi_stream_handler fsi_pio_pop_handler = { 1243 .init = fsi_pio_pop_init, 1244 .transfer = fsi_pio_pop, 1245 .start_stop = fsi_pio_start_stop, 1246 }; 1247 1248 static irqreturn_t fsi_interrupt(int irq, void *data) 1249 { 1250 struct fsi_master *master = data; 1251 u32 int_st = fsi_irq_get_status(master); 1252 1253 /* clear irq status */ 1254 fsi_master_mask_set(master, SOFT_RST, IR, 0); 1255 fsi_master_mask_set(master, SOFT_RST, IR, IR); 1256 1257 if (int_st & AB_IO(1, AO_SHIFT)) 1258 fsi_stream_transfer(&master->fsia.playback); 1259 if (int_st & AB_IO(1, BO_SHIFT)) 1260 fsi_stream_transfer(&master->fsib.playback); 1261 if (int_st & AB_IO(1, AI_SHIFT)) 1262 fsi_stream_transfer(&master->fsia.capture); 1263 if (int_st & AB_IO(1, BI_SHIFT)) 1264 fsi_stream_transfer(&master->fsib.capture); 1265 1266 fsi_count_fifo_err(&master->fsia); 1267 fsi_count_fifo_err(&master->fsib); 1268 1269 fsi_irq_clear_status(&master->fsia); 1270 fsi_irq_clear_status(&master->fsib); 1271 1272 return IRQ_HANDLED; 1273 } 1274 1275 /* 1276 * dma data transfer handler 1277 */ 1278 static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io) 1279 { 1280 struct snd_pcm_runtime *runtime = io->substream->runtime; 1281 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1282 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1283 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1284 1285 /* 1286 * 24bit data : 24bit bus / package in back 1287 * 16bit data : 16bit bus / stream mode 1288 */ 1289 io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) | 1290 BUSOP_SET(16, PACKAGE_16BITBUS_STREAM); 1291 1292 io->dma = dma_map_single(dai->dev, runtime->dma_area, 1293 snd_pcm_lib_buffer_bytes(io->substream), dir); 1294 return 0; 1295 } 1296 1297 static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io) 1298 { 1299 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1300 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1301 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1302 1303 dma_unmap_single(dai->dev, io->dma, 1304 snd_pcm_lib_buffer_bytes(io->substream), dir); 1305 return 0; 1306 } 1307 1308 static dma_addr_t fsi_dma_get_area(struct fsi_stream *io) 1309 { 1310 struct snd_pcm_runtime *runtime = io->substream->runtime; 1311 1312 return io->dma + samples_to_bytes(runtime, io->buff_sample_pos); 1313 } 1314 1315 static void fsi_dma_complete(void *data) 1316 { 1317 struct fsi_stream *io = (struct fsi_stream *)data; 1318 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1319 struct snd_pcm_runtime *runtime = io->substream->runtime; 1320 struct snd_soc_dai *dai = fsi_get_dai(io->substream); 1321 enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ? 1322 DMA_TO_DEVICE : DMA_FROM_DEVICE; 1323 1324 dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io), 1325 samples_to_bytes(runtime, io->period_samples), dir); 1326 1327 io->buff_sample_pos += io->period_samples; 1328 io->period_pos++; 1329 1330 if (io->period_pos >= runtime->periods) { 1331 io->period_pos = 0; 1332 io->buff_sample_pos = 0; 1333 } 1334 1335 fsi_count_fifo_err(fsi); 1336 fsi_stream_transfer(io); 1337 1338 snd_pcm_period_elapsed(io->substream); 1339 } 1340 1341 static void fsi_dma_do_work(struct work_struct *work) 1342 { 1343 struct fsi_stream *io = container_of(work, struct fsi_stream, work); 1344 struct fsi_priv *fsi = fsi_stream_to_priv(io); 1345 struct snd_soc_dai *dai; 1346 struct dma_async_tx_descriptor *desc; 1347 struct snd_pcm_runtime *runtime; 1348 enum dma_data_direction dir; 1349 int is_play = fsi_stream_is_play(fsi, io); 1350 int len; 1351 dma_addr_t buf; 1352 1353 if (!fsi_stream_is_working(fsi, io)) 1354 return; 1355 1356 dai = fsi_get_dai(io->substream); 1357 runtime = io->substream->runtime; 1358 dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE; 1359 len = samples_to_bytes(runtime, io->period_samples); 1360 buf = fsi_dma_get_area(io); 1361 1362 dma_sync_single_for_device(dai->dev, buf, len, dir); 1363 1364 desc = dmaengine_prep_slave_single(io->chan, buf, len, dir, 1365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1366 if (!desc) { 1367 dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n"); 1368 return; 1369 } 1370 1371 desc->callback = fsi_dma_complete; 1372 desc->callback_param = io; 1373 1374 if (dmaengine_submit(desc) < 0) { 1375 dev_err(dai->dev, "tx_submit() fail\n"); 1376 return; 1377 } 1378 1379 dma_async_issue_pending(io->chan); 1380 1381 /* 1382 * FIXME 1383 * 1384 * In DMAEngine case, codec and FSI cannot be started simultaneously 1385 * since FSI is using the scheduler work queue. 1386 * Therefore, in capture case, probably FSI FIFO will have got 1387 * overflow error in this point. 1388 * in that case, DMA cannot start transfer until error was cleared. 1389 */ 1390 if (!is_play) { 1391 if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) { 1392 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1393 fsi_reg_write(fsi, DIFF_ST, 0); 1394 } 1395 } 1396 } 1397 1398 static bool fsi_dma_filter(struct dma_chan *chan, void *param) 1399 { 1400 struct sh_dmae_slave *slave = param; 1401 1402 chan->private = slave; 1403 1404 return true; 1405 } 1406 1407 static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io) 1408 { 1409 schedule_work(&io->work); 1410 1411 return 0; 1412 } 1413 1414 static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io, 1415 int start) 1416 { 1417 struct fsi_master *master = fsi_get_master(fsi); 1418 u32 clk = fsi_is_port_a(fsi) ? CRA : CRB; 1419 u32 enable = start ? DMA_ON : 0; 1420 1421 fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable); 1422 1423 dmaengine_terminate_all(io->chan); 1424 1425 if (fsi_is_clk_master(fsi)) 1426 fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0); 1427 1428 return 0; 1429 } 1430 1431 static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev) 1432 { 1433 dma_cap_mask_t mask; 1434 1435 dma_cap_zero(mask); 1436 dma_cap_set(DMA_SLAVE, mask); 1437 1438 io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave); 1439 if (!io->chan) { 1440 1441 /* switch to PIO handler */ 1442 if (fsi_stream_is_play(fsi, io)) 1443 fsi->playback.handler = &fsi_pio_push_handler; 1444 else 1445 fsi->capture.handler = &fsi_pio_pop_handler; 1446 1447 dev_info(dev, "switch handler (dma => pio)\n"); 1448 1449 /* probe again */ 1450 return fsi_stream_probe(fsi, dev); 1451 } 1452 1453 INIT_WORK(&io->work, fsi_dma_do_work); 1454 1455 return 0; 1456 } 1457 1458 static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io) 1459 { 1460 cancel_work_sync(&io->work); 1461 1462 fsi_stream_stop(fsi, io); 1463 1464 if (io->chan) 1465 dma_release_channel(io->chan); 1466 1467 io->chan = NULL; 1468 return 0; 1469 } 1470 1471 static struct fsi_stream_handler fsi_dma_push_handler = { 1472 .init = fsi_dma_init, 1473 .quit = fsi_dma_quit, 1474 .probe = fsi_dma_probe, 1475 .transfer = fsi_dma_transfer, 1476 .remove = fsi_dma_remove, 1477 .start_stop = fsi_dma_push_start_stop, 1478 }; 1479 1480 /* 1481 * dai ops 1482 */ 1483 static void fsi_fifo_init(struct fsi_priv *fsi, 1484 struct fsi_stream *io, 1485 struct device *dev) 1486 { 1487 struct fsi_master *master = fsi_get_master(fsi); 1488 int is_play = fsi_stream_is_play(fsi, io); 1489 u32 shift, i; 1490 int frame_capa; 1491 1492 /* get on-chip RAM capacity */ 1493 shift = fsi_master_read(master, FIFO_SZ); 1494 shift >>= fsi_get_port_shift(fsi, io); 1495 shift &= FIFO_SZ_MASK; 1496 frame_capa = 256 << shift; 1497 dev_dbg(dev, "fifo = %d words\n", frame_capa); 1498 1499 /* 1500 * The maximum number of sample data varies depending 1501 * on the number of channels selected for the format. 1502 * 1503 * FIFOs are used in 4-channel units in 3-channel mode 1504 * and in 8-channel units in 5- to 7-channel mode 1505 * meaning that more FIFOs than the required size of DPRAM 1506 * are used. 1507 * 1508 * ex) if 256 words of DP-RAM is connected 1509 * 1 channel: 256 (256 x 1 = 256) 1510 * 2 channels: 128 (128 x 2 = 256) 1511 * 3 channels: 64 ( 64 x 3 = 192) 1512 * 4 channels: 64 ( 64 x 4 = 256) 1513 * 5 channels: 32 ( 32 x 5 = 160) 1514 * 6 channels: 32 ( 32 x 6 = 192) 1515 * 7 channels: 32 ( 32 x 7 = 224) 1516 * 8 channels: 32 ( 32 x 8 = 256) 1517 */ 1518 for (i = 1; i < fsi->chan_num; i <<= 1) 1519 frame_capa >>= 1; 1520 dev_dbg(dev, "%d channel %d store\n", 1521 fsi->chan_num, frame_capa); 1522 1523 io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa); 1524 1525 /* 1526 * set interrupt generation factor 1527 * clear FIFO 1528 */ 1529 if (is_play) { 1530 fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF); 1531 fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR); 1532 } else { 1533 fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF); 1534 fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR); 1535 } 1536 } 1537 1538 static int fsi_hw_startup(struct fsi_priv *fsi, 1539 struct fsi_stream *io, 1540 struct device *dev) 1541 { 1542 u32 data = 0; 1543 1544 /* clock setting */ 1545 if (fsi_is_clk_master(fsi)) 1546 data = DIMD | DOMD; 1547 1548 fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data); 1549 1550 /* clock inversion (CKG2) */ 1551 data = 0; 1552 if (fsi->bit_clk_inv) 1553 data |= (1 << 0); 1554 if (fsi->lr_clk_inv) 1555 data |= (1 << 4); 1556 if (fsi_is_clk_master(fsi)) 1557 data <<= 8; 1558 fsi_reg_write(fsi, CKG2, data); 1559 1560 /* spdif ? */ 1561 if (fsi_is_spdif(fsi)) { 1562 fsi_spdif_clk_ctrl(fsi, 1); 1563 fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD); 1564 } 1565 1566 /* 1567 * get bus settings 1568 */ 1569 data = 0; 1570 switch (io->sample_width) { 1571 case 2: 1572 data = BUSOP_GET(16, io->bus_option); 1573 break; 1574 case 4: 1575 data = BUSOP_GET(24, io->bus_option); 1576 break; 1577 } 1578 fsi_format_bus_setup(fsi, io, data, dev); 1579 1580 /* irq clear */ 1581 fsi_irq_disable(fsi, io); 1582 fsi_irq_clear_status(fsi); 1583 1584 /* fifo init */ 1585 fsi_fifo_init(fsi, io, dev); 1586 1587 /* start master clock */ 1588 if (fsi_is_clk_master(fsi)) 1589 return fsi_clk_enable(dev, fsi); 1590 1591 return 0; 1592 } 1593 1594 static int fsi_hw_shutdown(struct fsi_priv *fsi, 1595 struct device *dev) 1596 { 1597 /* stop master clock */ 1598 if (fsi_is_clk_master(fsi)) 1599 return fsi_clk_disable(dev, fsi); 1600 1601 return 0; 1602 } 1603 1604 static int fsi_dai_startup(struct snd_pcm_substream *substream, 1605 struct snd_soc_dai *dai) 1606 { 1607 struct fsi_priv *fsi = fsi_get_priv(substream); 1608 1609 fsi_clk_invalid(fsi); 1610 1611 return 0; 1612 } 1613 1614 static void fsi_dai_shutdown(struct snd_pcm_substream *substream, 1615 struct snd_soc_dai *dai) 1616 { 1617 struct fsi_priv *fsi = fsi_get_priv(substream); 1618 1619 fsi_clk_invalid(fsi); 1620 } 1621 1622 static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 1623 struct snd_soc_dai *dai) 1624 { 1625 struct fsi_priv *fsi = fsi_get_priv(substream); 1626 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1627 int ret = 0; 1628 1629 switch (cmd) { 1630 case SNDRV_PCM_TRIGGER_START: 1631 fsi_stream_init(fsi, io, substream); 1632 if (!ret) 1633 ret = fsi_hw_startup(fsi, io, dai->dev); 1634 if (!ret) 1635 ret = fsi_stream_transfer(io); 1636 if (!ret) 1637 fsi_stream_start(fsi, io); 1638 break; 1639 case SNDRV_PCM_TRIGGER_STOP: 1640 if (!ret) 1641 ret = fsi_hw_shutdown(fsi, dai->dev); 1642 fsi_stream_stop(fsi, io); 1643 fsi_stream_quit(fsi, io); 1644 break; 1645 } 1646 1647 return ret; 1648 } 1649 1650 static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt) 1651 { 1652 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 1653 case SND_SOC_DAIFMT_I2S: 1654 fsi->fmt = CR_I2S; 1655 fsi->chan_num = 2; 1656 break; 1657 case SND_SOC_DAIFMT_LEFT_J: 1658 fsi->fmt = CR_PCM; 1659 fsi->chan_num = 2; 1660 break; 1661 default: 1662 return -EINVAL; 1663 } 1664 1665 return 0; 1666 } 1667 1668 static int fsi_set_fmt_spdif(struct fsi_priv *fsi) 1669 { 1670 struct fsi_master *master = fsi_get_master(fsi); 1671 1672 if (fsi_version(master) < 2) 1673 return -EINVAL; 1674 1675 fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM; 1676 fsi->chan_num = 2; 1677 1678 return 0; 1679 } 1680 1681 static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1682 { 1683 struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai); 1684 int ret; 1685 1686 /* set master/slave audio interface */ 1687 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 1688 case SND_SOC_DAIFMT_CBM_CFM: 1689 fsi->clk_master = 1; 1690 break; 1691 case SND_SOC_DAIFMT_CBS_CFS: 1692 break; 1693 default: 1694 return -EINVAL; 1695 } 1696 1697 /* set clock inversion */ 1698 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 1699 case SND_SOC_DAIFMT_NB_IF: 1700 fsi->bit_clk_inv = 0; 1701 fsi->lr_clk_inv = 1; 1702 break; 1703 case SND_SOC_DAIFMT_IB_NF: 1704 fsi->bit_clk_inv = 1; 1705 fsi->lr_clk_inv = 0; 1706 break; 1707 case SND_SOC_DAIFMT_IB_IF: 1708 fsi->bit_clk_inv = 1; 1709 fsi->lr_clk_inv = 1; 1710 break; 1711 case SND_SOC_DAIFMT_NB_NF: 1712 default: 1713 fsi->bit_clk_inv = 0; 1714 fsi->lr_clk_inv = 0; 1715 break; 1716 } 1717 1718 if (fsi_is_clk_master(fsi)) { 1719 if (fsi->clk_cpg) 1720 fsi_clk_init(dai->dev, fsi, 0, 1, 1, 1721 fsi_clk_set_rate_cpg); 1722 else 1723 fsi_clk_init(dai->dev, fsi, 1, 1, 0, 1724 fsi_clk_set_rate_external); 1725 } 1726 1727 /* set format */ 1728 if (fsi_is_spdif(fsi)) 1729 ret = fsi_set_fmt_spdif(fsi); 1730 else 1731 ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK); 1732 1733 return ret; 1734 } 1735 1736 static int fsi_dai_hw_params(struct snd_pcm_substream *substream, 1737 struct snd_pcm_hw_params *params, 1738 struct snd_soc_dai *dai) 1739 { 1740 struct fsi_priv *fsi = fsi_get_priv(substream); 1741 1742 if (fsi_is_clk_master(fsi)) 1743 fsi_clk_valid(fsi, params_rate(params)); 1744 1745 return 0; 1746 } 1747 1748 static const struct snd_soc_dai_ops fsi_dai_ops = { 1749 .startup = fsi_dai_startup, 1750 .shutdown = fsi_dai_shutdown, 1751 .trigger = fsi_dai_trigger, 1752 .set_fmt = fsi_dai_set_fmt, 1753 .hw_params = fsi_dai_hw_params, 1754 }; 1755 1756 /* 1757 * pcm ops 1758 */ 1759 1760 static struct snd_pcm_hardware fsi_pcm_hardware = { 1761 .info = SNDRV_PCM_INFO_INTERLEAVED | 1762 SNDRV_PCM_INFO_MMAP | 1763 SNDRV_PCM_INFO_MMAP_VALID | 1764 SNDRV_PCM_INFO_PAUSE, 1765 .formats = FSI_FMTS, 1766 .rates = FSI_RATES, 1767 .rate_min = 8000, 1768 .rate_max = 192000, 1769 .channels_min = 2, 1770 .channels_max = 2, 1771 .buffer_bytes_max = 64 * 1024, 1772 .period_bytes_min = 32, 1773 .period_bytes_max = 8192, 1774 .periods_min = 1, 1775 .periods_max = 32, 1776 .fifo_size = 256, 1777 }; 1778 1779 static int fsi_pcm_open(struct snd_pcm_substream *substream) 1780 { 1781 struct snd_pcm_runtime *runtime = substream->runtime; 1782 int ret = 0; 1783 1784 snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware); 1785 1786 ret = snd_pcm_hw_constraint_integer(runtime, 1787 SNDRV_PCM_HW_PARAM_PERIODS); 1788 1789 return ret; 1790 } 1791 1792 static int fsi_hw_params(struct snd_pcm_substream *substream, 1793 struct snd_pcm_hw_params *hw_params) 1794 { 1795 return snd_pcm_lib_malloc_pages(substream, 1796 params_buffer_bytes(hw_params)); 1797 } 1798 1799 static int fsi_hw_free(struct snd_pcm_substream *substream) 1800 { 1801 return snd_pcm_lib_free_pages(substream); 1802 } 1803 1804 static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream) 1805 { 1806 struct fsi_priv *fsi = fsi_get_priv(substream); 1807 struct fsi_stream *io = fsi_stream_get(fsi, substream); 1808 1809 return fsi_sample2frame(fsi, io->buff_sample_pos); 1810 } 1811 1812 static struct snd_pcm_ops fsi_pcm_ops = { 1813 .open = fsi_pcm_open, 1814 .ioctl = snd_pcm_lib_ioctl, 1815 .hw_params = fsi_hw_params, 1816 .hw_free = fsi_hw_free, 1817 .pointer = fsi_pointer, 1818 }; 1819 1820 /* 1821 * snd_soc_platform 1822 */ 1823 1824 #define PREALLOC_BUFFER (32 * 1024) 1825 #define PREALLOC_BUFFER_MAX (32 * 1024) 1826 1827 static void fsi_pcm_free(struct snd_pcm *pcm) 1828 { 1829 snd_pcm_lib_preallocate_free_for_all(pcm); 1830 } 1831 1832 static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd) 1833 { 1834 struct snd_pcm *pcm = rtd->pcm; 1835 1836 /* 1837 * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel 1838 * in MMAP mode (i.e. aplay -M) 1839 */ 1840 return snd_pcm_lib_preallocate_pages_for_all( 1841 pcm, 1842 SNDRV_DMA_TYPE_CONTINUOUS, 1843 snd_dma_continuous_data(GFP_KERNEL), 1844 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1845 } 1846 1847 /* 1848 * alsa struct 1849 */ 1850 1851 static struct snd_soc_dai_driver fsi_soc_dai[] = { 1852 { 1853 .name = "fsia-dai", 1854 .playback = { 1855 .rates = FSI_RATES, 1856 .formats = FSI_FMTS, 1857 .channels_min = 2, 1858 .channels_max = 2, 1859 }, 1860 .capture = { 1861 .rates = FSI_RATES, 1862 .formats = FSI_FMTS, 1863 .channels_min = 2, 1864 .channels_max = 2, 1865 }, 1866 .ops = &fsi_dai_ops, 1867 }, 1868 { 1869 .name = "fsib-dai", 1870 .playback = { 1871 .rates = FSI_RATES, 1872 .formats = FSI_FMTS, 1873 .channels_min = 2, 1874 .channels_max = 2, 1875 }, 1876 .capture = { 1877 .rates = FSI_RATES, 1878 .formats = FSI_FMTS, 1879 .channels_min = 2, 1880 .channels_max = 2, 1881 }, 1882 .ops = &fsi_dai_ops, 1883 }, 1884 }; 1885 1886 static struct snd_soc_platform_driver fsi_soc_platform = { 1887 .ops = &fsi_pcm_ops, 1888 .pcm_new = fsi_pcm_new, 1889 .pcm_free = fsi_pcm_free, 1890 }; 1891 1892 static const struct snd_soc_component_driver fsi_soc_component = { 1893 .name = "fsi", 1894 }; 1895 1896 /* 1897 * platform function 1898 */ 1899 static void fsi_of_parse(char *name, 1900 struct device_node *np, 1901 struct sh_fsi_port_info *info, 1902 struct device *dev) 1903 { 1904 int i; 1905 char prop[128]; 1906 unsigned long flags = 0; 1907 struct { 1908 char *name; 1909 unsigned int val; 1910 } of_parse_property[] = { 1911 { "spdif-connection", SH_FSI_FMT_SPDIF }, 1912 { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE }, 1913 { "use-internal-clock", SH_FSI_CLK_CPG }, 1914 }; 1915 1916 for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) { 1917 sprintf(prop, "%s,%s", name, of_parse_property[i].name); 1918 if (of_get_property(np, prop, NULL)) 1919 flags |= of_parse_property[i].val; 1920 } 1921 info->flags = flags; 1922 1923 dev_dbg(dev, "%s flags : %lx\n", name, info->flags); 1924 } 1925 1926 static void fsi_port_info_init(struct fsi_priv *fsi, 1927 struct sh_fsi_port_info *info) 1928 { 1929 if (info->flags & SH_FSI_FMT_SPDIF) 1930 fsi->spdif = 1; 1931 1932 if (info->flags & SH_FSI_CLK_CPG) 1933 fsi->clk_cpg = 1; 1934 1935 if (info->flags & SH_FSI_ENABLE_STREAM_MODE) 1936 fsi->enable_stream = 1; 1937 } 1938 1939 static void fsi_handler_init(struct fsi_priv *fsi, 1940 struct sh_fsi_port_info *info) 1941 { 1942 fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */ 1943 fsi->playback.priv = fsi; 1944 fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */ 1945 fsi->capture.priv = fsi; 1946 1947 if (info->tx_id) { 1948 fsi->playback.slave.shdma_slave.slave_id = info->tx_id; 1949 fsi->playback.handler = &fsi_dma_push_handler; 1950 } 1951 } 1952 1953 static struct of_device_id fsi_of_match[]; 1954 static int fsi_probe(struct platform_device *pdev) 1955 { 1956 struct fsi_master *master; 1957 struct device_node *np = pdev->dev.of_node; 1958 struct sh_fsi_platform_info info; 1959 const struct fsi_core *core; 1960 struct fsi_priv *fsi; 1961 struct resource *res; 1962 unsigned int irq; 1963 int ret; 1964 1965 memset(&info, 0, sizeof(info)); 1966 1967 core = NULL; 1968 if (np) { 1969 const struct of_device_id *of_id; 1970 1971 of_id = of_match_device(fsi_of_match, &pdev->dev); 1972 if (of_id) { 1973 core = of_id->data; 1974 fsi_of_parse("fsia", np, &info.port_a, &pdev->dev); 1975 fsi_of_parse("fsib", np, &info.port_b, &pdev->dev); 1976 } 1977 } else { 1978 const struct platform_device_id *id_entry = pdev->id_entry; 1979 if (id_entry) 1980 core = (struct fsi_core *)id_entry->driver_data; 1981 1982 if (pdev->dev.platform_data) 1983 memcpy(&info, pdev->dev.platform_data, sizeof(info)); 1984 } 1985 1986 if (!core) { 1987 dev_err(&pdev->dev, "unknown fsi device\n"); 1988 return -ENODEV; 1989 } 1990 1991 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1992 irq = platform_get_irq(pdev, 0); 1993 if (!res || (int)irq <= 0) { 1994 dev_err(&pdev->dev, "Not enough FSI platform resources.\n"); 1995 return -ENODEV; 1996 } 1997 1998 master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL); 1999 if (!master) { 2000 dev_err(&pdev->dev, "Could not allocate master\n"); 2001 return -ENOMEM; 2002 } 2003 2004 master->base = devm_ioremap_nocache(&pdev->dev, 2005 res->start, resource_size(res)); 2006 if (!master->base) { 2007 dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n"); 2008 return -ENXIO; 2009 } 2010 2011 /* master setting */ 2012 master->core = core; 2013 spin_lock_init(&master->lock); 2014 2015 /* FSI A setting */ 2016 fsi = &master->fsia; 2017 fsi->base = master->base; 2018 fsi->master = master; 2019 fsi_port_info_init(fsi, &info.port_a); 2020 fsi_handler_init(fsi, &info.port_a); 2021 ret = fsi_stream_probe(fsi, &pdev->dev); 2022 if (ret < 0) { 2023 dev_err(&pdev->dev, "FSIA stream probe failed\n"); 2024 return ret; 2025 } 2026 2027 /* FSI B setting */ 2028 fsi = &master->fsib; 2029 fsi->base = master->base + 0x40; 2030 fsi->master = master; 2031 fsi_port_info_init(fsi, &info.port_b); 2032 fsi_handler_init(fsi, &info.port_b); 2033 ret = fsi_stream_probe(fsi, &pdev->dev); 2034 if (ret < 0) { 2035 dev_err(&pdev->dev, "FSIB stream probe failed\n"); 2036 goto exit_fsia; 2037 } 2038 2039 pm_runtime_enable(&pdev->dev); 2040 dev_set_drvdata(&pdev->dev, master); 2041 2042 ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0, 2043 dev_name(&pdev->dev), master); 2044 if (ret) { 2045 dev_err(&pdev->dev, "irq request err\n"); 2046 goto exit_fsib; 2047 } 2048 2049 ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform); 2050 if (ret < 0) { 2051 dev_err(&pdev->dev, "cannot snd soc register\n"); 2052 goto exit_fsib; 2053 } 2054 2055 ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component, 2056 fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai)); 2057 if (ret < 0) { 2058 dev_err(&pdev->dev, "cannot snd component register\n"); 2059 goto exit_snd_soc; 2060 } 2061 2062 return ret; 2063 2064 exit_snd_soc: 2065 snd_soc_unregister_platform(&pdev->dev); 2066 exit_fsib: 2067 pm_runtime_disable(&pdev->dev); 2068 fsi_stream_remove(&master->fsib); 2069 exit_fsia: 2070 fsi_stream_remove(&master->fsia); 2071 2072 return ret; 2073 } 2074 2075 static int fsi_remove(struct platform_device *pdev) 2076 { 2077 struct fsi_master *master; 2078 2079 master = dev_get_drvdata(&pdev->dev); 2080 2081 pm_runtime_disable(&pdev->dev); 2082 2083 snd_soc_unregister_component(&pdev->dev); 2084 snd_soc_unregister_platform(&pdev->dev); 2085 2086 fsi_stream_remove(&master->fsia); 2087 fsi_stream_remove(&master->fsib); 2088 2089 return 0; 2090 } 2091 2092 static void __fsi_suspend(struct fsi_priv *fsi, 2093 struct fsi_stream *io, 2094 struct device *dev) 2095 { 2096 if (!fsi_stream_is_working(fsi, io)) 2097 return; 2098 2099 fsi_stream_stop(fsi, io); 2100 fsi_hw_shutdown(fsi, dev); 2101 } 2102 2103 static void __fsi_resume(struct fsi_priv *fsi, 2104 struct fsi_stream *io, 2105 struct device *dev) 2106 { 2107 if (!fsi_stream_is_working(fsi, io)) 2108 return; 2109 2110 fsi_hw_startup(fsi, io, dev); 2111 fsi_stream_start(fsi, io); 2112 } 2113 2114 static int fsi_suspend(struct device *dev) 2115 { 2116 struct fsi_master *master = dev_get_drvdata(dev); 2117 struct fsi_priv *fsia = &master->fsia; 2118 struct fsi_priv *fsib = &master->fsib; 2119 2120 __fsi_suspend(fsia, &fsia->playback, dev); 2121 __fsi_suspend(fsia, &fsia->capture, dev); 2122 2123 __fsi_suspend(fsib, &fsib->playback, dev); 2124 __fsi_suspend(fsib, &fsib->capture, dev); 2125 2126 return 0; 2127 } 2128 2129 static int fsi_resume(struct device *dev) 2130 { 2131 struct fsi_master *master = dev_get_drvdata(dev); 2132 struct fsi_priv *fsia = &master->fsia; 2133 struct fsi_priv *fsib = &master->fsib; 2134 2135 __fsi_resume(fsia, &fsia->playback, dev); 2136 __fsi_resume(fsia, &fsia->capture, dev); 2137 2138 __fsi_resume(fsib, &fsib->playback, dev); 2139 __fsi_resume(fsib, &fsib->capture, dev); 2140 2141 return 0; 2142 } 2143 2144 static struct dev_pm_ops fsi_pm_ops = { 2145 .suspend = fsi_suspend, 2146 .resume = fsi_resume, 2147 }; 2148 2149 static struct fsi_core fsi1_core = { 2150 .ver = 1, 2151 2152 /* Interrupt */ 2153 .int_st = INT_ST, 2154 .iemsk = IEMSK, 2155 .imsk = IMSK, 2156 }; 2157 2158 static struct fsi_core fsi2_core = { 2159 .ver = 2, 2160 2161 /* Interrupt */ 2162 .int_st = CPU_INT_ST, 2163 .iemsk = CPU_IEMSK, 2164 .imsk = CPU_IMSK, 2165 .a_mclk = A_MST_CTLR, 2166 .b_mclk = B_MST_CTLR, 2167 }; 2168 2169 static struct of_device_id fsi_of_match[] = { 2170 { .compatible = "renesas,sh_fsi", .data = &fsi1_core}, 2171 { .compatible = "renesas,sh_fsi2", .data = &fsi2_core}, 2172 {}, 2173 }; 2174 MODULE_DEVICE_TABLE(of, fsi_of_match); 2175 2176 static struct platform_device_id fsi_id_table[] = { 2177 { "sh_fsi", (kernel_ulong_t)&fsi1_core }, 2178 { "sh_fsi2", (kernel_ulong_t)&fsi2_core }, 2179 {}, 2180 }; 2181 MODULE_DEVICE_TABLE(platform, fsi_id_table); 2182 2183 static struct platform_driver fsi_driver = { 2184 .driver = { 2185 .name = "fsi-pcm-audio", 2186 .pm = &fsi_pm_ops, 2187 .of_match_table = fsi_of_match, 2188 }, 2189 .probe = fsi_probe, 2190 .remove = fsi_remove, 2191 .id_table = fsi_id_table, 2192 }; 2193 2194 module_platform_driver(fsi_driver); 2195 2196 MODULE_LICENSE("GPL"); 2197 MODULE_DESCRIPTION("SuperH onchip FSI audio driver"); 2198 MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>"); 2199 MODULE_ALIAS("platform:fsi-pcm-audio"); 2200