11d3279c4SSylwester Nawrocki // SPDX-License-Identifier: GPL-2.0+
21d3279c4SSylwester Nawrocki //
31d3279c4SSylwester Nawrocki // idma.c - I2S0 internal DMA driver
41d3279c4SSylwester Nawrocki //
51d3279c4SSylwester Nawrocki // Copyright (c) 2011 Samsung Electronics Co., Ltd.
61d3279c4SSylwester Nawrocki // http://www.samsung.com
71d3279c4SSylwester Nawrocki
8f09aecd5SSangbeom Kim #include <linux/interrupt.h>
9f09aecd5SSangbeom Kim #include <linux/platform_device.h>
10f09aecd5SSangbeom Kim #include <linux/dma-mapping.h>
11f09aecd5SSangbeom Kim #include <linux/slab.h>
12da155d5bSPaul Gortmaker #include <linux/module.h>
13f09aecd5SSangbeom Kim #include <sound/pcm.h>
14f09aecd5SSangbeom Kim #include <sound/pcm_params.h>
15f09aecd5SSangbeom Kim #include <sound/soc.h>
16f09aecd5SSangbeom Kim
17f09aecd5SSangbeom Kim #include "i2s.h"
18f09aecd5SSangbeom Kim #include "idma.h"
19f09aecd5SSangbeom Kim #include "i2s-regs.h"
20f09aecd5SSangbeom Kim
21f09aecd5SSangbeom Kim #define ST_RUNNING (1<<0)
22f09aecd5SSangbeom Kim #define ST_OPENED (1<<1)
23f09aecd5SSangbeom Kim
24f09aecd5SSangbeom Kim static const struct snd_pcm_hardware idma_hardware = {
25f09aecd5SSangbeom Kim .info = SNDRV_PCM_INFO_INTERLEAVED |
26f09aecd5SSangbeom Kim SNDRV_PCM_INFO_BLOCK_TRANSFER |
27f09aecd5SSangbeom Kim SNDRV_PCM_INFO_MMAP |
28f09aecd5SSangbeom Kim SNDRV_PCM_INFO_MMAP_VALID |
29f09aecd5SSangbeom Kim SNDRV_PCM_INFO_PAUSE |
30f09aecd5SSangbeom Kim SNDRV_PCM_INFO_RESUME,
31f09aecd5SSangbeom Kim .buffer_bytes_max = MAX_IDMA_BUFFER,
32f09aecd5SSangbeom Kim .period_bytes_min = 128,
33f09aecd5SSangbeom Kim .period_bytes_max = MAX_IDMA_PERIOD,
34f09aecd5SSangbeom Kim .periods_min = 1,
35f09aecd5SSangbeom Kim .periods_max = 2,
36f09aecd5SSangbeom Kim };
37f09aecd5SSangbeom Kim
38f09aecd5SSangbeom Kim struct idma_ctrl {
39f09aecd5SSangbeom Kim spinlock_t lock;
40f09aecd5SSangbeom Kim int state;
41f09aecd5SSangbeom Kim dma_addr_t start;
42f09aecd5SSangbeom Kim dma_addr_t pos;
43f09aecd5SSangbeom Kim dma_addr_t end;
44f09aecd5SSangbeom Kim dma_addr_t period;
45f09aecd5SSangbeom Kim dma_addr_t periodsz;
46f09aecd5SSangbeom Kim void *token;
47f09aecd5SSangbeom Kim void (*cb)(void *dt, int bytes_xfer);
48f09aecd5SSangbeom Kim };
49f09aecd5SSangbeom Kim
50f09aecd5SSangbeom Kim static struct idma_info {
51f09aecd5SSangbeom Kim spinlock_t lock;
52f09aecd5SSangbeom Kim void __iomem *regs;
53f09aecd5SSangbeom Kim dma_addr_t lp_tx_addr;
54f09aecd5SSangbeom Kim } idma;
55f09aecd5SSangbeom Kim
56cb00e3a1SArnd Bergmann static int idma_irq;
57cb00e3a1SArnd Bergmann
idma_getpos(dma_addr_t * src)58f09aecd5SSangbeom Kim static void idma_getpos(dma_addr_t *src)
59f09aecd5SSangbeom Kim {
60f09aecd5SSangbeom Kim *src = idma.lp_tx_addr +
61f09aecd5SSangbeom Kim (readl(idma.regs + I2STRNCNT) & 0xffffff) * 4;
62f09aecd5SSangbeom Kim }
63f09aecd5SSangbeom Kim
idma_enqueue(struct snd_pcm_substream * substream)64f09aecd5SSangbeom Kim static int idma_enqueue(struct snd_pcm_substream *substream)
65f09aecd5SSangbeom Kim {
66f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
67f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
68f09aecd5SSangbeom Kim u32 val;
69f09aecd5SSangbeom Kim
70f09aecd5SSangbeom Kim spin_lock(&prtd->lock);
71f09aecd5SSangbeom Kim prtd->token = (void *) substream;
72f09aecd5SSangbeom Kim spin_unlock(&prtd->lock);
73f09aecd5SSangbeom Kim
74f09aecd5SSangbeom Kim /* Internal DMA Level0 Interrupt Address */
75f09aecd5SSangbeom Kim val = idma.lp_tx_addr + prtd->periodsz;
76f09aecd5SSangbeom Kim writel(val, idma.regs + I2SLVL0ADDR);
77f09aecd5SSangbeom Kim
78f09aecd5SSangbeom Kim /* Start address0 of I2S internal DMA operation. */
79f09aecd5SSangbeom Kim val = idma.lp_tx_addr;
80f09aecd5SSangbeom Kim writel(val, idma.regs + I2SSTR0);
81f09aecd5SSangbeom Kim
82f09aecd5SSangbeom Kim /*
83f09aecd5SSangbeom Kim * Transfer block size for I2S internal DMA.
84f09aecd5SSangbeom Kim * Should decide transfer size before start dma operation
85f09aecd5SSangbeom Kim */
86f09aecd5SSangbeom Kim val = readl(idma.regs + I2SSIZE);
87f09aecd5SSangbeom Kim val &= ~(I2SSIZE_TRNMSK << I2SSIZE_SHIFT);
88f09aecd5SSangbeom Kim val |= (((runtime->dma_bytes >> 2) &
89f09aecd5SSangbeom Kim I2SSIZE_TRNMSK) << I2SSIZE_SHIFT);
90f09aecd5SSangbeom Kim writel(val, idma.regs + I2SSIZE);
91f09aecd5SSangbeom Kim
92f09aecd5SSangbeom Kim val = readl(idma.regs + I2SAHB);
93f09aecd5SSangbeom Kim val |= AHB_INTENLVL0;
94f09aecd5SSangbeom Kim writel(val, idma.regs + I2SAHB);
95f09aecd5SSangbeom Kim
96f09aecd5SSangbeom Kim return 0;
97f09aecd5SSangbeom Kim }
98f09aecd5SSangbeom Kim
idma_setcallbk(struct snd_pcm_substream * substream,void (* cb)(void *,int))99f09aecd5SSangbeom Kim static void idma_setcallbk(struct snd_pcm_substream *substream,
100f09aecd5SSangbeom Kim void (*cb)(void *, int))
101f09aecd5SSangbeom Kim {
102f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
103f09aecd5SSangbeom Kim
104f09aecd5SSangbeom Kim spin_lock(&prtd->lock);
105f09aecd5SSangbeom Kim prtd->cb = cb;
106f09aecd5SSangbeom Kim spin_unlock(&prtd->lock);
107f09aecd5SSangbeom Kim }
108f09aecd5SSangbeom Kim
idma_control(int op)109f09aecd5SSangbeom Kim static void idma_control(int op)
110f09aecd5SSangbeom Kim {
111f09aecd5SSangbeom Kim u32 val = readl(idma.regs + I2SAHB);
112f09aecd5SSangbeom Kim
113f09aecd5SSangbeom Kim spin_lock(&idma.lock);
114f09aecd5SSangbeom Kim
115f09aecd5SSangbeom Kim switch (op) {
116f09aecd5SSangbeom Kim case LPAM_DMA_START:
117f09aecd5SSangbeom Kim val |= (AHB_INTENLVL0 | AHB_DMAEN);
118f09aecd5SSangbeom Kim break;
119f09aecd5SSangbeom Kim case LPAM_DMA_STOP:
120f09aecd5SSangbeom Kim val &= ~(AHB_INTENLVL0 | AHB_DMAEN);
121f09aecd5SSangbeom Kim break;
122f09aecd5SSangbeom Kim default:
123f09aecd5SSangbeom Kim spin_unlock(&idma.lock);
124f09aecd5SSangbeom Kim return;
125f09aecd5SSangbeom Kim }
126f09aecd5SSangbeom Kim
127f09aecd5SSangbeom Kim writel(val, idma.regs + I2SAHB);
128f09aecd5SSangbeom Kim spin_unlock(&idma.lock);
129f09aecd5SSangbeom Kim }
130f09aecd5SSangbeom Kim
idma_done(void * id,int bytes_xfer)131f09aecd5SSangbeom Kim static void idma_done(void *id, int bytes_xfer)
132f09aecd5SSangbeom Kim {
133f09aecd5SSangbeom Kim struct snd_pcm_substream *substream = id;
134f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
135f09aecd5SSangbeom Kim
136f09aecd5SSangbeom Kim if (prtd && (prtd->state & ST_RUNNING))
137f09aecd5SSangbeom Kim snd_pcm_period_elapsed(substream);
138f09aecd5SSangbeom Kim }
139f09aecd5SSangbeom Kim
idma_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params)140ba40ab62SKuninori Morimoto static int idma_hw_params(struct snd_soc_component *component,
141ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream,
142f09aecd5SSangbeom Kim struct snd_pcm_hw_params *params)
143f09aecd5SSangbeom Kim {
144f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
145f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
146f09aecd5SSangbeom Kim u32 mod = readl(idma.regs + I2SMOD);
147f09aecd5SSangbeom Kim u32 ahb = readl(idma.regs + I2SAHB);
148f09aecd5SSangbeom Kim
149f09aecd5SSangbeom Kim ahb |= (AHB_DMARLD | AHB_INTMASK);
150f09aecd5SSangbeom Kim mod |= MOD_TXS_IDMA;
151f09aecd5SSangbeom Kim writel(ahb, idma.regs + I2SAHB);
152f09aecd5SSangbeom Kim writel(mod, idma.regs + I2SMOD);
153f09aecd5SSangbeom Kim
154f09aecd5SSangbeom Kim snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
155f09aecd5SSangbeom Kim runtime->dma_bytes = params_buffer_bytes(params);
156f09aecd5SSangbeom Kim
157f09aecd5SSangbeom Kim prtd->start = prtd->pos = runtime->dma_addr;
158f09aecd5SSangbeom Kim prtd->period = params_periods(params);
159f09aecd5SSangbeom Kim prtd->periodsz = params_period_bytes(params);
160f09aecd5SSangbeom Kim prtd->end = runtime->dma_addr + runtime->dma_bytes;
161f09aecd5SSangbeom Kim
162f09aecd5SSangbeom Kim idma_setcallbk(substream, idma_done);
163f09aecd5SSangbeom Kim
164f09aecd5SSangbeom Kim return 0;
165f09aecd5SSangbeom Kim }
166f09aecd5SSangbeom Kim
idma_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)167ba40ab62SKuninori Morimoto static int idma_hw_free(struct snd_soc_component *component,
168ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream)
169f09aecd5SSangbeom Kim {
170f09aecd5SSangbeom Kim snd_pcm_set_runtime_buffer(substream, NULL);
171f09aecd5SSangbeom Kim
172f09aecd5SSangbeom Kim return 0;
173f09aecd5SSangbeom Kim }
174f09aecd5SSangbeom Kim
idma_prepare(struct snd_soc_component * component,struct snd_pcm_substream * substream)175ba40ab62SKuninori Morimoto static int idma_prepare(struct snd_soc_component *component,
176ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream)
177f09aecd5SSangbeom Kim {
178f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
179f09aecd5SSangbeom Kim
180f09aecd5SSangbeom Kim prtd->pos = prtd->start;
181f09aecd5SSangbeom Kim
182f09aecd5SSangbeom Kim /* flush the DMA channel */
183f09aecd5SSangbeom Kim idma_control(LPAM_DMA_STOP);
184f09aecd5SSangbeom Kim idma_enqueue(substream);
185f09aecd5SSangbeom Kim
186f09aecd5SSangbeom Kim return 0;
187f09aecd5SSangbeom Kim }
188f09aecd5SSangbeom Kim
idma_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)189ba40ab62SKuninori Morimoto static int idma_trigger(struct snd_soc_component *component,
190ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream, int cmd)
191f09aecd5SSangbeom Kim {
192f09aecd5SSangbeom Kim struct idma_ctrl *prtd = substream->runtime->private_data;
193f09aecd5SSangbeom Kim int ret = 0;
194f09aecd5SSangbeom Kim
195f09aecd5SSangbeom Kim spin_lock(&prtd->lock);
196f09aecd5SSangbeom Kim
197f09aecd5SSangbeom Kim switch (cmd) {
198f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_RESUME:
199f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_START:
200f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
201f09aecd5SSangbeom Kim prtd->state |= ST_RUNNING;
202f09aecd5SSangbeom Kim idma_control(LPAM_DMA_START);
203f09aecd5SSangbeom Kim break;
204f09aecd5SSangbeom Kim
205f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_SUSPEND:
206f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_STOP:
207f09aecd5SSangbeom Kim case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
208f09aecd5SSangbeom Kim prtd->state &= ~ST_RUNNING;
209f09aecd5SSangbeom Kim idma_control(LPAM_DMA_STOP);
210f09aecd5SSangbeom Kim break;
211f09aecd5SSangbeom Kim
212f09aecd5SSangbeom Kim default:
213f09aecd5SSangbeom Kim ret = -EINVAL;
214f09aecd5SSangbeom Kim break;
215f09aecd5SSangbeom Kim }
216f09aecd5SSangbeom Kim
217f09aecd5SSangbeom Kim spin_unlock(&prtd->lock);
218f09aecd5SSangbeom Kim
219f09aecd5SSangbeom Kim return ret;
220f09aecd5SSangbeom Kim }
221f09aecd5SSangbeom Kim
222f09aecd5SSangbeom Kim static snd_pcm_uframes_t
idma_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream)223ba40ab62SKuninori Morimoto idma_pointer(struct snd_soc_component *component,
224ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream)
225f09aecd5SSangbeom Kim {
226f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
227f09aecd5SSangbeom Kim struct idma_ctrl *prtd = runtime->private_data;
228f09aecd5SSangbeom Kim dma_addr_t src;
229f09aecd5SSangbeom Kim unsigned long res;
230f09aecd5SSangbeom Kim
231f09aecd5SSangbeom Kim spin_lock(&prtd->lock);
232f09aecd5SSangbeom Kim
233f09aecd5SSangbeom Kim idma_getpos(&src);
234f09aecd5SSangbeom Kim res = src - prtd->start;
235f09aecd5SSangbeom Kim
236f09aecd5SSangbeom Kim spin_unlock(&prtd->lock);
237f09aecd5SSangbeom Kim
238f09aecd5SSangbeom Kim return bytes_to_frames(substream->runtime, res);
239f09aecd5SSangbeom Kim }
240f09aecd5SSangbeom Kim
idma_mmap(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct vm_area_struct * vma)241ba40ab62SKuninori Morimoto static int idma_mmap(struct snd_soc_component *component,
242ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream,
243f09aecd5SSangbeom Kim struct vm_area_struct *vma)
244f09aecd5SSangbeom Kim {
245f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
246f09aecd5SSangbeom Kim unsigned long size, offset;
247f09aecd5SSangbeom Kim
248f09aecd5SSangbeom Kim /* From snd_pcm_lib_mmap_iomem */
249f09aecd5SSangbeom Kim vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
250f09aecd5SSangbeom Kim size = vma->vm_end - vma->vm_start;
251f09aecd5SSangbeom Kim offset = vma->vm_pgoff << PAGE_SHIFT;
252*de531908SMinghao Chi return io_remap_pfn_range(vma, vma->vm_start,
253f09aecd5SSangbeom Kim (runtime->dma_addr + offset) >> PAGE_SHIFT,
254f09aecd5SSangbeom Kim size, vma->vm_page_prot);
255f09aecd5SSangbeom Kim }
256f09aecd5SSangbeom Kim
iis_irq(int irqno,void * dev_id)257f09aecd5SSangbeom Kim static irqreturn_t iis_irq(int irqno, void *dev_id)
258f09aecd5SSangbeom Kim {
259f09aecd5SSangbeom Kim struct idma_ctrl *prtd = (struct idma_ctrl *)dev_id;
26041adf905SSachin Kamat u32 iisahb, val, addr;
261f09aecd5SSangbeom Kim
262f09aecd5SSangbeom Kim iisahb = readl(idma.regs + I2SAHB);
263f09aecd5SSangbeom Kim
264f09aecd5SSangbeom Kim val = (iisahb & AHB_LVL0INT) ? AHB_CLRLVL0INT : 0;
265f09aecd5SSangbeom Kim
266f09aecd5SSangbeom Kim if (val) {
267f09aecd5SSangbeom Kim iisahb |= val;
268f09aecd5SSangbeom Kim writel(iisahb, idma.regs + I2SAHB);
269f09aecd5SSangbeom Kim
270f09aecd5SSangbeom Kim addr = readl(idma.regs + I2SLVL0ADDR) - idma.lp_tx_addr;
271f09aecd5SSangbeom Kim addr += prtd->periodsz;
2721aa91b6dSArnd Bergmann addr %= (u32)(prtd->end - prtd->start);
273f09aecd5SSangbeom Kim addr += idma.lp_tx_addr;
274f09aecd5SSangbeom Kim
275f09aecd5SSangbeom Kim writel(addr, idma.regs + I2SLVL0ADDR);
276f09aecd5SSangbeom Kim
277f09aecd5SSangbeom Kim if (prtd->cb)
278f09aecd5SSangbeom Kim prtd->cb(prtd->token, prtd->period);
279f09aecd5SSangbeom Kim }
280f09aecd5SSangbeom Kim
281f09aecd5SSangbeom Kim return IRQ_HANDLED;
282f09aecd5SSangbeom Kim }
283f09aecd5SSangbeom Kim
idma_open(struct snd_soc_component * component,struct snd_pcm_substream * substream)284ba40ab62SKuninori Morimoto static int idma_open(struct snd_soc_component *component,
285ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream)
286f09aecd5SSangbeom Kim {
287f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
288f09aecd5SSangbeom Kim struct idma_ctrl *prtd;
289f09aecd5SSangbeom Kim int ret;
290f09aecd5SSangbeom Kim
291f09aecd5SSangbeom Kim snd_soc_set_runtime_hwparams(substream, &idma_hardware);
292f09aecd5SSangbeom Kim
293f09aecd5SSangbeom Kim prtd = kzalloc(sizeof(struct idma_ctrl), GFP_KERNEL);
294f09aecd5SSangbeom Kim if (prtd == NULL)
295f09aecd5SSangbeom Kim return -ENOMEM;
296f09aecd5SSangbeom Kim
297cb00e3a1SArnd Bergmann ret = request_irq(idma_irq, iis_irq, 0, "i2s", prtd);
298f09aecd5SSangbeom Kim if (ret < 0) {
299f09aecd5SSangbeom Kim pr_err("fail to claim i2s irq , ret = %d\n", ret);
300f09aecd5SSangbeom Kim kfree(prtd);
301f09aecd5SSangbeom Kim return ret;
302f09aecd5SSangbeom Kim }
303f09aecd5SSangbeom Kim
304f09aecd5SSangbeom Kim spin_lock_init(&prtd->lock);
305f09aecd5SSangbeom Kim
306f09aecd5SSangbeom Kim runtime->private_data = prtd;
307f09aecd5SSangbeom Kim
308f09aecd5SSangbeom Kim return 0;
309f09aecd5SSangbeom Kim }
310f09aecd5SSangbeom Kim
idma_close(struct snd_soc_component * component,struct snd_pcm_substream * substream)311ba40ab62SKuninori Morimoto static int idma_close(struct snd_soc_component *component,
312ba40ab62SKuninori Morimoto struct snd_pcm_substream *substream)
313f09aecd5SSangbeom Kim {
314f09aecd5SSangbeom Kim struct snd_pcm_runtime *runtime = substream->runtime;
315f09aecd5SSangbeom Kim struct idma_ctrl *prtd = runtime->private_data;
316f09aecd5SSangbeom Kim
317cb00e3a1SArnd Bergmann free_irq(idma_irq, prtd);
318f09aecd5SSangbeom Kim
319f09aecd5SSangbeom Kim if (!prtd)
320f09aecd5SSangbeom Kim pr_err("idma_close called with prtd == NULL\n");
321f09aecd5SSangbeom Kim
322f09aecd5SSangbeom Kim kfree(prtd);
323f09aecd5SSangbeom Kim
324f09aecd5SSangbeom Kim return 0;
325f09aecd5SSangbeom Kim }
326f09aecd5SSangbeom Kim
idma_free(struct snd_soc_component * component,struct snd_pcm * pcm)327ba40ab62SKuninori Morimoto static void idma_free(struct snd_soc_component *component,
328ba40ab62SKuninori Morimoto struct snd_pcm *pcm)
329f09aecd5SSangbeom Kim {
330f09aecd5SSangbeom Kim struct snd_pcm_substream *substream;
331f09aecd5SSangbeom Kim struct snd_dma_buffer *buf;
332f09aecd5SSangbeom Kim
333f09aecd5SSangbeom Kim substream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
334f09aecd5SSangbeom Kim if (!substream)
335f09aecd5SSangbeom Kim return;
336f09aecd5SSangbeom Kim
337f09aecd5SSangbeom Kim buf = &substream->dma_buffer;
338f09aecd5SSangbeom Kim if (!buf->area)
339f09aecd5SSangbeom Kim return;
340f09aecd5SSangbeom Kim
341e8a70c25SLars-Peter Clausen iounmap((void __iomem *)buf->area);
342f09aecd5SSangbeom Kim
343f09aecd5SSangbeom Kim buf->area = NULL;
344f09aecd5SSangbeom Kim buf->addr = 0;
345f09aecd5SSangbeom Kim }
346f09aecd5SSangbeom Kim
preallocate_idma_buffer(struct snd_pcm * pcm,int stream)347f09aecd5SSangbeom Kim static int preallocate_idma_buffer(struct snd_pcm *pcm, int stream)
348f09aecd5SSangbeom Kim {
349f09aecd5SSangbeom Kim struct snd_pcm_substream *substream = pcm->streams[stream].substream;
350f09aecd5SSangbeom Kim struct snd_dma_buffer *buf = &substream->dma_buffer;
351f09aecd5SSangbeom Kim
352f09aecd5SSangbeom Kim buf->dev.dev = pcm->card->dev;
353f09aecd5SSangbeom Kim buf->private_data = NULL;
354f09aecd5SSangbeom Kim
355f09aecd5SSangbeom Kim /* Assign PCM buffer pointers */
356f09aecd5SSangbeom Kim buf->dev.type = SNDRV_DMA_TYPE_CONTINUOUS;
357f09aecd5SSangbeom Kim buf->addr = idma.lp_tx_addr;
358f09aecd5SSangbeom Kim buf->bytes = idma_hardware.buffer_bytes_max;
359e8a70c25SLars-Peter Clausen buf->area = (unsigned char * __force)ioremap(buf->addr, buf->bytes);
3603ecb4675SJiasheng Jiang if (!buf->area)
3613ecb4675SJiasheng Jiang return -ENOMEM;
362f09aecd5SSangbeom Kim
363f09aecd5SSangbeom Kim return 0;
364f09aecd5SSangbeom Kim }
365f09aecd5SSangbeom Kim
idma_new(struct snd_soc_component * component,struct snd_soc_pcm_runtime * rtd)366ba40ab62SKuninori Morimoto static int idma_new(struct snd_soc_component *component,
367ba40ab62SKuninori Morimoto struct snd_soc_pcm_runtime *rtd)
368f09aecd5SSangbeom Kim {
369f09aecd5SSangbeom Kim struct snd_card *card = rtd->card->snd_card;
370f09aecd5SSangbeom Kim struct snd_pcm *pcm = rtd->pcm;
371c9bd5e69SRussell King int ret;
372f09aecd5SSangbeom Kim
373c9bd5e69SRussell King ret = dma_coerce_mask_and_coherent(card->dev, DMA_BIT_MASK(32));
374c9bd5e69SRussell King if (ret)
375c9bd5e69SRussell King return ret;
376f09aecd5SSangbeom Kim
37725e9e756SJoachim Eastwood if (pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream) {
378f09aecd5SSangbeom Kim ret = preallocate_idma_buffer(pcm,
379f09aecd5SSangbeom Kim SNDRV_PCM_STREAM_PLAYBACK);
380b2ed1b0bSMark Brown }
381f09aecd5SSangbeom Kim
382f09aecd5SSangbeom Kim return ret;
383f09aecd5SSangbeom Kim }
384f09aecd5SSangbeom Kim
idma_reg_addr_init(void __iomem * regs,dma_addr_t addr)3859b8f5695SMark Brown void idma_reg_addr_init(void __iomem *regs, dma_addr_t addr)
386f09aecd5SSangbeom Kim {
387f09aecd5SSangbeom Kim spin_lock_init(&idma.lock);
388f09aecd5SSangbeom Kim idma.regs = regs;
389f09aecd5SSangbeom Kim idma.lp_tx_addr = addr;
390f09aecd5SSangbeom Kim }
3910930c33aSArnd Bergmann EXPORT_SYMBOL_GPL(idma_reg_addr_init);
392f09aecd5SSangbeom Kim
39317d619daSKuninori Morimoto static const struct snd_soc_component_driver asoc_idma_platform = {
394ba40ab62SKuninori Morimoto .open = idma_open,
395ba40ab62SKuninori Morimoto .close = idma_close,
396ba40ab62SKuninori Morimoto .trigger = idma_trigger,
397ba40ab62SKuninori Morimoto .pointer = idma_pointer,
398ba40ab62SKuninori Morimoto .mmap = idma_mmap,
399ba40ab62SKuninori Morimoto .hw_params = idma_hw_params,
400ba40ab62SKuninori Morimoto .hw_free = idma_hw_free,
401ba40ab62SKuninori Morimoto .prepare = idma_prepare,
402ba40ab62SKuninori Morimoto .pcm_construct = idma_new,
403ba40ab62SKuninori Morimoto .pcm_destruct = idma_free,
404f09aecd5SSangbeom Kim };
405f09aecd5SSangbeom Kim
asoc_idma_platform_probe(struct platform_device * pdev)406fdca21adSBill Pemberton static int asoc_idma_platform_probe(struct platform_device *pdev)
407f09aecd5SSangbeom Kim {
408cb00e3a1SArnd Bergmann idma_irq = platform_get_irq(pdev, 0);
409cb00e3a1SArnd Bergmann if (idma_irq < 0)
410cb00e3a1SArnd Bergmann return idma_irq;
411cb00e3a1SArnd Bergmann
41217d619daSKuninori Morimoto return devm_snd_soc_register_component(&pdev->dev, &asoc_idma_platform,
41317d619daSKuninori Morimoto NULL, 0);
414f09aecd5SSangbeom Kim }
415f09aecd5SSangbeom Kim
416f09aecd5SSangbeom Kim static struct platform_driver asoc_idma_driver = {
417f09aecd5SSangbeom Kim .driver = {
418f09aecd5SSangbeom Kim .name = "samsung-idma",
419f09aecd5SSangbeom Kim },
420f09aecd5SSangbeom Kim
421f09aecd5SSangbeom Kim .probe = asoc_idma_platform_probe,
422f09aecd5SSangbeom Kim };
423f09aecd5SSangbeom Kim
424e00c3f55SMark Brown module_platform_driver(asoc_idma_driver);
425f09aecd5SSangbeom Kim
426f09aecd5SSangbeom Kim MODULE_AUTHOR("Jaswinder Singh, <jassisinghbrar@gmail.com>");
427f09aecd5SSangbeom Kim MODULE_DESCRIPTION("Samsung ASoC IDMA Driver");
428f09aecd5SSangbeom Kim MODULE_LICENSE("GPL");
429