1 // SPDX-License-Identifier: GPL-2.0-only 2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver 3 4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd. 5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com> 6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <linux/spinlock.h> 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 21 #include "rockchip_i2s_tdm.h" 22 23 #define DRV_NAME "rockchip-i2s-tdm" 24 25 #define DEFAULT_MCLK_FS 256 26 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */ 27 #define MULTIPLEX_CH_MAX 10 28 29 #define TRCM_TXRX 0 30 #define TRCM_TX 1 31 #define TRCM_RX 2 32 33 struct txrx_config { 34 u32 addr; 35 u32 reg; 36 u32 txonly; 37 u32 rxonly; 38 }; 39 40 struct rk_i2s_soc_data { 41 u32 softrst_offset; 42 u32 grf_reg_offset; 43 u32 grf_shift; 44 int config_count; 45 const struct txrx_config *configs; 46 int (*init)(struct device *dev, u32 addr); 47 }; 48 49 struct rk_i2s_tdm_dev { 50 struct device *dev; 51 struct clk *hclk; 52 struct clk *mclk_tx; 53 struct clk *mclk_rx; 54 struct regmap *regmap; 55 struct regmap *grf; 56 struct snd_dmaengine_dai_dma_data capture_dma_data; 57 struct snd_dmaengine_dai_dma_data playback_dma_data; 58 struct reset_control *tx_reset; 59 struct reset_control *rx_reset; 60 const struct rk_i2s_soc_data *soc_data; 61 bool is_master_mode; 62 bool io_multiplex; 63 bool tdm_mode; 64 unsigned int frame_width; 65 unsigned int clk_trcm; 66 unsigned int i2s_sdis[CH_GRP_MAX]; 67 unsigned int i2s_sdos[CH_GRP_MAX]; 68 int refcount; 69 spinlock_t lock; /* xfer lock */ 70 bool has_playback; 71 bool has_capture; 72 struct snd_soc_dai_driver *dai; 73 }; 74 75 static int to_ch_num(unsigned int val) 76 { 77 switch (val) { 78 case I2S_CHN_4: 79 return 4; 80 case I2S_CHN_6: 81 return 6; 82 case I2S_CHN_8: 83 return 8; 84 default: 85 return 2; 86 } 87 } 88 89 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 90 { 91 clk_disable_unprepare(i2s_tdm->mclk_tx); 92 clk_disable_unprepare(i2s_tdm->mclk_rx); 93 } 94 95 /** 96 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on 97 * failure. 98 * @i2s_tdm: rk_i2s_tdm_dev struct 99 * 100 * This function attempts to enable all mclk clocks, but cleans up after 101 * itself on failure. Guarantees to balance its calls. 102 * 103 * Returns success (0) or negative errno. 104 */ 105 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 106 { 107 int ret = 0; 108 109 ret = clk_prepare_enable(i2s_tdm->mclk_tx); 110 if (ret) 111 goto err_mclk_tx; 112 ret = clk_prepare_enable(i2s_tdm->mclk_rx); 113 if (ret) 114 goto err_mclk_rx; 115 116 return 0; 117 118 err_mclk_rx: 119 clk_disable_unprepare(i2s_tdm->mclk_tx); 120 err_mclk_tx: 121 return ret; 122 } 123 124 static int __maybe_unused i2s_tdm_runtime_suspend(struct device *dev) 125 { 126 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 127 128 regcache_cache_only(i2s_tdm->regmap, true); 129 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 130 131 clk_disable_unprepare(i2s_tdm->hclk); 132 133 return 0; 134 } 135 136 static int __maybe_unused i2s_tdm_runtime_resume(struct device *dev) 137 { 138 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 139 int ret; 140 141 ret = clk_prepare_enable(i2s_tdm->hclk); 142 if (ret) 143 goto err_hclk; 144 145 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 146 if (ret) 147 goto err_mclk; 148 149 regcache_cache_only(i2s_tdm->regmap, false); 150 regcache_mark_dirty(i2s_tdm->regmap); 151 152 ret = regcache_sync(i2s_tdm->regmap); 153 if (ret) 154 goto err_regcache; 155 156 return 0; 157 158 err_regcache: 159 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 160 err_mclk: 161 clk_disable_unprepare(i2s_tdm->hclk); 162 err_hclk: 163 return ret; 164 } 165 166 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai) 167 { 168 return snd_soc_dai_get_drvdata(dai); 169 } 170 171 /* 172 * Makes sure that both tx and rx are reset at the same time to sync lrck 173 * when clk_trcm > 0. 174 */ 175 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm) 176 { 177 /* This is technically race-y. 178 * 179 * In an ideal world, we could atomically assert both resets at the 180 * same time, through an atomic bulk reset API. This API however does 181 * not exist, so what the downstream vendor code used to do was 182 * implement half a reset controller here and require the CRU to be 183 * passed to the driver as a device tree node. Violating abstractions 184 * like that is bad, especially when it influences something like the 185 * bindings which are supposed to describe the hardware, not whatever 186 * workarounds the driver needs, so it was dropped. 187 * 188 * In practice, asserting the resets one by one appears to work just 189 * fine for playback. During duplex (playback + capture) operation, 190 * this might become an issue, but that should be solved by the 191 * implementation of the aforementioned API, not by shoving a reset 192 * controller into an audio driver. 193 */ 194 195 reset_control_assert(i2s_tdm->tx_reset); 196 reset_control_assert(i2s_tdm->rx_reset); 197 udelay(10); 198 reset_control_deassert(i2s_tdm->tx_reset); 199 reset_control_deassert(i2s_tdm->rx_reset); 200 udelay(10); 201 } 202 203 static void rockchip_snd_reset(struct reset_control *rc) 204 { 205 reset_control_assert(rc); 206 udelay(10); 207 reset_control_deassert(rc); 208 udelay(10); 209 } 210 211 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm, 212 unsigned int clr) 213 { 214 unsigned int xfer_mask = 0; 215 unsigned int xfer_val = 0; 216 unsigned int val; 217 int retry = 10; 218 bool tx = clr & I2S_CLR_TXC; 219 bool rx = clr & I2S_CLR_RXC; 220 221 if (!(rx || tx)) 222 return; 223 224 if (tx) { 225 xfer_mask = I2S_XFER_TXS_START; 226 xfer_val = I2S_XFER_TXS_STOP; 227 } 228 if (rx) { 229 xfer_mask |= I2S_XFER_RXS_START; 230 xfer_val |= I2S_XFER_RXS_STOP; 231 } 232 233 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val); 234 udelay(150); 235 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr); 236 237 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 238 /* Wait on the clear operation to finish */ 239 while (val) { 240 udelay(15); 241 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 242 retry--; 243 if (!retry) { 244 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n", 245 tx ? "tx" : "", rx ? "rx" : ""); 246 if (rx && tx) 247 rockchip_snd_xfer_sync_reset(i2s_tdm); 248 else if (tx) 249 rockchip_snd_reset(i2s_tdm->tx_reset); 250 else if (rx) 251 rockchip_snd_reset(i2s_tdm->rx_reset); 252 break; 253 } 254 } 255 } 256 257 static inline void rockchip_enable_tde(struct regmap *regmap) 258 { 259 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 260 I2S_DMACR_TDE_ENABLE); 261 } 262 263 static inline void rockchip_disable_tde(struct regmap *regmap) 264 { 265 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 266 I2S_DMACR_TDE_DISABLE); 267 } 268 269 static inline void rockchip_enable_rde(struct regmap *regmap) 270 { 271 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 272 I2S_DMACR_RDE_ENABLE); 273 } 274 275 static inline void rockchip_disable_rde(struct regmap *regmap) 276 { 277 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 278 I2S_DMACR_RDE_DISABLE); 279 } 280 281 /* only used when clk_trcm > 0 */ 282 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream, 283 struct snd_soc_dai *dai, int on) 284 { 285 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 286 unsigned long flags; 287 288 spin_lock_irqsave(&i2s_tdm->lock, flags); 289 if (on) { 290 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 291 rockchip_enable_tde(i2s_tdm->regmap); 292 else 293 rockchip_enable_rde(i2s_tdm->regmap); 294 295 if (++i2s_tdm->refcount == 1) { 296 rockchip_snd_xfer_sync_reset(i2s_tdm); 297 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 298 I2S_XFER_TXS_START | 299 I2S_XFER_RXS_START, 300 I2S_XFER_TXS_START | 301 I2S_XFER_RXS_START); 302 } 303 } else { 304 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 305 rockchip_disable_tde(i2s_tdm->regmap); 306 else 307 rockchip_disable_rde(i2s_tdm->regmap); 308 309 if (--i2s_tdm->refcount == 0) { 310 rockchip_snd_xfer_clear(i2s_tdm, 311 I2S_CLR_TXC | I2S_CLR_RXC); 312 } 313 } 314 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 315 } 316 317 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 318 { 319 if (on) { 320 rockchip_enable_tde(i2s_tdm->regmap); 321 322 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 323 I2S_XFER_TXS_START, 324 I2S_XFER_TXS_START); 325 } else { 326 rockchip_disable_tde(i2s_tdm->regmap); 327 328 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC); 329 } 330 } 331 332 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 333 { 334 if (on) { 335 rockchip_enable_rde(i2s_tdm->regmap); 336 337 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 338 I2S_XFER_RXS_START, 339 I2S_XFER_RXS_START); 340 } else { 341 rockchip_disable_rde(i2s_tdm->regmap); 342 343 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC); 344 } 345 } 346 347 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai, 348 unsigned int fmt) 349 { 350 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai); 351 unsigned int mask, val, tdm_val, txcr_val, rxcr_val; 352 int ret; 353 bool is_tdm = i2s_tdm->tdm_mode; 354 355 ret = pm_runtime_resume_and_get(cpu_dai->dev); 356 if (ret < 0 && ret != -EACCES) 357 return ret; 358 359 mask = I2S_CKR_MSS_MASK; 360 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 361 case SND_SOC_DAIFMT_BP_FP: 362 val = I2S_CKR_MSS_MASTER; 363 i2s_tdm->is_master_mode = true; 364 break; 365 case SND_SOC_DAIFMT_BC_FC: 366 val = I2S_CKR_MSS_SLAVE; 367 i2s_tdm->is_master_mode = false; 368 break; 369 default: 370 ret = -EINVAL; 371 goto err_pm_put; 372 } 373 374 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 375 376 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 377 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 378 case SND_SOC_DAIFMT_NB_NF: 379 val = I2S_CKR_CKP_NORMAL | 380 I2S_CKR_TLP_NORMAL | 381 I2S_CKR_RLP_NORMAL; 382 break; 383 case SND_SOC_DAIFMT_NB_IF: 384 val = I2S_CKR_CKP_NORMAL | 385 I2S_CKR_TLP_INVERTED | 386 I2S_CKR_RLP_INVERTED; 387 break; 388 case SND_SOC_DAIFMT_IB_NF: 389 val = I2S_CKR_CKP_INVERTED | 390 I2S_CKR_TLP_NORMAL | 391 I2S_CKR_RLP_NORMAL; 392 break; 393 case SND_SOC_DAIFMT_IB_IF: 394 val = I2S_CKR_CKP_INVERTED | 395 I2S_CKR_TLP_INVERTED | 396 I2S_CKR_RLP_INVERTED; 397 break; 398 default: 399 ret = -EINVAL; 400 goto err_pm_put; 401 } 402 403 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 404 405 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 406 case SND_SOC_DAIFMT_RIGHT_J: 407 txcr_val = I2S_TXCR_IBM_RSJM; 408 rxcr_val = I2S_RXCR_IBM_RSJM; 409 break; 410 case SND_SOC_DAIFMT_LEFT_J: 411 txcr_val = I2S_TXCR_IBM_LSJM; 412 rxcr_val = I2S_RXCR_IBM_LSJM; 413 break; 414 case SND_SOC_DAIFMT_I2S: 415 txcr_val = I2S_TXCR_IBM_NORMAL; 416 rxcr_val = I2S_RXCR_IBM_NORMAL; 417 break; 418 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */ 419 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 420 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 421 break; 422 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 423 txcr_val = I2S_TXCR_TFS_PCM; 424 rxcr_val = I2S_RXCR_TFS_PCM; 425 break; 426 default: 427 ret = -EINVAL; 428 goto err_pm_put; 429 } 430 431 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 432 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val); 433 434 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 435 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val); 436 437 if (is_tdm) { 438 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 439 case SND_SOC_DAIFMT_RIGHT_J: 440 val = I2S_TXCR_TFS_TDM_I2S; 441 tdm_val = TDM_SHIFT_CTRL(2); 442 break; 443 case SND_SOC_DAIFMT_LEFT_J: 444 val = I2S_TXCR_TFS_TDM_I2S; 445 tdm_val = TDM_SHIFT_CTRL(1); 446 break; 447 case SND_SOC_DAIFMT_I2S: 448 val = I2S_TXCR_TFS_TDM_I2S; 449 tdm_val = TDM_SHIFT_CTRL(0); 450 break; 451 case SND_SOC_DAIFMT_DSP_A: 452 val = I2S_TXCR_TFS_TDM_PCM; 453 tdm_val = TDM_SHIFT_CTRL(0); 454 break; 455 case SND_SOC_DAIFMT_DSP_B: 456 val = I2S_TXCR_TFS_TDM_PCM; 457 tdm_val = TDM_SHIFT_CTRL(2); 458 break; 459 default: 460 ret = -EINVAL; 461 goto err_pm_put; 462 } 463 464 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1); 465 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME; 466 467 mask = I2S_TXCR_TFS_MASK; 468 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val); 469 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val); 470 471 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK | 472 TDM_SHIFT_CTRL_MSK; 473 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 474 mask, tdm_val); 475 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 476 mask, tdm_val); 477 } 478 479 err_pm_put: 480 pm_runtime_put(cpu_dai->dev); 481 482 return ret; 483 } 484 485 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream, 486 struct rk_i2s_tdm_dev *i2s_tdm) 487 { 488 int stream; 489 490 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 491 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 492 rockchip_disable_tde(i2s_tdm->regmap); 493 else 494 rockchip_disable_rde(i2s_tdm->regmap); 495 496 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC); 497 } 498 499 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream, 500 struct rk_i2s_tdm_dev *i2s_tdm) 501 { 502 int stream; 503 504 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 505 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 506 rockchip_enable_tde(i2s_tdm->regmap); 507 else 508 rockchip_enable_rde(i2s_tdm->regmap); 509 510 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 511 I2S_XFER_TXS_START | 512 I2S_XFER_RXS_START, 513 I2S_XFER_TXS_START | 514 I2S_XFER_RXS_START); 515 } 516 517 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream, 518 struct snd_soc_dai *dai) 519 { 520 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 521 int usable_chs = MULTIPLEX_CH_MAX; 522 unsigned int val = 0; 523 524 if (!i2s_tdm->io_multiplex) 525 return 0; 526 527 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 528 dev_err(i2s_tdm->dev, 529 "io multiplex not supported for this device\n"); 530 return -EINVAL; 531 } 532 533 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 534 struct snd_pcm_str *playback_str = 535 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; 536 537 if (playback_str->substream_opened) { 538 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 539 val &= I2S_TXCR_CSR_MASK; 540 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 541 } 542 543 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 544 val &= I2S_RXCR_CSR_MASK; 545 546 if (to_ch_num(val) > usable_chs) { 547 dev_err(i2s_tdm->dev, 548 "Capture channels (%d) > usable channels (%d)\n", 549 to_ch_num(val), usable_chs); 550 return -EINVAL; 551 } 552 553 } else { 554 struct snd_pcm_str *capture_str = 555 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; 556 557 if (capture_str->substream_opened) { 558 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 559 val &= I2S_RXCR_CSR_MASK; 560 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 561 } 562 563 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 564 val &= I2S_TXCR_CSR_MASK; 565 566 if (to_ch_num(val) > usable_chs) { 567 dev_err(i2s_tdm->dev, 568 "Playback channels (%d) > usable channels (%d)\n", 569 to_ch_num(val), usable_chs); 570 return -EINVAL; 571 } 572 } 573 574 val <<= i2s_tdm->soc_data->grf_shift; 575 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16; 576 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val); 577 578 return 0; 579 } 580 581 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream, 582 struct snd_soc_dai *dai, 583 unsigned int div_bclk, 584 unsigned int div_lrck, 585 unsigned int fmt) 586 { 587 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 588 unsigned long flags; 589 590 if (!i2s_tdm->clk_trcm) 591 return 0; 592 593 spin_lock_irqsave(&i2s_tdm->lock, flags); 594 if (i2s_tdm->refcount) 595 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm); 596 597 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 598 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK, 599 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk)); 600 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 601 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK, 602 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck)); 603 604 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 605 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 606 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 607 fmt); 608 else 609 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 610 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 611 fmt); 612 613 if (i2s_tdm->refcount) 614 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm); 615 spin_unlock_irqrestore(&i2s_tdm->lock, flags); 616 617 return 0; 618 } 619 620 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream, 621 struct snd_pcm_hw_params *params, 622 struct snd_soc_dai *dai) 623 { 624 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 625 unsigned int val = 0; 626 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64; 627 int err; 628 629 if (i2s_tdm->is_master_mode) { 630 struct clk *mclk; 631 632 if (i2s_tdm->clk_trcm == TRCM_TX) { 633 mclk = i2s_tdm->mclk_tx; 634 } else if (i2s_tdm->clk_trcm == TRCM_RX) { 635 mclk = i2s_tdm->mclk_rx; 636 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 637 mclk = i2s_tdm->mclk_tx; 638 } else { 639 mclk = i2s_tdm->mclk_rx; 640 } 641 642 err = clk_set_rate(mclk, DEFAULT_MCLK_FS * params_rate(params)); 643 if (err) 644 return err; 645 646 mclk_rate = clk_get_rate(mclk); 647 bclk_rate = i2s_tdm->frame_width * params_rate(params); 648 if (!bclk_rate) 649 return -EINVAL; 650 651 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 652 div_lrck = bclk_rate / params_rate(params); 653 } 654 655 switch (params_format(params)) { 656 case SNDRV_PCM_FORMAT_S8: 657 val |= I2S_TXCR_VDW(8); 658 break; 659 case SNDRV_PCM_FORMAT_S16_LE: 660 val |= I2S_TXCR_VDW(16); 661 break; 662 case SNDRV_PCM_FORMAT_S20_3LE: 663 val |= I2S_TXCR_VDW(20); 664 break; 665 case SNDRV_PCM_FORMAT_S24_LE: 666 val |= I2S_TXCR_VDW(24); 667 break; 668 case SNDRV_PCM_FORMAT_S32_LE: 669 val |= I2S_TXCR_VDW(32); 670 break; 671 default: 672 return -EINVAL; 673 } 674 675 switch (params_channels(params)) { 676 case 8: 677 val |= I2S_CHN_8; 678 break; 679 case 6: 680 val |= I2S_CHN_6; 681 break; 682 case 4: 683 val |= I2S_CHN_4; 684 break; 685 case 2: 686 val |= I2S_CHN_2; 687 break; 688 default: 689 return -EINVAL; 690 } 691 692 if (i2s_tdm->clk_trcm) { 693 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val); 694 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 695 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 696 I2S_CLKDIV_TXM_MASK, 697 I2S_CLKDIV_TXM(div_bclk)); 698 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 699 I2S_CKR_TSD_MASK, 700 I2S_CKR_TSD(div_lrck)); 701 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 702 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 703 val); 704 } else { 705 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 706 I2S_CLKDIV_RXM_MASK, 707 I2S_CLKDIV_RXM(div_bclk)); 708 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 709 I2S_CKR_RSD_MASK, 710 I2S_CKR_RSD(div_lrck)); 711 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 712 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 713 val); 714 } 715 716 return rockchip_i2s_io_multiplex(substream, dai); 717 } 718 719 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream, 720 int cmd, struct snd_soc_dai *dai) 721 { 722 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 723 724 switch (cmd) { 725 case SNDRV_PCM_TRIGGER_START: 726 case SNDRV_PCM_TRIGGER_RESUME: 727 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 728 if (i2s_tdm->clk_trcm) 729 rockchip_snd_txrxctrl(substream, dai, 1); 730 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 731 rockchip_snd_rxctrl(i2s_tdm, 1); 732 else 733 rockchip_snd_txctrl(i2s_tdm, 1); 734 break; 735 case SNDRV_PCM_TRIGGER_SUSPEND: 736 case SNDRV_PCM_TRIGGER_STOP: 737 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 738 if (i2s_tdm->clk_trcm) 739 rockchip_snd_txrxctrl(substream, dai, 0); 740 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 741 rockchip_snd_rxctrl(i2s_tdm, 0); 742 else 743 rockchip_snd_txctrl(i2s_tdm, 0); 744 break; 745 default: 746 return -EINVAL; 747 } 748 749 return 0; 750 } 751 752 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai) 753 { 754 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 755 756 if (i2s_tdm->has_capture) 757 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data); 758 if (i2s_tdm->has_playback) 759 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data); 760 761 return 0; 762 } 763 764 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai, 765 unsigned int tx_mask, unsigned int rx_mask, 766 int slots, int slot_width) 767 { 768 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 769 unsigned int mask, val; 770 771 i2s_tdm->tdm_mode = true; 772 i2s_tdm->frame_width = slots * slot_width; 773 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK; 774 val = TDM_SLOT_BIT_WIDTH(slot_width) | 775 TDM_FRAME_WIDTH(slots * slot_width); 776 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 777 mask, val); 778 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 779 mask, val); 780 781 return 0; 782 } 783 784 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai, 785 unsigned int ratio) 786 { 787 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 788 789 if (ratio < 32 || ratio > 512 || ratio % 2 == 1) 790 return -EINVAL; 791 792 i2s_tdm->frame_width = ratio; 793 794 return 0; 795 } 796 797 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = { 798 .probe = rockchip_i2s_tdm_dai_probe, 799 .hw_params = rockchip_i2s_tdm_hw_params, 800 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio, 801 .set_fmt = rockchip_i2s_tdm_set_fmt, 802 .set_tdm_slot = rockchip_dai_tdm_slot, 803 .trigger = rockchip_i2s_tdm_trigger, 804 }; 805 806 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = { 807 .name = DRV_NAME, 808 .legacy_dai_naming = 1, 809 }; 810 811 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg) 812 { 813 switch (reg) { 814 case I2S_TXCR: 815 case I2S_RXCR: 816 case I2S_CKR: 817 case I2S_DMACR: 818 case I2S_INTCR: 819 case I2S_XFER: 820 case I2S_CLR: 821 case I2S_TXDR: 822 case I2S_TDM_TXCR: 823 case I2S_TDM_RXCR: 824 case I2S_CLKDIV: 825 return true; 826 default: 827 return false; 828 } 829 } 830 831 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg) 832 { 833 switch (reg) { 834 case I2S_TXCR: 835 case I2S_RXCR: 836 case I2S_CKR: 837 case I2S_DMACR: 838 case I2S_INTCR: 839 case I2S_XFER: 840 case I2S_CLR: 841 case I2S_TXDR: 842 case I2S_RXDR: 843 case I2S_TXFIFOLR: 844 case I2S_INTSR: 845 case I2S_RXFIFOLR: 846 case I2S_TDM_TXCR: 847 case I2S_TDM_RXCR: 848 case I2S_CLKDIV: 849 return true; 850 default: 851 return false; 852 } 853 } 854 855 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg) 856 { 857 switch (reg) { 858 case I2S_TXFIFOLR: 859 case I2S_INTSR: 860 case I2S_CLR: 861 case I2S_TXDR: 862 case I2S_RXDR: 863 case I2S_RXFIFOLR: 864 return true; 865 default: 866 return false; 867 } 868 } 869 870 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg) 871 { 872 if (reg == I2S_RXDR) 873 return true; 874 return false; 875 } 876 877 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = { 878 {0x00, 0x7200000f}, 879 {0x04, 0x01c8000f}, 880 {0x08, 0x00001f1f}, 881 {0x10, 0x001f0000}, 882 {0x14, 0x01f00000}, 883 {0x30, 0x00003eff}, 884 {0x34, 0x00003eff}, 885 {0x38, 0x00000707}, 886 }; 887 888 static const struct regmap_config rockchip_i2s_tdm_regmap_config = { 889 .reg_bits = 32, 890 .reg_stride = 4, 891 .val_bits = 32, 892 .max_register = I2S_CLKDIV, 893 .reg_defaults = rockchip_i2s_tdm_reg_defaults, 894 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults), 895 .writeable_reg = rockchip_i2s_tdm_wr_reg, 896 .readable_reg = rockchip_i2s_tdm_rd_reg, 897 .volatile_reg = rockchip_i2s_tdm_volatile_reg, 898 .precious_reg = rockchip_i2s_tdm_precious_reg, 899 .cache_type = REGCACHE_FLAT, 900 }; 901 902 static int common_soc_init(struct device *dev, u32 addr) 903 { 904 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 905 const struct txrx_config *configs = i2s_tdm->soc_data->configs; 906 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm; 907 int i; 908 909 if (trcm == TRCM_TXRX) 910 return 0; 911 912 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 913 dev_err(i2s_tdm->dev, 914 "no grf present but non-txrx TRCM specified\n"); 915 return -EINVAL; 916 } 917 918 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { 919 if (addr != configs[i].addr) 920 continue; 921 reg = configs[i].reg; 922 if (trcm == TRCM_TX) 923 val = configs[i].txonly; 924 else 925 val = configs[i].rxonly; 926 927 if (reg) 928 regmap_write(i2s_tdm->grf, reg, val); 929 } 930 931 return 0; 932 } 933 934 static const struct txrx_config px30_txrx_config[] = { 935 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY }, 936 }; 937 938 static const struct txrx_config rk1808_txrx_config[] = { 939 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY }, 940 }; 941 942 static const struct txrx_config rk3308_txrx_config[] = { 943 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY }, 944 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY }, 945 }; 946 947 static const struct txrx_config rk3568_txrx_config[] = { 948 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY }, 949 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE }, 950 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE }, 951 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY }, 952 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY }, 953 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE }, 954 }; 955 956 static const struct txrx_config rv1126_txrx_config[] = { 957 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY }, 958 }; 959 960 static const struct rk_i2s_soc_data px30_i2s_soc_data = { 961 .softrst_offset = 0x0300, 962 .configs = px30_txrx_config, 963 .config_count = ARRAY_SIZE(px30_txrx_config), 964 .init = common_soc_init, 965 }; 966 967 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = { 968 .softrst_offset = 0x0300, 969 .configs = rk1808_txrx_config, 970 .config_count = ARRAY_SIZE(rk1808_txrx_config), 971 .init = common_soc_init, 972 }; 973 974 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = { 975 .softrst_offset = 0x0400, 976 .grf_reg_offset = 0x0308, 977 .grf_shift = 5, 978 .configs = rk3308_txrx_config, 979 .config_count = ARRAY_SIZE(rk3308_txrx_config), 980 .init = common_soc_init, 981 }; 982 983 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = { 984 .softrst_offset = 0x0400, 985 .configs = rk3568_txrx_config, 986 .config_count = ARRAY_SIZE(rk3568_txrx_config), 987 .init = common_soc_init, 988 }; 989 990 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = { 991 .softrst_offset = 0x0300, 992 .configs = rv1126_txrx_config, 993 .config_count = ARRAY_SIZE(rv1126_txrx_config), 994 .init = common_soc_init, 995 }; 996 997 static const struct of_device_id rockchip_i2s_tdm_match[] = { 998 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data }, 999 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, 1000 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, 1001 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, 1002 { .compatible = "rockchip,rk3588-i2s-tdm" }, 1003 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, 1004 {}, 1005 }; 1006 1007 static const struct snd_soc_dai_driver i2s_tdm_dai = { 1008 .ops = &rockchip_i2s_tdm_dai_ops, 1009 }; 1010 1011 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm) 1012 { 1013 struct snd_soc_dai_driver *dai; 1014 struct property *dma_names; 1015 const char *dma_name; 1016 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | 1017 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | 1018 SNDRV_PCM_FMTBIT_S32_LE); 1019 struct device_node *node = i2s_tdm->dev->of_node; 1020 1021 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1022 if (!strcmp(dma_name, "tx")) 1023 i2s_tdm->has_playback = true; 1024 if (!strcmp(dma_name, "rx")) 1025 i2s_tdm->has_capture = true; 1026 } 1027 1028 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai, 1029 sizeof(*dai), GFP_KERNEL); 1030 if (!dai) 1031 return -ENOMEM; 1032 1033 if (i2s_tdm->has_playback) { 1034 dai->playback.stream_name = "Playback"; 1035 dai->playback.channels_min = 2; 1036 dai->playback.channels_max = 8; 1037 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 1038 dai->playback.formats = formats; 1039 } 1040 1041 if (i2s_tdm->has_capture) { 1042 dai->capture.stream_name = "Capture"; 1043 dai->capture.channels_min = 2; 1044 dai->capture.channels_max = 8; 1045 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 1046 dai->capture.formats = formats; 1047 } 1048 1049 if (i2s_tdm->clk_trcm != TRCM_TXRX) 1050 dai->symmetric_rate = 1; 1051 1052 i2s_tdm->dai = dai; 1053 1054 return 0; 1055 } 1056 1057 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm, 1058 int num, 1059 bool is_rx_path) 1060 { 1061 unsigned int *i2s_data; 1062 int i, j; 1063 1064 if (is_rx_path) 1065 i2s_data = i2s_tdm->i2s_sdis; 1066 else 1067 i2s_data = i2s_tdm->i2s_sdos; 1068 1069 for (i = 0; i < num; i++) { 1070 if (i2s_data[i] > CH_GRP_MAX - 1) { 1071 dev_err(i2s_tdm->dev, 1072 "%s path i2s_data[%d]: %d is too high, max is: %d\n", 1073 is_rx_path ? "RX" : "TX", 1074 i, i2s_data[i], CH_GRP_MAX); 1075 return -EINVAL; 1076 } 1077 1078 for (j = 0; j < num; j++) { 1079 if (i == j) 1080 continue; 1081 1082 if (i2s_data[i] == i2s_data[j]) { 1083 dev_err(i2s_tdm->dev, 1084 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n", 1085 is_rx_path ? "RX" : "TX", 1086 i, i2s_data[i], 1087 j, i2s_data[j]); 1088 return -EINVAL; 1089 } 1090 } 1091 } 1092 1093 return 0; 1094 } 1095 1096 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1097 int num) 1098 { 1099 int idx; 1100 1101 for (idx = 0; idx < num; idx++) { 1102 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 1103 I2S_TXCR_PATH_MASK(idx), 1104 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx])); 1105 } 1106 } 1107 1108 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1109 int num) 1110 { 1111 int idx; 1112 1113 for (idx = 0; idx < num; idx++) { 1114 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 1115 I2S_RXCR_PATH_MASK(idx), 1116 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx])); 1117 } 1118 } 1119 1120 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1121 int num, bool is_rx_path) 1122 { 1123 if (is_rx_path) 1124 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num); 1125 else 1126 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num); 1127 } 1128 1129 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1130 struct device_node *np, 1131 bool is_rx_path) 1132 { 1133 char *i2s_tx_path_prop = "rockchip,i2s-tx-route"; 1134 char *i2s_rx_path_prop = "rockchip,i2s-rx-route"; 1135 char *i2s_path_prop; 1136 unsigned int *i2s_data; 1137 int num, ret = 0; 1138 1139 if (is_rx_path) { 1140 i2s_path_prop = i2s_rx_path_prop; 1141 i2s_data = i2s_tdm->i2s_sdis; 1142 } else { 1143 i2s_path_prop = i2s_tx_path_prop; 1144 i2s_data = i2s_tdm->i2s_sdos; 1145 } 1146 1147 num = of_count_phandle_with_args(np, i2s_path_prop, NULL); 1148 if (num < 0) { 1149 if (num != -ENOENT) { 1150 dev_err(i2s_tdm->dev, 1151 "Failed to read '%s' num: %d\n", 1152 i2s_path_prop, num); 1153 ret = num; 1154 } 1155 return ret; 1156 } else if (num != CH_GRP_MAX) { 1157 dev_err(i2s_tdm->dev, 1158 "The num: %d should be: %d\n", num, CH_GRP_MAX); 1159 return -EINVAL; 1160 } 1161 1162 ret = of_property_read_u32_array(np, i2s_path_prop, 1163 i2s_data, num); 1164 if (ret < 0) { 1165 dev_err(i2s_tdm->dev, 1166 "Failed to read '%s': %d\n", 1167 i2s_path_prop, ret); 1168 return ret; 1169 } 1170 1171 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path); 1172 if (ret < 0) { 1173 dev_err(i2s_tdm->dev, 1174 "Failed to check i2s data bus: %d\n", ret); 1175 return ret; 1176 } 1177 1178 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path); 1179 1180 return 0; 1181 } 1182 1183 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1184 struct device_node *np) 1185 { 1186 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0); 1187 } 1188 1189 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1190 struct device_node *np) 1191 { 1192 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1); 1193 } 1194 1195 static int rockchip_i2s_tdm_probe(struct platform_device *pdev) 1196 { 1197 struct device_node *node = pdev->dev.of_node; 1198 struct rk_i2s_tdm_dev *i2s_tdm; 1199 struct resource *res; 1200 void __iomem *regs; 1201 int ret; 1202 1203 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL); 1204 if (!i2s_tdm) 1205 return -ENOMEM; 1206 1207 i2s_tdm->dev = &pdev->dev; 1208 1209 spin_lock_init(&i2s_tdm->lock); 1210 i2s_tdm->soc_data = device_get_match_data(&pdev->dev); 1211 i2s_tdm->frame_width = 64; 1212 1213 i2s_tdm->clk_trcm = TRCM_TXRX; 1214 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only")) 1215 i2s_tdm->clk_trcm = TRCM_TX; 1216 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) { 1217 if (i2s_tdm->clk_trcm) { 1218 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n"); 1219 return -EINVAL; 1220 } 1221 i2s_tdm->clk_trcm = TRCM_RX; 1222 } 1223 1224 ret = rockchip_i2s_tdm_init_dai(i2s_tdm); 1225 if (ret) 1226 return ret; 1227 1228 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 1229 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1230 "tx-m"); 1231 if (IS_ERR(i2s_tdm->tx_reset)) { 1232 ret = PTR_ERR(i2s_tdm->tx_reset); 1233 return dev_err_probe(i2s_tdm->dev, ret, 1234 "Error in tx-m reset control\n"); 1235 } 1236 1237 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1238 "rx-m"); 1239 if (IS_ERR(i2s_tdm->rx_reset)) { 1240 ret = PTR_ERR(i2s_tdm->rx_reset); 1241 return dev_err_probe(i2s_tdm->dev, ret, 1242 "Error in rx-m reset control\n"); 1243 } 1244 1245 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk"); 1246 if (IS_ERR(i2s_tdm->hclk)) { 1247 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk), 1248 "Failed to get clock hclk\n"); 1249 } 1250 1251 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); 1252 if (IS_ERR(i2s_tdm->mclk_tx)) { 1253 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx), 1254 "Failed to get clock mclk_tx\n"); 1255 } 1256 1257 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); 1258 if (IS_ERR(i2s_tdm->mclk_rx)) { 1259 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx), 1260 "Failed to get clock mclk_rx\n"); 1261 } 1262 1263 i2s_tdm->io_multiplex = 1264 of_property_read_bool(node, "rockchip,io-multiplex"); 1265 1266 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1267 if (IS_ERR(regs)) { 1268 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs), 1269 "Failed to get resource IORESOURCE_MEM\n"); 1270 } 1271 1272 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1273 &rockchip_i2s_tdm_regmap_config); 1274 if (IS_ERR(i2s_tdm->regmap)) { 1275 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap), 1276 "Failed to initialise regmap\n"); 1277 } 1278 1279 if (i2s_tdm->has_playback) { 1280 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR; 1281 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1282 i2s_tdm->playback_dma_data.maxburst = 8; 1283 } 1284 1285 if (i2s_tdm->has_capture) { 1286 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR; 1287 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1288 i2s_tdm->capture_dma_data.maxburst = 8; 1289 } 1290 1291 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node); 1292 if (ret < 0) { 1293 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret); 1294 return ret; 1295 } 1296 1297 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node); 1298 if (ret < 0) { 1299 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret); 1300 return ret; 1301 } 1302 1303 dev_set_drvdata(&pdev->dev, i2s_tdm); 1304 1305 ret = clk_prepare_enable(i2s_tdm->hclk); 1306 if (ret) { 1307 return dev_err_probe(i2s_tdm->dev, ret, 1308 "Failed to enable clock hclk\n"); 1309 } 1310 1311 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 1312 if (ret) { 1313 ret = dev_err_probe(i2s_tdm->dev, ret, 1314 "Failed to enable one or more mclks\n"); 1315 goto err_disable_hclk; 1316 } 1317 1318 pm_runtime_enable(&pdev->dev); 1319 1320 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 1321 I2S_DMACR_TDL(16)); 1322 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 1323 I2S_DMACR_RDL(16)); 1324 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK, 1325 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT); 1326 1327 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init) 1328 i2s_tdm->soc_data->init(&pdev->dev, res->start); 1329 1330 ret = devm_snd_soc_register_component(&pdev->dev, 1331 &rockchip_i2s_tdm_component, 1332 i2s_tdm->dai, 1); 1333 1334 if (ret) { 1335 dev_err(&pdev->dev, "Could not register DAI\n"); 1336 goto err_suspend; 1337 } 1338 1339 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1340 if (ret) { 1341 dev_err(&pdev->dev, "Could not register PCM\n"); 1342 goto err_suspend; 1343 } 1344 1345 return 0; 1346 1347 err_suspend: 1348 if (!pm_runtime_status_suspended(&pdev->dev)) 1349 i2s_tdm_runtime_suspend(&pdev->dev); 1350 pm_runtime_disable(&pdev->dev); 1351 1352 err_disable_hclk: 1353 clk_disable_unprepare(i2s_tdm->hclk); 1354 1355 return ret; 1356 } 1357 1358 static void rockchip_i2s_tdm_remove(struct platform_device *pdev) 1359 { 1360 if (!pm_runtime_status_suspended(&pdev->dev)) 1361 i2s_tdm_runtime_suspend(&pdev->dev); 1362 1363 pm_runtime_disable(&pdev->dev); 1364 } 1365 1366 static int __maybe_unused rockchip_i2s_tdm_suspend(struct device *dev) 1367 { 1368 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1369 1370 regcache_mark_dirty(i2s_tdm->regmap); 1371 1372 return 0; 1373 } 1374 1375 static int __maybe_unused rockchip_i2s_tdm_resume(struct device *dev) 1376 { 1377 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1378 int ret; 1379 1380 ret = pm_runtime_resume_and_get(dev); 1381 if (ret < 0) 1382 return ret; 1383 ret = regcache_sync(i2s_tdm->regmap); 1384 pm_runtime_put(dev); 1385 1386 return ret; 1387 } 1388 1389 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = { 1390 SET_RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume, 1391 NULL) 1392 SET_SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend, 1393 rockchip_i2s_tdm_resume) 1394 }; 1395 1396 static struct platform_driver rockchip_i2s_tdm_driver = { 1397 .probe = rockchip_i2s_tdm_probe, 1398 .remove = rockchip_i2s_tdm_remove, 1399 .driver = { 1400 .name = DRV_NAME, 1401 .of_match_table = rockchip_i2s_tdm_match, 1402 .pm = &rockchip_i2s_tdm_pm_ops, 1403 }, 1404 }; 1405 module_platform_driver(rockchip_i2s_tdm_driver); 1406 1407 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface"); 1408 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1409 MODULE_LICENSE("GPL v2"); 1410 MODULE_ALIAS("platform:" DRV_NAME); 1411 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match); 1412