xref: /linux/sound/soc/rockchip/rockchip_i2s.c (revision e5c86679d5e864947a52fb31e45a425dea3e7fa9)
1 /* sound/soc/rockchip/rockchip_i2s.c
2  *
3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
4  *
5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6  * Author: Jianqun <jay.xu@rock-chips.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/delay.h>
16 #include <linux/of_gpio.h>
17 #include <linux/of_device.h>
18 #include <linux/clk.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/regmap.h>
21 #include <sound/pcm_params.h>
22 #include <sound/dmaengine_pcm.h>
23 
24 #include "rockchip_i2s.h"
25 
26 #define DRV_NAME "rockchip-i2s"
27 
28 struct rk_i2s_pins {
29 	u32 reg_offset;
30 	u32 shift;
31 };
32 
33 struct rk_i2s_dev {
34 	struct device *dev;
35 
36 	struct clk *hclk;
37 	struct clk *mclk;
38 
39 	struct snd_dmaengine_dai_dma_data capture_dma_data;
40 	struct snd_dmaengine_dai_dma_data playback_dma_data;
41 
42 	struct regmap *regmap;
43 	struct regmap *grf;
44 
45 /*
46  * Used to indicate the tx/rx status.
47  * I2S controller hopes to start the tx and rx together,
48  * also to stop them when they are both try to stop.
49 */
50 	bool tx_start;
51 	bool rx_start;
52 	bool is_master_mode;
53 	const struct rk_i2s_pins *pins;
54 };
55 
56 static int i2s_runtime_suspend(struct device *dev)
57 {
58 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
59 
60 	regcache_cache_only(i2s->regmap, true);
61 	clk_disable_unprepare(i2s->mclk);
62 
63 	return 0;
64 }
65 
66 static int i2s_runtime_resume(struct device *dev)
67 {
68 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
69 	int ret;
70 
71 	ret = clk_prepare_enable(i2s->mclk);
72 	if (ret) {
73 		dev_err(i2s->dev, "clock enable failed %d\n", ret);
74 		return ret;
75 	}
76 
77 	regcache_cache_only(i2s->regmap, false);
78 	regcache_mark_dirty(i2s->regmap);
79 
80 	ret = regcache_sync(i2s->regmap);
81 	if (ret)
82 		clk_disable_unprepare(i2s->mclk);
83 
84 	return ret;
85 }
86 
87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
88 {
89 	return snd_soc_dai_get_drvdata(dai);
90 }
91 
92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
93 {
94 	unsigned int val = 0;
95 	int retry = 10;
96 
97 	if (on) {
98 		regmap_update_bits(i2s->regmap, I2S_DMACR,
99 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
100 
101 		regmap_update_bits(i2s->regmap, I2S_XFER,
102 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
103 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
104 
105 		i2s->tx_start = true;
106 	} else {
107 		i2s->tx_start = false;
108 
109 		regmap_update_bits(i2s->regmap, I2S_DMACR,
110 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
111 
112 		if (!i2s->rx_start) {
113 			regmap_update_bits(i2s->regmap, I2S_XFER,
114 					   I2S_XFER_TXS_START |
115 					   I2S_XFER_RXS_START,
116 					   I2S_XFER_TXS_STOP |
117 					   I2S_XFER_RXS_STOP);
118 
119 			regmap_update_bits(i2s->regmap, I2S_CLR,
120 					   I2S_CLR_TXC | I2S_CLR_RXC,
121 					   I2S_CLR_TXC | I2S_CLR_RXC);
122 
123 			regmap_read(i2s->regmap, I2S_CLR, &val);
124 
125 			/* Should wait for clear operation to finish */
126 			while (val) {
127 				regmap_read(i2s->regmap, I2S_CLR, &val);
128 				retry--;
129 				if (!retry) {
130 					dev_warn(i2s->dev, "fail to clear\n");
131 					break;
132 				}
133 			}
134 		}
135 	}
136 }
137 
138 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
139 {
140 	unsigned int val = 0;
141 	int retry = 10;
142 
143 	if (on) {
144 		regmap_update_bits(i2s->regmap, I2S_DMACR,
145 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
146 
147 		regmap_update_bits(i2s->regmap, I2S_XFER,
148 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
149 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
150 
151 		i2s->rx_start = true;
152 	} else {
153 		i2s->rx_start = false;
154 
155 		regmap_update_bits(i2s->regmap, I2S_DMACR,
156 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
157 
158 		if (!i2s->tx_start) {
159 			regmap_update_bits(i2s->regmap, I2S_XFER,
160 					   I2S_XFER_TXS_START |
161 					   I2S_XFER_RXS_START,
162 					   I2S_XFER_TXS_STOP |
163 					   I2S_XFER_RXS_STOP);
164 
165 			regmap_update_bits(i2s->regmap, I2S_CLR,
166 					   I2S_CLR_TXC | I2S_CLR_RXC,
167 					   I2S_CLR_TXC | I2S_CLR_RXC);
168 
169 			regmap_read(i2s->regmap, I2S_CLR, &val);
170 
171 			/* Should wait for clear operation to finish */
172 			while (val) {
173 				regmap_read(i2s->regmap, I2S_CLR, &val);
174 				retry--;
175 				if (!retry) {
176 					dev_warn(i2s->dev, "fail to clear\n");
177 					break;
178 				}
179 			}
180 		}
181 	}
182 }
183 
184 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
185 				unsigned int fmt)
186 {
187 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
188 	unsigned int mask = 0, val = 0;
189 
190 	mask = I2S_CKR_MSS_MASK;
191 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
192 	case SND_SOC_DAIFMT_CBS_CFS:
193 		/* Set source clock in Master mode */
194 		val = I2S_CKR_MSS_MASTER;
195 		i2s->is_master_mode = true;
196 		break;
197 	case SND_SOC_DAIFMT_CBM_CFM:
198 		val = I2S_CKR_MSS_SLAVE;
199 		i2s->is_master_mode = false;
200 		break;
201 	default:
202 		return -EINVAL;
203 	}
204 
205 	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
206 
207 	mask = I2S_TXCR_IBM_MASK;
208 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
209 	case SND_SOC_DAIFMT_RIGHT_J:
210 		val = I2S_TXCR_IBM_RSJM;
211 		break;
212 	case SND_SOC_DAIFMT_LEFT_J:
213 		val = I2S_TXCR_IBM_LSJM;
214 		break;
215 	case SND_SOC_DAIFMT_I2S:
216 		val = I2S_TXCR_IBM_NORMAL;
217 		break;
218 	default:
219 		return -EINVAL;
220 	}
221 
222 	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
223 
224 	mask = I2S_RXCR_IBM_MASK;
225 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
226 	case SND_SOC_DAIFMT_RIGHT_J:
227 		val = I2S_RXCR_IBM_RSJM;
228 		break;
229 	case SND_SOC_DAIFMT_LEFT_J:
230 		val = I2S_RXCR_IBM_LSJM;
231 		break;
232 	case SND_SOC_DAIFMT_I2S:
233 		val = I2S_RXCR_IBM_NORMAL;
234 		break;
235 	default:
236 		return -EINVAL;
237 	}
238 
239 	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
240 
241 	return 0;
242 }
243 
244 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
245 				  struct snd_pcm_hw_params *params,
246 				  struct snd_soc_dai *dai)
247 {
248 	struct rk_i2s_dev *i2s = to_info(dai);
249 	struct snd_soc_pcm_runtime *rtd = substream->private_data;
250 	unsigned int val = 0;
251 	unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck;
252 
253 	if (i2s->is_master_mode) {
254 		mclk_rate = clk_get_rate(i2s->mclk);
255 		bclk_rate = 2 * 32 * params_rate(params);
256 		if (bclk_rate && mclk_rate % bclk_rate)
257 			return -EINVAL;
258 
259 		div_bclk = mclk_rate / bclk_rate;
260 		div_lrck = bclk_rate / params_rate(params);
261 		regmap_update_bits(i2s->regmap, I2S_CKR,
262 				   I2S_CKR_MDIV_MASK,
263 				   I2S_CKR_MDIV(div_bclk));
264 
265 		regmap_update_bits(i2s->regmap, I2S_CKR,
266 				   I2S_CKR_TSD_MASK |
267 				   I2S_CKR_RSD_MASK,
268 				   I2S_CKR_TSD(div_lrck) |
269 				   I2S_CKR_RSD(div_lrck));
270 	}
271 
272 	switch (params_format(params)) {
273 	case SNDRV_PCM_FORMAT_S8:
274 		val |= I2S_TXCR_VDW(8);
275 		break;
276 	case SNDRV_PCM_FORMAT_S16_LE:
277 		val |= I2S_TXCR_VDW(16);
278 		break;
279 	case SNDRV_PCM_FORMAT_S20_3LE:
280 		val |= I2S_TXCR_VDW(20);
281 		break;
282 	case SNDRV_PCM_FORMAT_S24_LE:
283 		val |= I2S_TXCR_VDW(24);
284 		break;
285 	case SNDRV_PCM_FORMAT_S32_LE:
286 		val |= I2S_TXCR_VDW(32);
287 		break;
288 	default:
289 		return -EINVAL;
290 	}
291 
292 	switch (params_channels(params)) {
293 	case 8:
294 		val |= I2S_CHN_8;
295 		break;
296 	case 6:
297 		val |= I2S_CHN_6;
298 		break;
299 	case 4:
300 		val |= I2S_CHN_4;
301 		break;
302 	case 2:
303 		val |= I2S_CHN_2;
304 		break;
305 	default:
306 		dev_err(i2s->dev, "invalid channel: %d\n",
307 			params_channels(params));
308 		return -EINVAL;
309 	}
310 
311 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
312 		regmap_update_bits(i2s->regmap, I2S_RXCR,
313 				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
314 				   val);
315 	else
316 		regmap_update_bits(i2s->regmap, I2S_TXCR,
317 				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
318 				   val);
319 
320 	if (!IS_ERR(i2s->grf) && i2s->pins) {
321 		regmap_read(i2s->regmap, I2S_TXCR, &val);
322 		val &= I2S_TXCR_CSR_MASK;
323 
324 		switch (val) {
325 		case I2S_CHN_4:
326 			val = I2S_IO_4CH_OUT_6CH_IN;
327 			break;
328 		case I2S_CHN_6:
329 			val = I2S_IO_6CH_OUT_4CH_IN;
330 			break;
331 		case I2S_CHN_8:
332 			val = I2S_IO_8CH_OUT_2CH_IN;
333 			break;
334 		default:
335 			val = I2S_IO_2CH_OUT_8CH_IN;
336 			break;
337 		}
338 
339 		val <<= i2s->pins->shift;
340 		val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16;
341 		regmap_write(i2s->grf, i2s->pins->reg_offset, val);
342 	}
343 
344 	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
345 			   I2S_DMACR_TDL(16));
346 	regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
347 			   I2S_DMACR_RDL(16));
348 
349 	val = I2S_CKR_TRCM_TXRX;
350 	if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates)
351 		val = I2S_CKR_TRCM_TXONLY;
352 
353 	regmap_update_bits(i2s->regmap, I2S_CKR,
354 			   I2S_CKR_TRCM_MASK,
355 			   val);
356 	return 0;
357 }
358 
359 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
360 				int cmd, struct snd_soc_dai *dai)
361 {
362 	struct rk_i2s_dev *i2s = to_info(dai);
363 	int ret = 0;
364 
365 	switch (cmd) {
366 	case SNDRV_PCM_TRIGGER_START:
367 	case SNDRV_PCM_TRIGGER_RESUME:
368 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
369 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
370 			rockchip_snd_rxctrl(i2s, 1);
371 		else
372 			rockchip_snd_txctrl(i2s, 1);
373 		break;
374 	case SNDRV_PCM_TRIGGER_SUSPEND:
375 	case SNDRV_PCM_TRIGGER_STOP:
376 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
377 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
378 			rockchip_snd_rxctrl(i2s, 0);
379 		else
380 			rockchip_snd_txctrl(i2s, 0);
381 		break;
382 	default:
383 		ret = -EINVAL;
384 		break;
385 	}
386 
387 	return ret;
388 }
389 
390 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
391 				   unsigned int freq, int dir)
392 {
393 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
394 	int ret;
395 
396 	ret = clk_set_rate(i2s->mclk, freq);
397 	if (ret)
398 		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
399 
400 	return ret;
401 }
402 
403 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
404 {
405 	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
406 
407 	dai->capture_dma_data = &i2s->capture_dma_data;
408 	dai->playback_dma_data = &i2s->playback_dma_data;
409 
410 	return 0;
411 }
412 
413 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
414 	.hw_params = rockchip_i2s_hw_params,
415 	.set_sysclk = rockchip_i2s_set_sysclk,
416 	.set_fmt = rockchip_i2s_set_fmt,
417 	.trigger = rockchip_i2s_trigger,
418 };
419 
420 static struct snd_soc_dai_driver rockchip_i2s_dai = {
421 	.probe = rockchip_i2s_dai_probe,
422 	.playback = {
423 		.stream_name = "Playback",
424 		.channels_min = 2,
425 		.channels_max = 8,
426 		.rates = SNDRV_PCM_RATE_8000_192000,
427 		.formats = (SNDRV_PCM_FMTBIT_S8 |
428 			    SNDRV_PCM_FMTBIT_S16_LE |
429 			    SNDRV_PCM_FMTBIT_S20_3LE |
430 			    SNDRV_PCM_FMTBIT_S24_LE |
431 			    SNDRV_PCM_FMTBIT_S32_LE),
432 	},
433 	.capture = {
434 		.stream_name = "Capture",
435 		.channels_min = 2,
436 		.channels_max = 2,
437 		.rates = SNDRV_PCM_RATE_8000_192000,
438 		.formats = (SNDRV_PCM_FMTBIT_S8 |
439 			    SNDRV_PCM_FMTBIT_S16_LE |
440 			    SNDRV_PCM_FMTBIT_S20_3LE |
441 			    SNDRV_PCM_FMTBIT_S24_LE |
442 			    SNDRV_PCM_FMTBIT_S32_LE),
443 	},
444 	.ops = &rockchip_i2s_dai_ops,
445 	.symmetric_rates = 1,
446 };
447 
448 static const struct snd_soc_component_driver rockchip_i2s_component = {
449 	.name = DRV_NAME,
450 };
451 
452 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
453 {
454 	switch (reg) {
455 	case I2S_TXCR:
456 	case I2S_RXCR:
457 	case I2S_CKR:
458 	case I2S_DMACR:
459 	case I2S_INTCR:
460 	case I2S_XFER:
461 	case I2S_CLR:
462 	case I2S_TXDR:
463 		return true;
464 	default:
465 		return false;
466 	}
467 }
468 
469 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
470 {
471 	switch (reg) {
472 	case I2S_TXCR:
473 	case I2S_RXCR:
474 	case I2S_CKR:
475 	case I2S_DMACR:
476 	case I2S_INTCR:
477 	case I2S_XFER:
478 	case I2S_CLR:
479 	case I2S_RXDR:
480 	case I2S_FIFOLR:
481 	case I2S_INTSR:
482 		return true;
483 	default:
484 		return false;
485 	}
486 }
487 
488 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
489 {
490 	switch (reg) {
491 	case I2S_INTSR:
492 	case I2S_CLR:
493 		return true;
494 	default:
495 		return false;
496 	}
497 }
498 
499 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
500 {
501 	switch (reg) {
502 	default:
503 		return false;
504 	}
505 }
506 
507 static const struct reg_default rockchip_i2s_reg_defaults[] = {
508 	{0x00, 0x0000000f},
509 	{0x04, 0x0000000f},
510 	{0x08, 0x00071f1f},
511 	{0x10, 0x001f0000},
512 	{0x14, 0x01f00000},
513 };
514 
515 static const struct regmap_config rockchip_i2s_regmap_config = {
516 	.reg_bits = 32,
517 	.reg_stride = 4,
518 	.val_bits = 32,
519 	.max_register = I2S_RXDR,
520 	.reg_defaults = rockchip_i2s_reg_defaults,
521 	.num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults),
522 	.writeable_reg = rockchip_i2s_wr_reg,
523 	.readable_reg = rockchip_i2s_rd_reg,
524 	.volatile_reg = rockchip_i2s_volatile_reg,
525 	.precious_reg = rockchip_i2s_precious_reg,
526 	.cache_type = REGCACHE_FLAT,
527 };
528 
529 static const struct rk_i2s_pins rk3399_i2s_pins = {
530 	.reg_offset = 0xe220,
531 	.shift = 11,
532 };
533 
534 static const struct of_device_id rockchip_i2s_match[] = {
535 	{ .compatible = "rockchip,rk3066-i2s", },
536 	{ .compatible = "rockchip,rk3188-i2s", },
537 	{ .compatible = "rockchip,rk3288-i2s", },
538 	{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
539 	{},
540 };
541 
542 static int rockchip_i2s_probe(struct platform_device *pdev)
543 {
544 	struct device_node *node = pdev->dev.of_node;
545 	const struct of_device_id *of_id;
546 	struct rk_i2s_dev *i2s;
547 	struct snd_soc_dai_driver *soc_dai;
548 	struct resource *res;
549 	void __iomem *regs;
550 	int ret;
551 	int val;
552 
553 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
554 	if (!i2s) {
555 		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
556 		return -ENOMEM;
557 	}
558 
559 	i2s->dev = &pdev->dev;
560 
561 	i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
562 	if (!IS_ERR(i2s->grf)) {
563 		of_id = of_match_device(rockchip_i2s_match, &pdev->dev);
564 		if (!of_id || !of_id->data)
565 			return -EINVAL;
566 
567 		i2s->pins = of_id->data;
568 	}
569 
570 	/* try to prepare related clocks */
571 	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
572 	if (IS_ERR(i2s->hclk)) {
573 		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
574 		return PTR_ERR(i2s->hclk);
575 	}
576 	ret = clk_prepare_enable(i2s->hclk);
577 	if (ret) {
578 		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
579 		return ret;
580 	}
581 
582 	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
583 	if (IS_ERR(i2s->mclk)) {
584 		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
585 		return PTR_ERR(i2s->mclk);
586 	}
587 
588 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
589 	regs = devm_ioremap_resource(&pdev->dev, res);
590 	if (IS_ERR(regs))
591 		return PTR_ERR(regs);
592 
593 	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
594 					    &rockchip_i2s_regmap_config);
595 	if (IS_ERR(i2s->regmap)) {
596 		dev_err(&pdev->dev,
597 			"Failed to initialise managed register map\n");
598 		return PTR_ERR(i2s->regmap);
599 	}
600 
601 	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
602 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
603 	i2s->playback_dma_data.maxburst = 4;
604 
605 	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
606 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
607 	i2s->capture_dma_data.maxburst = 4;
608 
609 	dev_set_drvdata(&pdev->dev, i2s);
610 
611 	pm_runtime_enable(&pdev->dev);
612 	if (!pm_runtime_enabled(&pdev->dev)) {
613 		ret = i2s_runtime_resume(&pdev->dev);
614 		if (ret)
615 			goto err_pm_disable;
616 	}
617 
618 	soc_dai = devm_kzalloc(&pdev->dev,
619 			       sizeof(*soc_dai), GFP_KERNEL);
620 	if (!soc_dai)
621 		return -ENOMEM;
622 
623 	memcpy(soc_dai, &rockchip_i2s_dai, sizeof(*soc_dai));
624 	if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) {
625 		if (val >= 2 && val <= 8)
626 			soc_dai->playback.channels_max = val;
627 	}
628 
629 	if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) {
630 		if (val >= 2 && val <= 8)
631 			soc_dai->capture.channels_max = val;
632 	}
633 
634 	ret = devm_snd_soc_register_component(&pdev->dev,
635 					      &rockchip_i2s_component,
636 					      soc_dai, 1);
637 
638 	if (ret) {
639 		dev_err(&pdev->dev, "Could not register DAI\n");
640 		goto err_suspend;
641 	}
642 
643 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
644 	if (ret) {
645 		dev_err(&pdev->dev, "Could not register PCM\n");
646 		return ret;
647 	}
648 
649 	return 0;
650 
651 err_suspend:
652 	if (!pm_runtime_status_suspended(&pdev->dev))
653 		i2s_runtime_suspend(&pdev->dev);
654 err_pm_disable:
655 	pm_runtime_disable(&pdev->dev);
656 
657 	return ret;
658 }
659 
660 static int rockchip_i2s_remove(struct platform_device *pdev)
661 {
662 	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
663 
664 	pm_runtime_disable(&pdev->dev);
665 	if (!pm_runtime_status_suspended(&pdev->dev))
666 		i2s_runtime_suspend(&pdev->dev);
667 
668 	clk_disable_unprepare(i2s->mclk);
669 	clk_disable_unprepare(i2s->hclk);
670 
671 	return 0;
672 }
673 
674 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
675 	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
676 			   NULL)
677 };
678 
679 static struct platform_driver rockchip_i2s_driver = {
680 	.probe = rockchip_i2s_probe,
681 	.remove = rockchip_i2s_remove,
682 	.driver = {
683 		.name = DRV_NAME,
684 		.of_match_table = of_match_ptr(rockchip_i2s_match),
685 		.pm = &rockchip_i2s_pm_ops,
686 	},
687 };
688 module_platform_driver(rockchip_i2s_driver);
689 
690 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
691 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
692 MODULE_LICENSE("GPL v2");
693 MODULE_ALIAS("platform:" DRV_NAME);
694 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
695