1 /* sound/soc/rockchip/rockchip_i2s.c 2 * 3 * ALSA SoC Audio Layer - Rockchip I2S Controller driver 4 * 5 * Copyright (c) 2014 Rockchip Electronics Co. Ltd. 6 * Author: Jianqun <jay.xu@rock-chips.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/module.h> 14 #include <linux/mfd/syscon.h> 15 #include <linux/delay.h> 16 #include <linux/of_gpio.h> 17 #include <linux/of_device.h> 18 #include <linux/clk.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/regmap.h> 21 #include <sound/pcm_params.h> 22 #include <sound/dmaengine_pcm.h> 23 24 #include "rockchip_i2s.h" 25 26 #define DRV_NAME "rockchip-i2s" 27 28 struct rk_i2s_pins { 29 u32 reg_offset; 30 u32 shift; 31 }; 32 33 struct rk_i2s_dev { 34 struct device *dev; 35 36 struct clk *hclk; 37 struct clk *mclk; 38 39 struct snd_dmaengine_dai_dma_data capture_dma_data; 40 struct snd_dmaengine_dai_dma_data playback_dma_data; 41 42 struct regmap *regmap; 43 struct regmap *grf; 44 45 /* 46 * Used to indicate the tx/rx status. 47 * I2S controller hopes to start the tx and rx together, 48 * also to stop them when they are both try to stop. 49 */ 50 bool tx_start; 51 bool rx_start; 52 bool is_master_mode; 53 const struct rk_i2s_pins *pins; 54 }; 55 56 static int i2s_runtime_suspend(struct device *dev) 57 { 58 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 59 60 regcache_cache_only(i2s->regmap, true); 61 clk_disable_unprepare(i2s->mclk); 62 63 return 0; 64 } 65 66 static int i2s_runtime_resume(struct device *dev) 67 { 68 struct rk_i2s_dev *i2s = dev_get_drvdata(dev); 69 int ret; 70 71 ret = clk_prepare_enable(i2s->mclk); 72 if (ret) { 73 dev_err(i2s->dev, "clock enable failed %d\n", ret); 74 return ret; 75 } 76 77 regcache_cache_only(i2s->regmap, false); 78 regcache_mark_dirty(i2s->regmap); 79 80 ret = regcache_sync(i2s->regmap); 81 if (ret) 82 clk_disable_unprepare(i2s->mclk); 83 84 return ret; 85 } 86 87 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai) 88 { 89 return snd_soc_dai_get_drvdata(dai); 90 } 91 92 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on) 93 { 94 unsigned int val = 0; 95 int retry = 10; 96 97 if (on) { 98 regmap_update_bits(i2s->regmap, I2S_DMACR, 99 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE); 100 101 regmap_update_bits(i2s->regmap, I2S_XFER, 102 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 103 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 104 105 i2s->tx_start = true; 106 } else { 107 i2s->tx_start = false; 108 109 regmap_update_bits(i2s->regmap, I2S_DMACR, 110 I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE); 111 112 if (!i2s->rx_start) { 113 regmap_update_bits(i2s->regmap, I2S_XFER, 114 I2S_XFER_TXS_START | 115 I2S_XFER_RXS_START, 116 I2S_XFER_TXS_STOP | 117 I2S_XFER_RXS_STOP); 118 119 udelay(150); 120 regmap_update_bits(i2s->regmap, I2S_CLR, 121 I2S_CLR_TXC | I2S_CLR_RXC, 122 I2S_CLR_TXC | I2S_CLR_RXC); 123 124 regmap_read(i2s->regmap, I2S_CLR, &val); 125 126 /* Should wait for clear operation to finish */ 127 while (val) { 128 regmap_read(i2s->regmap, I2S_CLR, &val); 129 retry--; 130 if (!retry) { 131 dev_warn(i2s->dev, "fail to clear\n"); 132 break; 133 } 134 } 135 } 136 } 137 } 138 139 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on) 140 { 141 unsigned int val = 0; 142 int retry = 10; 143 144 if (on) { 145 regmap_update_bits(i2s->regmap, I2S_DMACR, 146 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE); 147 148 regmap_update_bits(i2s->regmap, I2S_XFER, 149 I2S_XFER_TXS_START | I2S_XFER_RXS_START, 150 I2S_XFER_TXS_START | I2S_XFER_RXS_START); 151 152 i2s->rx_start = true; 153 } else { 154 i2s->rx_start = false; 155 156 regmap_update_bits(i2s->regmap, I2S_DMACR, 157 I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE); 158 159 if (!i2s->tx_start) { 160 regmap_update_bits(i2s->regmap, I2S_XFER, 161 I2S_XFER_TXS_START | 162 I2S_XFER_RXS_START, 163 I2S_XFER_TXS_STOP | 164 I2S_XFER_RXS_STOP); 165 166 udelay(150); 167 regmap_update_bits(i2s->regmap, I2S_CLR, 168 I2S_CLR_TXC | I2S_CLR_RXC, 169 I2S_CLR_TXC | I2S_CLR_RXC); 170 171 regmap_read(i2s->regmap, I2S_CLR, &val); 172 173 /* Should wait for clear operation to finish */ 174 while (val) { 175 regmap_read(i2s->regmap, I2S_CLR, &val); 176 retry--; 177 if (!retry) { 178 dev_warn(i2s->dev, "fail to clear\n"); 179 break; 180 } 181 } 182 } 183 } 184 } 185 186 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai, 187 unsigned int fmt) 188 { 189 struct rk_i2s_dev *i2s = to_info(cpu_dai); 190 unsigned int mask = 0, val = 0; 191 192 mask = I2S_CKR_MSS_MASK; 193 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 194 case SND_SOC_DAIFMT_CBS_CFS: 195 /* Set source clock in Master mode */ 196 val = I2S_CKR_MSS_MASTER; 197 i2s->is_master_mode = true; 198 break; 199 case SND_SOC_DAIFMT_CBM_CFM: 200 val = I2S_CKR_MSS_SLAVE; 201 i2s->is_master_mode = false; 202 break; 203 default: 204 return -EINVAL; 205 } 206 207 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 208 209 mask = I2S_CKR_CKP_MASK; 210 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 211 case SND_SOC_DAIFMT_NB_NF: 212 val = I2S_CKR_CKP_NEG; 213 break; 214 case SND_SOC_DAIFMT_IB_NF: 215 val = I2S_CKR_CKP_POS; 216 break; 217 default: 218 return -EINVAL; 219 } 220 221 regmap_update_bits(i2s->regmap, I2S_CKR, mask, val); 222 223 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 224 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 225 case SND_SOC_DAIFMT_RIGHT_J: 226 val = I2S_TXCR_IBM_RSJM; 227 break; 228 case SND_SOC_DAIFMT_LEFT_J: 229 val = I2S_TXCR_IBM_LSJM; 230 break; 231 case SND_SOC_DAIFMT_I2S: 232 val = I2S_TXCR_IBM_NORMAL; 233 break; 234 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ 235 val = I2S_TXCR_TFS_PCM; 236 break; 237 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ 238 val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 239 break; 240 default: 241 return -EINVAL; 242 } 243 244 regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val); 245 246 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 247 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 248 case SND_SOC_DAIFMT_RIGHT_J: 249 val = I2S_RXCR_IBM_RSJM; 250 break; 251 case SND_SOC_DAIFMT_LEFT_J: 252 val = I2S_RXCR_IBM_LSJM; 253 break; 254 case SND_SOC_DAIFMT_I2S: 255 val = I2S_RXCR_IBM_NORMAL; 256 break; 257 case SND_SOC_DAIFMT_DSP_A: /* PCM no delay mode */ 258 val = I2S_RXCR_TFS_PCM; 259 break; 260 case SND_SOC_DAIFMT_DSP_B: /* PCM delay 1 mode */ 261 val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 262 break; 263 default: 264 return -EINVAL; 265 } 266 267 regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val); 268 269 return 0; 270 } 271 272 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream, 273 struct snd_pcm_hw_params *params, 274 struct snd_soc_dai *dai) 275 { 276 struct rk_i2s_dev *i2s = to_info(dai); 277 struct snd_soc_pcm_runtime *rtd = substream->private_data; 278 unsigned int val = 0; 279 unsigned int mclk_rate, bclk_rate, div_bclk, div_lrck; 280 281 if (i2s->is_master_mode) { 282 mclk_rate = clk_get_rate(i2s->mclk); 283 bclk_rate = 2 * 32 * params_rate(params); 284 if (bclk_rate && mclk_rate % bclk_rate) 285 return -EINVAL; 286 287 div_bclk = mclk_rate / bclk_rate; 288 div_lrck = bclk_rate / params_rate(params); 289 regmap_update_bits(i2s->regmap, I2S_CKR, 290 I2S_CKR_MDIV_MASK, 291 I2S_CKR_MDIV(div_bclk)); 292 293 regmap_update_bits(i2s->regmap, I2S_CKR, 294 I2S_CKR_TSD_MASK | 295 I2S_CKR_RSD_MASK, 296 I2S_CKR_TSD(div_lrck) | 297 I2S_CKR_RSD(div_lrck)); 298 } 299 300 switch (params_format(params)) { 301 case SNDRV_PCM_FORMAT_S8: 302 val |= I2S_TXCR_VDW(8); 303 break; 304 case SNDRV_PCM_FORMAT_S16_LE: 305 val |= I2S_TXCR_VDW(16); 306 break; 307 case SNDRV_PCM_FORMAT_S20_3LE: 308 val |= I2S_TXCR_VDW(20); 309 break; 310 case SNDRV_PCM_FORMAT_S24_LE: 311 val |= I2S_TXCR_VDW(24); 312 break; 313 case SNDRV_PCM_FORMAT_S32_LE: 314 val |= I2S_TXCR_VDW(32); 315 break; 316 default: 317 return -EINVAL; 318 } 319 320 switch (params_channels(params)) { 321 case 8: 322 val |= I2S_CHN_8; 323 break; 324 case 6: 325 val |= I2S_CHN_6; 326 break; 327 case 4: 328 val |= I2S_CHN_4; 329 break; 330 case 2: 331 case 1: 332 val |= I2S_CHN_2; 333 break; 334 default: 335 dev_err(i2s->dev, "invalid channel: %d\n", 336 params_channels(params)); 337 return -EINVAL; 338 } 339 340 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 341 regmap_update_bits(i2s->regmap, I2S_RXCR, 342 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 343 val); 344 else 345 regmap_update_bits(i2s->regmap, I2S_TXCR, 346 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 347 val); 348 349 if (!IS_ERR(i2s->grf) && i2s->pins) { 350 regmap_read(i2s->regmap, I2S_TXCR, &val); 351 val &= I2S_TXCR_CSR_MASK; 352 353 switch (val) { 354 case I2S_CHN_4: 355 val = I2S_IO_4CH_OUT_6CH_IN; 356 break; 357 case I2S_CHN_6: 358 val = I2S_IO_6CH_OUT_4CH_IN; 359 break; 360 case I2S_CHN_8: 361 val = I2S_IO_8CH_OUT_2CH_IN; 362 break; 363 default: 364 val = I2S_IO_2CH_OUT_8CH_IN; 365 break; 366 } 367 368 val <<= i2s->pins->shift; 369 val |= (I2S_IO_DIRECTION_MASK << i2s->pins->shift) << 16; 370 regmap_write(i2s->grf, i2s->pins->reg_offset, val); 371 } 372 373 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 374 I2S_DMACR_TDL(16)); 375 regmap_update_bits(i2s->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 376 I2S_DMACR_RDL(16)); 377 378 val = I2S_CKR_TRCM_TXRX; 379 if (dai->driver->symmetric_rates && rtd->dai_link->symmetric_rates) 380 val = I2S_CKR_TRCM_TXONLY; 381 382 regmap_update_bits(i2s->regmap, I2S_CKR, 383 I2S_CKR_TRCM_MASK, 384 val); 385 return 0; 386 } 387 388 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream, 389 int cmd, struct snd_soc_dai *dai) 390 { 391 struct rk_i2s_dev *i2s = to_info(dai); 392 int ret = 0; 393 394 switch (cmd) { 395 case SNDRV_PCM_TRIGGER_START: 396 case SNDRV_PCM_TRIGGER_RESUME: 397 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 398 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 399 rockchip_snd_rxctrl(i2s, 1); 400 else 401 rockchip_snd_txctrl(i2s, 1); 402 break; 403 case SNDRV_PCM_TRIGGER_SUSPEND: 404 case SNDRV_PCM_TRIGGER_STOP: 405 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 406 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 407 rockchip_snd_rxctrl(i2s, 0); 408 else 409 rockchip_snd_txctrl(i2s, 0); 410 break; 411 default: 412 ret = -EINVAL; 413 break; 414 } 415 416 return ret; 417 } 418 419 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id, 420 unsigned int freq, int dir) 421 { 422 struct rk_i2s_dev *i2s = to_info(cpu_dai); 423 int ret; 424 425 ret = clk_set_rate(i2s->mclk, freq); 426 if (ret) 427 dev_err(i2s->dev, "Fail to set mclk %d\n", ret); 428 429 return ret; 430 } 431 432 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai) 433 { 434 struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai); 435 436 dai->capture_dma_data = &i2s->capture_dma_data; 437 dai->playback_dma_data = &i2s->playback_dma_data; 438 439 return 0; 440 } 441 442 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = { 443 .hw_params = rockchip_i2s_hw_params, 444 .set_sysclk = rockchip_i2s_set_sysclk, 445 .set_fmt = rockchip_i2s_set_fmt, 446 .trigger = rockchip_i2s_trigger, 447 }; 448 449 static struct snd_soc_dai_driver rockchip_i2s_dai = { 450 .probe = rockchip_i2s_dai_probe, 451 .playback = { 452 .stream_name = "Playback", 453 .channels_min = 2, 454 .channels_max = 8, 455 .rates = SNDRV_PCM_RATE_8000_192000, 456 .formats = (SNDRV_PCM_FMTBIT_S8 | 457 SNDRV_PCM_FMTBIT_S16_LE | 458 SNDRV_PCM_FMTBIT_S20_3LE | 459 SNDRV_PCM_FMTBIT_S24_LE | 460 SNDRV_PCM_FMTBIT_S32_LE), 461 }, 462 .capture = { 463 .stream_name = "Capture", 464 .channels_min = 1, 465 .channels_max = 2, 466 .rates = SNDRV_PCM_RATE_8000_192000, 467 .formats = (SNDRV_PCM_FMTBIT_S8 | 468 SNDRV_PCM_FMTBIT_S16_LE | 469 SNDRV_PCM_FMTBIT_S20_3LE | 470 SNDRV_PCM_FMTBIT_S24_LE | 471 SNDRV_PCM_FMTBIT_S32_LE), 472 }, 473 .ops = &rockchip_i2s_dai_ops, 474 .symmetric_rates = 1, 475 }; 476 477 static const struct snd_soc_component_driver rockchip_i2s_component = { 478 .name = DRV_NAME, 479 }; 480 481 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg) 482 { 483 switch (reg) { 484 case I2S_TXCR: 485 case I2S_RXCR: 486 case I2S_CKR: 487 case I2S_DMACR: 488 case I2S_INTCR: 489 case I2S_XFER: 490 case I2S_CLR: 491 case I2S_TXDR: 492 return true; 493 default: 494 return false; 495 } 496 } 497 498 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg) 499 { 500 switch (reg) { 501 case I2S_TXCR: 502 case I2S_RXCR: 503 case I2S_CKR: 504 case I2S_DMACR: 505 case I2S_INTCR: 506 case I2S_XFER: 507 case I2S_CLR: 508 case I2S_TXDR: 509 case I2S_RXDR: 510 case I2S_FIFOLR: 511 case I2S_INTSR: 512 return true; 513 default: 514 return false; 515 } 516 } 517 518 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg) 519 { 520 switch (reg) { 521 case I2S_INTSR: 522 case I2S_CLR: 523 case I2S_FIFOLR: 524 case I2S_TXDR: 525 case I2S_RXDR: 526 return true; 527 default: 528 return false; 529 } 530 } 531 532 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg) 533 { 534 switch (reg) { 535 case I2S_RXDR: 536 return true; 537 default: 538 return false; 539 } 540 } 541 542 static const struct reg_default rockchip_i2s_reg_defaults[] = { 543 {0x00, 0x0000000f}, 544 {0x04, 0x0000000f}, 545 {0x08, 0x00071f1f}, 546 {0x10, 0x001f0000}, 547 {0x14, 0x01f00000}, 548 }; 549 550 static const struct regmap_config rockchip_i2s_regmap_config = { 551 .reg_bits = 32, 552 .reg_stride = 4, 553 .val_bits = 32, 554 .max_register = I2S_RXDR, 555 .reg_defaults = rockchip_i2s_reg_defaults, 556 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_reg_defaults), 557 .writeable_reg = rockchip_i2s_wr_reg, 558 .readable_reg = rockchip_i2s_rd_reg, 559 .volatile_reg = rockchip_i2s_volatile_reg, 560 .precious_reg = rockchip_i2s_precious_reg, 561 .cache_type = REGCACHE_FLAT, 562 }; 563 564 static const struct rk_i2s_pins rk3399_i2s_pins = { 565 .reg_offset = 0xe220, 566 .shift = 11, 567 }; 568 569 static const struct of_device_id rockchip_i2s_match[] = { 570 { .compatible = "rockchip,rk3066-i2s", }, 571 { .compatible = "rockchip,rk3188-i2s", }, 572 { .compatible = "rockchip,rk3288-i2s", }, 573 { .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins }, 574 {}, 575 }; 576 577 static int rockchip_i2s_probe(struct platform_device *pdev) 578 { 579 struct device_node *node = pdev->dev.of_node; 580 const struct of_device_id *of_id; 581 struct rk_i2s_dev *i2s; 582 struct snd_soc_dai_driver *soc_dai; 583 struct resource *res; 584 void __iomem *regs; 585 int ret; 586 int val; 587 588 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL); 589 if (!i2s) 590 return -ENOMEM; 591 592 i2s->dev = &pdev->dev; 593 594 i2s->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 595 if (!IS_ERR(i2s->grf)) { 596 of_id = of_match_device(rockchip_i2s_match, &pdev->dev); 597 if (!of_id || !of_id->data) 598 return -EINVAL; 599 600 i2s->pins = of_id->data; 601 } 602 603 /* try to prepare related clocks */ 604 i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk"); 605 if (IS_ERR(i2s->hclk)) { 606 dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n"); 607 return PTR_ERR(i2s->hclk); 608 } 609 ret = clk_prepare_enable(i2s->hclk); 610 if (ret) { 611 dev_err(i2s->dev, "hclock enable failed %d\n", ret); 612 return ret; 613 } 614 615 i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk"); 616 if (IS_ERR(i2s->mclk)) { 617 dev_err(&pdev->dev, "Can't retrieve i2s master clock\n"); 618 return PTR_ERR(i2s->mclk); 619 } 620 621 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 622 regs = devm_ioremap_resource(&pdev->dev, res); 623 if (IS_ERR(regs)) 624 return PTR_ERR(regs); 625 626 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 627 &rockchip_i2s_regmap_config); 628 if (IS_ERR(i2s->regmap)) { 629 dev_err(&pdev->dev, 630 "Failed to initialise managed register map\n"); 631 return PTR_ERR(i2s->regmap); 632 } 633 634 i2s->playback_dma_data.addr = res->start + I2S_TXDR; 635 i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 636 i2s->playback_dma_data.maxburst = 4; 637 638 i2s->capture_dma_data.addr = res->start + I2S_RXDR; 639 i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 640 i2s->capture_dma_data.maxburst = 4; 641 642 dev_set_drvdata(&pdev->dev, i2s); 643 644 pm_runtime_enable(&pdev->dev); 645 if (!pm_runtime_enabled(&pdev->dev)) { 646 ret = i2s_runtime_resume(&pdev->dev); 647 if (ret) 648 goto err_pm_disable; 649 } 650 651 soc_dai = devm_kmemdup(&pdev->dev, &rockchip_i2s_dai, 652 sizeof(*soc_dai), GFP_KERNEL); 653 if (!soc_dai) { 654 ret = -ENOMEM; 655 goto err_pm_disable; 656 } 657 658 if (!of_property_read_u32(node, "rockchip,playback-channels", &val)) { 659 if (val >= 2 && val <= 8) 660 soc_dai->playback.channels_max = val; 661 } 662 663 if (!of_property_read_u32(node, "rockchip,capture-channels", &val)) { 664 if (val >= 1 && val <= 8) 665 soc_dai->capture.channels_max = val; 666 } 667 668 ret = devm_snd_soc_register_component(&pdev->dev, 669 &rockchip_i2s_component, 670 soc_dai, 1); 671 672 if (ret) { 673 dev_err(&pdev->dev, "Could not register DAI\n"); 674 goto err_suspend; 675 } 676 677 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 678 if (ret) { 679 dev_err(&pdev->dev, "Could not register PCM\n"); 680 return ret; 681 } 682 683 return 0; 684 685 err_suspend: 686 if (!pm_runtime_status_suspended(&pdev->dev)) 687 i2s_runtime_suspend(&pdev->dev); 688 err_pm_disable: 689 pm_runtime_disable(&pdev->dev); 690 691 return ret; 692 } 693 694 static int rockchip_i2s_remove(struct platform_device *pdev) 695 { 696 struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev); 697 698 pm_runtime_disable(&pdev->dev); 699 if (!pm_runtime_status_suspended(&pdev->dev)) 700 i2s_runtime_suspend(&pdev->dev); 701 702 clk_disable_unprepare(i2s->hclk); 703 704 return 0; 705 } 706 707 static const struct dev_pm_ops rockchip_i2s_pm_ops = { 708 SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume, 709 NULL) 710 }; 711 712 static struct platform_driver rockchip_i2s_driver = { 713 .probe = rockchip_i2s_probe, 714 .remove = rockchip_i2s_remove, 715 .driver = { 716 .name = DRV_NAME, 717 .of_match_table = of_match_ptr(rockchip_i2s_match), 718 .pm = &rockchip_i2s_pm_ops, 719 }, 720 }; 721 module_platform_driver(rockchip_i2s_driver); 722 723 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface"); 724 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>"); 725 MODULE_LICENSE("GPL v2"); 726 MODULE_ALIAS("platform:" DRV_NAME); 727 MODULE_DEVICE_TABLE(of, rockchip_i2s_match); 728