xref: /linux/sound/soc/rockchip/rockchip_i2s.c (revision 04eeb606a8383b306f4bc6991da8231b5f3924b0) 
1 /* sound/soc/rockchip/rockchip_i2s.c
2  *
3  * ALSA SoC Audio Layer - Rockchip I2S Controller driver
4  *
5  * Copyright (c) 2014 Rockchip Electronics Co. Ltd.
6  * Author: Jianqun <jay.xu@rock-chips.com>
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  */
12 
13 #include <linux/module.h>
14 #include <linux/delay.h>
15 #include <linux/of_gpio.h>
16 #include <linux/clk.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/regmap.h>
19 #include <sound/pcm_params.h>
20 #include <sound/dmaengine_pcm.h>
21 
22 #include "rockchip_i2s.h"
23 
24 #define DRV_NAME "rockchip-i2s"
25 
26 struct rk_i2s_dev {
27 	struct device *dev;
28 
29 	struct clk *hclk;
30 	struct clk *mclk;
31 
32 	struct snd_dmaengine_dai_dma_data capture_dma_data;
33 	struct snd_dmaengine_dai_dma_data playback_dma_data;
34 
35 	struct regmap *regmap;
36 
37 /*
38  * Used to indicate the tx/rx status.
39  * I2S controller hopes to start the tx and rx together,
40  * also to stop them when they are both try to stop.
41 */
42 	bool tx_start;
43 	bool rx_start;
44 };
45 
46 static int i2s_runtime_suspend(struct device *dev)
47 {
48 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
49 
50 	clk_disable_unprepare(i2s->mclk);
51 
52 	return 0;
53 }
54 
55 static int i2s_runtime_resume(struct device *dev)
56 {
57 	struct rk_i2s_dev *i2s = dev_get_drvdata(dev);
58 	int ret;
59 
60 	ret = clk_prepare_enable(i2s->mclk);
61 	if (ret) {
62 		dev_err(i2s->dev, "clock enable failed %d\n", ret);
63 		return ret;
64 	}
65 
66 	return 0;
67 }
68 
69 static inline struct rk_i2s_dev *to_info(struct snd_soc_dai *dai)
70 {
71 	return snd_soc_dai_get_drvdata(dai);
72 }
73 
74 static void rockchip_snd_txctrl(struct rk_i2s_dev *i2s, int on)
75 {
76 	unsigned int val = 0;
77 	int retry = 10;
78 
79 	if (on) {
80 		regmap_update_bits(i2s->regmap, I2S_DMACR,
81 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
82 
83 		regmap_update_bits(i2s->regmap, I2S_XFER,
84 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
85 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
86 
87 		i2s->tx_start = true;
88 	} else {
89 		i2s->tx_start = false;
90 
91 		regmap_update_bits(i2s->regmap, I2S_DMACR,
92 				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
93 
94 		if (!i2s->rx_start) {
95 			regmap_update_bits(i2s->regmap, I2S_XFER,
96 					   I2S_XFER_TXS_START |
97 					   I2S_XFER_RXS_START,
98 					   I2S_XFER_TXS_STOP |
99 					   I2S_XFER_RXS_STOP);
100 
101 			regmap_update_bits(i2s->regmap, I2S_CLR,
102 					   I2S_CLR_TXC | I2S_CLR_RXC,
103 					   I2S_CLR_TXC | I2S_CLR_RXC);
104 
105 			regmap_read(i2s->regmap, I2S_CLR, &val);
106 
107 			/* Should wait for clear operation to finish */
108 			while (val) {
109 				regmap_read(i2s->regmap, I2S_CLR, &val);
110 				retry--;
111 				if (!retry) {
112 					dev_warn(i2s->dev, "fail to clear\n");
113 					break;
114 				}
115 			}
116 		}
117 	}
118 }
119 
120 static void rockchip_snd_rxctrl(struct rk_i2s_dev *i2s, int on)
121 {
122 	unsigned int val = 0;
123 	int retry = 10;
124 
125 	if (on) {
126 		regmap_update_bits(i2s->regmap, I2S_DMACR,
127 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
128 
129 		regmap_update_bits(i2s->regmap, I2S_XFER,
130 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START,
131 				   I2S_XFER_TXS_START | I2S_XFER_RXS_START);
132 
133 		i2s->rx_start = true;
134 	} else {
135 		i2s->rx_start = false;
136 
137 		regmap_update_bits(i2s->regmap, I2S_DMACR,
138 				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
139 
140 		if (!i2s->tx_start) {
141 			regmap_update_bits(i2s->regmap, I2S_XFER,
142 					   I2S_XFER_TXS_START |
143 					   I2S_XFER_RXS_START,
144 					   I2S_XFER_TXS_STOP |
145 					   I2S_XFER_RXS_STOP);
146 
147 			regmap_update_bits(i2s->regmap, I2S_CLR,
148 					   I2S_CLR_TXC | I2S_CLR_RXC,
149 					   I2S_CLR_TXC | I2S_CLR_RXC);
150 
151 			regmap_read(i2s->regmap, I2S_CLR, &val);
152 
153 			/* Should wait for clear operation to finish */
154 			while (val) {
155 				regmap_read(i2s->regmap, I2S_CLR, &val);
156 				retry--;
157 				if (!retry)
158 					dev_warn(i2s->dev, "fail to clear\n");
159 			}
160 		}
161 	}
162 }
163 
164 static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
165 				unsigned int fmt)
166 {
167 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
168 	unsigned int mask = 0, val = 0;
169 
170 	mask = I2S_CKR_MSS_MASK;
171 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
172 	case SND_SOC_DAIFMT_CBS_CFS:
173 		/* Set source clock in Master mode */
174 		val = I2S_CKR_MSS_MASTER;
175 		break;
176 	case SND_SOC_DAIFMT_CBM_CFM:
177 		val = I2S_CKR_MSS_SLAVE;
178 		break;
179 	default:
180 		return -EINVAL;
181 	}
182 
183 	regmap_update_bits(i2s->regmap, I2S_CKR, mask, val);
184 
185 	mask = I2S_TXCR_IBM_MASK;
186 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
187 	case SND_SOC_DAIFMT_RIGHT_J:
188 		val = I2S_TXCR_IBM_RSJM;
189 		break;
190 	case SND_SOC_DAIFMT_LEFT_J:
191 		val = I2S_TXCR_IBM_LSJM;
192 		break;
193 	case SND_SOC_DAIFMT_I2S:
194 		val = I2S_TXCR_IBM_NORMAL;
195 		break;
196 	default:
197 		return -EINVAL;
198 	}
199 
200 	regmap_update_bits(i2s->regmap, I2S_TXCR, mask, val);
201 
202 	mask = I2S_RXCR_IBM_MASK;
203 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
204 	case SND_SOC_DAIFMT_RIGHT_J:
205 		val = I2S_RXCR_IBM_RSJM;
206 		break;
207 	case SND_SOC_DAIFMT_LEFT_J:
208 		val = I2S_RXCR_IBM_LSJM;
209 		break;
210 	case SND_SOC_DAIFMT_I2S:
211 		val = I2S_RXCR_IBM_NORMAL;
212 		break;
213 	default:
214 		return -EINVAL;
215 	}
216 
217 	regmap_update_bits(i2s->regmap, I2S_RXCR, mask, val);
218 
219 	return 0;
220 }
221 
222 static int rockchip_i2s_hw_params(struct snd_pcm_substream *substream,
223 				  struct snd_pcm_hw_params *params,
224 				  struct snd_soc_dai *dai)
225 {
226 	struct rk_i2s_dev *i2s = to_info(dai);
227 	unsigned int val = 0;
228 
229 	switch (params_format(params)) {
230 	case SNDRV_PCM_FORMAT_S8:
231 		val |= I2S_TXCR_VDW(8);
232 		break;
233 	case SNDRV_PCM_FORMAT_S16_LE:
234 		val |= I2S_TXCR_VDW(16);
235 		break;
236 	case SNDRV_PCM_FORMAT_S20_3LE:
237 		val |= I2S_TXCR_VDW(20);
238 		break;
239 	case SNDRV_PCM_FORMAT_S24_LE:
240 		val |= I2S_TXCR_VDW(24);
241 		break;
242 	default:
243 		return -EINVAL;
244 	}
245 
246 	regmap_update_bits(i2s->regmap, I2S_TXCR, I2S_TXCR_VDW_MASK, val);
247 	regmap_update_bits(i2s->regmap, I2S_RXCR, I2S_RXCR_VDW_MASK, val);
248 
249 	return 0;
250 }
251 
252 static int rockchip_i2s_trigger(struct snd_pcm_substream *substream,
253 				int cmd, struct snd_soc_dai *dai)
254 {
255 	struct rk_i2s_dev *i2s = to_info(dai);
256 	int ret = 0;
257 
258 	switch (cmd) {
259 	case SNDRV_PCM_TRIGGER_START:
260 	case SNDRV_PCM_TRIGGER_RESUME:
261 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
262 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
263 			rockchip_snd_rxctrl(i2s, 1);
264 		else
265 			rockchip_snd_txctrl(i2s, 1);
266 		break;
267 	case SNDRV_PCM_TRIGGER_SUSPEND:
268 	case SNDRV_PCM_TRIGGER_STOP:
269 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
270 		if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
271 			rockchip_snd_rxctrl(i2s, 0);
272 		else
273 			rockchip_snd_txctrl(i2s, 0);
274 		break;
275 	default:
276 		ret = -EINVAL;
277 		break;
278 	}
279 
280 	return ret;
281 }
282 
283 static int rockchip_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
284 				   unsigned int freq, int dir)
285 {
286 	struct rk_i2s_dev *i2s = to_info(cpu_dai);
287 	int ret;
288 
289 	ret = clk_set_rate(i2s->mclk, freq);
290 	if (ret)
291 		dev_err(i2s->dev, "Fail to set mclk %d\n", ret);
292 
293 	return ret;
294 }
295 
296 static int rockchip_i2s_dai_probe(struct snd_soc_dai *dai)
297 {
298 	struct rk_i2s_dev *i2s = snd_soc_dai_get_drvdata(dai);
299 
300 	dai->capture_dma_data = &i2s->capture_dma_data;
301 	dai->playback_dma_data = &i2s->playback_dma_data;
302 
303 	return 0;
304 }
305 
306 static const struct snd_soc_dai_ops rockchip_i2s_dai_ops = {
307 	.hw_params = rockchip_i2s_hw_params,
308 	.set_sysclk = rockchip_i2s_set_sysclk,
309 	.set_fmt = rockchip_i2s_set_fmt,
310 	.trigger = rockchip_i2s_trigger,
311 };
312 
313 static struct snd_soc_dai_driver rockchip_i2s_dai = {
314 	.probe = rockchip_i2s_dai_probe,
315 	.playback = {
316 		.stream_name = "Playback",
317 		.channels_min = 2,
318 		.channels_max = 8,
319 		.rates = SNDRV_PCM_RATE_8000_192000,
320 		.formats = (SNDRV_PCM_FMTBIT_S8 |
321 			    SNDRV_PCM_FMTBIT_S16_LE |
322 			    SNDRV_PCM_FMTBIT_S20_3LE |
323 			    SNDRV_PCM_FMTBIT_S24_LE),
324 	},
325 	.capture = {
326 		.stream_name = "Capture",
327 		.channels_min = 2,
328 		.channels_max = 2,
329 		.rates = SNDRV_PCM_RATE_8000_192000,
330 		.formats = (SNDRV_PCM_FMTBIT_S8 |
331 			    SNDRV_PCM_FMTBIT_S16_LE |
332 			    SNDRV_PCM_FMTBIT_S20_3LE |
333 			    SNDRV_PCM_FMTBIT_S24_LE),
334 	},
335 	.ops = &rockchip_i2s_dai_ops,
336 };
337 
338 static const struct snd_soc_component_driver rockchip_i2s_component = {
339 	.name = DRV_NAME,
340 };
341 
342 static bool rockchip_i2s_wr_reg(struct device *dev, unsigned int reg)
343 {
344 	switch (reg) {
345 	case I2S_TXCR:
346 	case I2S_RXCR:
347 	case I2S_CKR:
348 	case I2S_DMACR:
349 	case I2S_INTCR:
350 	case I2S_XFER:
351 	case I2S_CLR:
352 	case I2S_TXDR:
353 		return true;
354 	default:
355 		return false;
356 	}
357 }
358 
359 static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
360 {
361 	switch (reg) {
362 	case I2S_TXCR:
363 	case I2S_RXCR:
364 	case I2S_CKR:
365 	case I2S_DMACR:
366 	case I2S_INTCR:
367 	case I2S_XFER:
368 	case I2S_CLR:
369 	case I2S_RXDR:
370 	case I2S_FIFOLR:
371 	case I2S_INTSR:
372 		return true;
373 	default:
374 		return false;
375 	}
376 }
377 
378 static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
379 {
380 	switch (reg) {
381 	case I2S_INTSR:
382 	case I2S_CLR:
383 		return true;
384 	default:
385 		return false;
386 	}
387 }
388 
389 static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
390 {
391 	switch (reg) {
392 	default:
393 		return false;
394 	}
395 }
396 
397 static const struct regmap_config rockchip_i2s_regmap_config = {
398 	.reg_bits = 32,
399 	.reg_stride = 4,
400 	.val_bits = 32,
401 	.max_register = I2S_RXDR,
402 	.writeable_reg = rockchip_i2s_wr_reg,
403 	.readable_reg = rockchip_i2s_rd_reg,
404 	.volatile_reg = rockchip_i2s_volatile_reg,
405 	.precious_reg = rockchip_i2s_precious_reg,
406 	.cache_type = REGCACHE_FLAT,
407 };
408 
409 static int rockchip_i2s_probe(struct platform_device *pdev)
410 {
411 	struct rk_i2s_dev *i2s;
412 	struct resource *res;
413 	void __iomem *regs;
414 	int ret;
415 
416 	i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
417 	if (!i2s) {
418 		dev_err(&pdev->dev, "Can't allocate rk_i2s_dev\n");
419 		return -ENOMEM;
420 	}
421 
422 	/* try to prepare related clocks */
423 	i2s->hclk = devm_clk_get(&pdev->dev, "i2s_hclk");
424 	if (IS_ERR(i2s->hclk)) {
425 		dev_err(&pdev->dev, "Can't retrieve i2s bus clock\n");
426 		return PTR_ERR(i2s->hclk);
427 	}
428 	ret = clk_prepare_enable(i2s->hclk);
429 	if (ret) {
430 		dev_err(i2s->dev, "hclock enable failed %d\n", ret);
431 		return ret;
432 	}
433 
434 	i2s->mclk = devm_clk_get(&pdev->dev, "i2s_clk");
435 	if (IS_ERR(i2s->mclk)) {
436 		dev_err(&pdev->dev, "Can't retrieve i2s master clock\n");
437 		return PTR_ERR(i2s->mclk);
438 	}
439 
440 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
441 	regs = devm_ioremap_resource(&pdev->dev, res);
442 	if (IS_ERR(regs))
443 		return PTR_ERR(regs);
444 
445 	i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
446 					    &rockchip_i2s_regmap_config);
447 	if (IS_ERR(i2s->regmap)) {
448 		dev_err(&pdev->dev,
449 			"Failed to initialise managed register map\n");
450 		return PTR_ERR(i2s->regmap);
451 	}
452 
453 	i2s->playback_dma_data.addr = res->start + I2S_TXDR;
454 	i2s->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
455 	i2s->playback_dma_data.maxburst = 16;
456 
457 	i2s->capture_dma_data.addr = res->start + I2S_RXDR;
458 	i2s->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
459 	i2s->capture_dma_data.maxburst = 16;
460 
461 	i2s->dev = &pdev->dev;
462 	dev_set_drvdata(&pdev->dev, i2s);
463 
464 	pm_runtime_enable(&pdev->dev);
465 	if (!pm_runtime_enabled(&pdev->dev)) {
466 		ret = i2s_runtime_resume(&pdev->dev);
467 		if (ret)
468 			goto err_pm_disable;
469 	}
470 
471 	ret = devm_snd_soc_register_component(&pdev->dev,
472 					      &rockchip_i2s_component,
473 					      &rockchip_i2s_dai, 1);
474 	if (ret) {
475 		dev_err(&pdev->dev, "Could not register DAI\n");
476 		goto err_suspend;
477 	}
478 
479 	ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
480 	if (ret) {
481 		dev_err(&pdev->dev, "Could not register PCM\n");
482 		goto err_pcm_register;
483 	}
484 
485 	return 0;
486 
487 err_pcm_register:
488 	snd_dmaengine_pcm_unregister(&pdev->dev);
489 err_suspend:
490 	if (!pm_runtime_status_suspended(&pdev->dev))
491 		i2s_runtime_suspend(&pdev->dev);
492 err_pm_disable:
493 	pm_runtime_disable(&pdev->dev);
494 
495 	return ret;
496 }
497 
498 static int rockchip_i2s_remove(struct platform_device *pdev)
499 {
500 	struct rk_i2s_dev *i2s = dev_get_drvdata(&pdev->dev);
501 
502 	pm_runtime_disable(&pdev->dev);
503 	if (!pm_runtime_status_suspended(&pdev->dev))
504 		i2s_runtime_suspend(&pdev->dev);
505 
506 	clk_disable_unprepare(i2s->mclk);
507 	clk_disable_unprepare(i2s->hclk);
508 	snd_dmaengine_pcm_unregister(&pdev->dev);
509 	snd_soc_unregister_component(&pdev->dev);
510 
511 	return 0;
512 }
513 
514 static const struct of_device_id rockchip_i2s_match[] = {
515 	{ .compatible = "rockchip,rk3066-i2s", },
516 	{},
517 };
518 
519 static const struct dev_pm_ops rockchip_i2s_pm_ops = {
520 	SET_RUNTIME_PM_OPS(i2s_runtime_suspend, i2s_runtime_resume,
521 			   NULL)
522 };
523 
524 static struct platform_driver rockchip_i2s_driver = {
525 	.probe = rockchip_i2s_probe,
526 	.remove = rockchip_i2s_remove,
527 	.driver = {
528 		.name = DRV_NAME,
529 		.owner = THIS_MODULE,
530 		.of_match_table = of_match_ptr(rockchip_i2s_match),
531 		.pm = &rockchip_i2s_pm_ops,
532 	},
533 };
534 module_platform_driver(rockchip_i2s_driver);
535 
536 MODULE_DESCRIPTION("ROCKCHIP IIS ASoC Interface");
537 MODULE_AUTHOR("jianqun <jay.xu@rock-chips.com>");
538 MODULE_LICENSE("GPL v2");
539 MODULE_ALIAS("platform:" DRV_NAME);
540 MODULE_DEVICE_TABLE(of, rockchip_i2s_match);
541