1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 #include <sound/soc.h> 16 17 /* REGISTER OFFSET */ 18 #define SSICR 0x000 19 #define SSISR 0x004 20 #define SSIFCR 0x010 21 #define SSIFSR 0x014 22 #define SSIFTDR 0x018 23 #define SSIFRDR 0x01c 24 #define SSIOFR 0x020 25 #define SSISCR 0x024 26 27 /* SSI REGISTER BITS */ 28 #define SSICR_DWL(x) (((x) & 0x7) << 19) 29 #define SSICR_SWL(x) (((x) & 0x7) << 16) 30 31 #define SSICR_CKS BIT(30) 32 #define SSICR_TUIEN BIT(29) 33 #define SSICR_TOIEN BIT(28) 34 #define SSICR_RUIEN BIT(27) 35 #define SSICR_ROIEN BIT(26) 36 #define SSICR_MST BIT(14) 37 #define SSICR_BCKP BIT(13) 38 #define SSICR_LRCKP BIT(12) 39 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 40 #define SSICR_TEN BIT(1) 41 #define SSICR_REN BIT(0) 42 43 #define SSISR_TUIRQ BIT(29) 44 #define SSISR_TOIRQ BIT(28) 45 #define SSISR_RUIRQ BIT(27) 46 #define SSISR_ROIRQ BIT(26) 47 #define SSISR_IIRQ BIT(25) 48 49 #define SSIFCR_AUCKE BIT(31) 50 #define SSIFCR_SSIRST BIT(16) 51 #define SSIFCR_TIE BIT(3) 52 #define SSIFCR_RIE BIT(2) 53 #define SSIFCR_TFRST BIT(1) 54 #define SSIFCR_RFRST BIT(0) 55 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 56 57 #define SSIFSR_TDC_MASK 0x3f 58 #define SSIFSR_TDC_SHIFT 24 59 #define SSIFSR_RDC_MASK 0x3f 60 #define SSIFSR_RDC_SHIFT 8 61 62 #define SSIFSR_TDE BIT(16) 63 #define SSIFSR_RDF BIT(0) 64 65 #define SSIOFR_LRCONT BIT(8) 66 67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 69 70 /* Pre allocated buffers sizes */ 71 #define PREALLOC_BUFFER (SZ_32K) 72 #define PREALLOC_BUFFER_MAX (SZ_32K) 73 74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 76 #define SSI_CHAN_MIN 2 77 #define SSI_CHAN_MAX 2 78 #define SSI_FIFO_DEPTH 32 79 80 struct rz_ssi_priv; 81 82 struct rz_ssi_stream { 83 struct rz_ssi_priv *priv; 84 struct snd_pcm_substream *substream; 85 int fifo_sample_size; /* sample capacity of SSI FIFO */ 86 int dma_buffer_pos; /* The address for the next DMA descriptor */ 87 int period_counter; /* for keeping track of periods transferred */ 88 int sample_width; 89 int buffer_pos; /* current frame position in the buffer */ 90 int running; /* 0=stopped, 1=running */ 91 92 int uerr_num; 93 int oerr_num; 94 95 struct dma_chan *dma_ch; 96 97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 98 }; 99 100 struct rz_ssi_priv { 101 void __iomem *base; 102 struct reset_control *rstc; 103 struct device *dev; 104 struct clk *sfr_clk; 105 struct clk *clk; 106 107 phys_addr_t phys; 108 int irq_int; 109 int irq_tx; 110 int irq_rx; 111 int irq_rt; 112 113 spinlock_t lock; 114 115 /* 116 * The SSI supports full-duplex transmission and reception. 117 * However, if an error occurs, channel reset (both transmission 118 * and reception reset) is required. 119 * So it is better to use as half-duplex (playing and recording 120 * should be done on separate channels). 121 */ 122 struct rz_ssi_stream playback; 123 struct rz_ssi_stream capture; 124 125 /* clock */ 126 unsigned long audio_mck; 127 unsigned long audio_clk_1; 128 unsigned long audio_clk_2; 129 130 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 131 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 132 bool dma_rt; 133 134 /* Full duplex communication support */ 135 struct { 136 unsigned int rate; 137 unsigned int channels; 138 unsigned int sample_width; 139 unsigned int sample_bits; 140 } hw_params_cache; 141 }; 142 143 static void rz_ssi_dma_complete(void *data); 144 145 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 146 { 147 writel(data, (priv->base + reg)); 148 } 149 150 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 151 { 152 return readl(priv->base + reg); 153 } 154 155 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 156 u32 bclr, u32 bset) 157 { 158 u32 val; 159 160 val = readl(priv->base + reg); 161 val = (val & ~bclr) | bset; 162 writel(val, (priv->base + reg)); 163 } 164 165 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi, 166 struct snd_pcm_substream *substream) 167 { 168 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 169 } 170 171 static inline struct rz_ssi_stream * 172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 173 { 174 struct rz_ssi_stream *stream = &ssi->playback; 175 176 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 177 stream = &ssi->capture; 178 179 return stream; 180 } 181 182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 183 { 184 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 185 } 186 187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 188 struct snd_pcm_substream *substream) 189 { 190 struct rz_ssi_priv *ssi = strm->priv; 191 unsigned long flags; 192 193 spin_lock_irqsave(&ssi->lock, flags); 194 strm->substream = substream; 195 spin_unlock_irqrestore(&ssi->lock, flags); 196 } 197 198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 199 struct rz_ssi_stream *strm) 200 { 201 unsigned long flags; 202 bool ret; 203 204 spin_lock_irqsave(&ssi->lock, flags); 205 ret = strm->substream && strm->substream->runtime; 206 spin_unlock_irqrestore(&ssi->lock, flags); 207 208 return ret; 209 } 210 211 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 212 { 213 return strm->substream && strm->running; 214 } 215 216 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 217 struct snd_pcm_substream *substream) 218 { 219 struct snd_pcm_runtime *runtime = substream->runtime; 220 221 rz_ssi_set_substream(strm, substream); 222 strm->sample_width = samples_to_bytes(runtime, 1); 223 strm->dma_buffer_pos = 0; 224 strm->period_counter = 0; 225 strm->buffer_pos = 0; 226 227 strm->oerr_num = 0; 228 strm->uerr_num = 0; 229 strm->running = 0; 230 231 /* fifo init */ 232 strm->fifo_sample_size = SSI_FIFO_DEPTH; 233 } 234 235 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 236 struct rz_ssi_stream *strm) 237 { 238 struct device *dev = ssi->dev; 239 240 rz_ssi_set_substream(strm, NULL); 241 242 if (strm->oerr_num > 0) 243 dev_info(dev, "overrun = %d\n", strm->oerr_num); 244 245 if (strm->uerr_num > 0) 246 dev_info(dev, "underrun = %d\n", strm->uerr_num); 247 } 248 249 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 250 unsigned int channels) 251 { 252 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 253 unsigned int channel_bits = 32; /* System Word Length */ 254 unsigned long bclk_rate = rate * channels * channel_bits; 255 unsigned int div; 256 unsigned int i; 257 u32 ssicr = 0; 258 u32 clk_ckdv; 259 260 /* Clear AUCKE so we can set MST */ 261 rz_ssi_reg_writel(ssi, SSIFCR, 0); 262 263 /* Continue to output LRCK pin even when idle */ 264 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 265 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 266 if (ssi->audio_clk_1 % bclk_rate) 267 ssi->audio_mck = ssi->audio_clk_2; 268 else 269 ssi->audio_mck = ssi->audio_clk_1; 270 } 271 272 /* Clock setting */ 273 ssicr |= SSICR_MST; 274 if (ssi->audio_mck == ssi->audio_clk_1) 275 ssicr |= SSICR_CKS; 276 if (ssi->bckp_rise) 277 ssicr |= SSICR_BCKP; 278 if (ssi->lrckp_fsync_fall) 279 ssicr |= SSICR_LRCKP; 280 281 /* Determine the clock divider */ 282 clk_ckdv = 0; 283 div = ssi->audio_mck / bclk_rate; 284 /* try to find an match */ 285 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 286 if (ckdv[i] == div) { 287 clk_ckdv = i; 288 break; 289 } 290 } 291 292 if (i == ARRAY_SIZE(ckdv)) { 293 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 294 return -EINVAL; 295 } 296 297 /* 298 * DWL: Data Word Length = 16 bits 299 * SWL: System Word Length = 32 bits 300 */ 301 ssicr |= SSICR_CKDV(clk_ckdv); 302 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 303 rz_ssi_reg_writel(ssi, SSICR, ssicr); 304 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 305 306 return 0; 307 } 308 309 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 310 { 311 int timeout; 312 313 /* Disable irqs */ 314 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 315 SSICR_RUIEN | SSICR_ROIEN, 0); 316 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 317 318 /* Clear all error flags */ 319 rz_ssi_reg_mask_setl(ssi, SSISR, 320 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 321 SSISR_RUIRQ), 0); 322 323 /* Wait for idle */ 324 timeout = 100; 325 while (--timeout) { 326 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ) 327 break; 328 udelay(1); 329 } 330 331 if (!timeout) 332 dev_info(ssi->dev, "timeout waiting for SSI idle\n"); 333 334 /* Hold FIFOs in reset */ 335 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 336 } 337 338 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 339 { 340 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream); 341 bool is_full_duplex; 342 u32 ssicr, ssifcr; 343 344 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 345 rz_ssi_is_stream_running(&ssi->capture); 346 ssicr = rz_ssi_reg_readl(ssi, SSICR); 347 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 348 if (!is_full_duplex) { 349 ssifcr &= ~0xF; 350 } else { 351 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 352 rz_ssi_set_idle(ssi); 353 ssifcr &= ~SSIFCR_FIFO_RST; 354 } 355 356 /* FIFO interrupt thresholds */ 357 if (rz_ssi_is_dma_enabled(ssi)) 358 rz_ssi_reg_writel(ssi, SSISCR, 0); 359 else 360 rz_ssi_reg_writel(ssi, SSISCR, 361 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 362 SSISCR_RDFS(0)); 363 364 /* enable IRQ */ 365 if (is_play) { 366 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 367 ssifcr |= SSIFCR_TIE; 368 if (!is_full_duplex) 369 ssifcr |= SSIFCR_RFRST; 370 } else { 371 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 372 ssifcr |= SSIFCR_RIE; 373 if (!is_full_duplex) 374 ssifcr |= SSIFCR_TFRST; 375 } 376 377 rz_ssi_reg_writel(ssi, SSICR, ssicr); 378 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 379 380 /* Clear all error flags */ 381 rz_ssi_reg_mask_setl(ssi, SSISR, 382 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 383 SSISR_RUIRQ), 0); 384 385 strm->running = 1; 386 if (is_full_duplex) 387 ssicr |= SSICR_TEN | SSICR_REN; 388 else 389 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 390 391 rz_ssi_reg_writel(ssi, SSICR, ssicr); 392 393 return 0; 394 } 395 396 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 397 { 398 strm->running = 0; 399 400 if (rz_ssi_is_stream_running(&ssi->playback) || 401 rz_ssi_is_stream_running(&ssi->capture)) 402 return 0; 403 404 /* Disable TX/RX */ 405 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 406 407 /* Cancel all remaining DMA transactions */ 408 if (rz_ssi_is_dma_enabled(ssi)) { 409 if (ssi->playback.dma_ch) 410 dmaengine_terminate_async(ssi->playback.dma_ch); 411 if (ssi->capture.dma_ch) 412 dmaengine_terminate_async(ssi->capture.dma_ch); 413 } 414 415 rz_ssi_set_idle(ssi); 416 417 return 0; 418 } 419 420 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 421 { 422 struct snd_pcm_substream *substream = strm->substream; 423 struct snd_pcm_runtime *runtime; 424 int current_period; 425 426 if (!strm->running || !substream || !substream->runtime) 427 return; 428 429 runtime = substream->runtime; 430 strm->buffer_pos += frames; 431 WARN_ON(strm->buffer_pos > runtime->buffer_size); 432 433 /* ring buffer */ 434 if (strm->buffer_pos == runtime->buffer_size) 435 strm->buffer_pos = 0; 436 437 current_period = strm->buffer_pos / runtime->period_size; 438 if (strm->period_counter != current_period) { 439 snd_pcm_period_elapsed(strm->substream); 440 strm->period_counter = current_period; 441 } 442 } 443 444 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 445 { 446 struct snd_pcm_substream *substream = strm->substream; 447 struct snd_pcm_runtime *runtime; 448 u16 *buf; 449 int fifo_samples; 450 int frames_left; 451 int samples; 452 int i; 453 454 if (!rz_ssi_stream_is_valid(ssi, strm)) 455 return -EINVAL; 456 457 runtime = substream->runtime; 458 459 do { 460 /* frames left in this period */ 461 frames_left = runtime->period_size - 462 (strm->buffer_pos % runtime->period_size); 463 if (!frames_left) 464 frames_left = runtime->period_size; 465 466 /* Samples in RX FIFO */ 467 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 468 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 469 470 /* Only read full frames at a time */ 471 samples = 0; 472 while (frames_left && (fifo_samples >= runtime->channels)) { 473 samples += runtime->channels; 474 fifo_samples -= runtime->channels; 475 frames_left--; 476 } 477 478 /* not enough samples yet */ 479 if (!samples) 480 break; 481 482 /* calculate new buffer index */ 483 buf = (u16 *)runtime->dma_area; 484 buf += strm->buffer_pos * runtime->channels; 485 486 /* Note, only supports 16-bit samples */ 487 for (i = 0; i < samples; i++) 488 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 489 490 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 491 rz_ssi_pointer_update(strm, samples / runtime->channels); 492 } while (!frames_left && fifo_samples >= runtime->channels); 493 494 return 0; 495 } 496 497 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 498 { 499 struct snd_pcm_substream *substream = strm->substream; 500 struct snd_pcm_runtime *runtime = substream->runtime; 501 int sample_space; 502 int samples = 0; 503 int frames_left; 504 int i; 505 u32 ssifsr; 506 u16 *buf; 507 508 if (!rz_ssi_stream_is_valid(ssi, strm)) 509 return -EINVAL; 510 511 /* frames left in this period */ 512 frames_left = runtime->period_size - (strm->buffer_pos % 513 runtime->period_size); 514 if (frames_left == 0) 515 frames_left = runtime->period_size; 516 517 sample_space = strm->fifo_sample_size; 518 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 519 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 520 521 /* Only add full frames at a time */ 522 while (frames_left && (sample_space >= runtime->channels)) { 523 samples += runtime->channels; 524 sample_space -= runtime->channels; 525 frames_left--; 526 } 527 528 /* no space to send anything right now */ 529 if (samples == 0) 530 return 0; 531 532 /* calculate new buffer index */ 533 buf = (u16 *)(runtime->dma_area); 534 buf += strm->buffer_pos * runtime->channels; 535 536 /* Note, only supports 16-bit samples */ 537 for (i = 0; i < samples; i++) 538 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 539 540 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 541 rz_ssi_pointer_update(strm, samples / runtime->channels); 542 543 return 0; 544 } 545 546 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 547 { 548 struct rz_ssi_stream *strm_playback = NULL; 549 struct rz_ssi_stream *strm_capture = NULL; 550 struct rz_ssi_priv *ssi = data; 551 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 552 553 if (ssi->playback.substream) 554 strm_playback = &ssi->playback; 555 if (ssi->capture.substream) 556 strm_capture = &ssi->capture; 557 558 if (!strm_playback && !strm_capture) 559 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 560 561 if (irq == ssi->irq_int) { /* error or idle */ 562 bool is_stopped = false; 563 int i, count; 564 565 if (rz_ssi_is_dma_enabled(ssi)) 566 count = 4; 567 else 568 count = 1; 569 570 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 571 is_stopped = true; 572 573 if (ssi->capture.substream && is_stopped) { 574 if (ssisr & SSISR_RUIRQ) 575 strm_capture->uerr_num++; 576 if (ssisr & SSISR_ROIRQ) 577 strm_capture->oerr_num++; 578 579 rz_ssi_stop(ssi, strm_capture); 580 } 581 582 if (ssi->playback.substream && is_stopped) { 583 if (ssisr & SSISR_TUIRQ) 584 strm_playback->uerr_num++; 585 if (ssisr & SSISR_TOIRQ) 586 strm_playback->oerr_num++; 587 588 rz_ssi_stop(ssi, strm_playback); 589 } 590 591 /* Clear all flags */ 592 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 593 SSISR_ROIRQ | SSISR_RUIRQ, 0); 594 595 /* Add/remove more data */ 596 if (ssi->capture.substream && is_stopped) { 597 for (i = 0; i < count; i++) 598 strm_capture->transfer(ssi, strm_capture); 599 } 600 601 if (ssi->playback.substream && is_stopped) { 602 for (i = 0; i < count; i++) 603 strm_playback->transfer(ssi, strm_playback); 604 } 605 606 /* Resume */ 607 if (ssi->playback.substream && is_stopped) 608 rz_ssi_start(ssi, &ssi->playback); 609 if (ssi->capture.substream && is_stopped) 610 rz_ssi_start(ssi, &ssi->capture); 611 } 612 613 if (!rz_ssi_is_stream_running(&ssi->playback) && 614 !rz_ssi_is_stream_running(&ssi->capture)) 615 return IRQ_HANDLED; 616 617 /* tx data empty */ 618 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 619 strm_playback->transfer(ssi, &ssi->playback); 620 621 /* rx data full */ 622 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 623 strm_capture->transfer(ssi, &ssi->capture); 624 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 625 } 626 627 if (irq == ssi->irq_rt) { 628 if (ssi->playback.substream) { 629 strm_playback->transfer(ssi, &ssi->playback); 630 } else { 631 strm_capture->transfer(ssi, &ssi->capture); 632 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 633 } 634 } 635 636 return IRQ_HANDLED; 637 } 638 639 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 640 struct dma_chan *dma_ch, bool is_play) 641 { 642 struct dma_slave_config cfg; 643 644 memset(&cfg, 0, sizeof(cfg)); 645 646 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 647 cfg.dst_addr = ssi->phys + SSIFTDR; 648 cfg.src_addr = ssi->phys + SSIFRDR; 649 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 650 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 651 652 return dmaengine_slave_config(dma_ch, &cfg); 653 } 654 655 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 656 struct rz_ssi_stream *strm) 657 { 658 struct snd_pcm_substream *substream = strm->substream; 659 struct dma_async_tx_descriptor *desc; 660 struct snd_pcm_runtime *runtime; 661 enum dma_transfer_direction dir; 662 u32 dma_paddr, dma_size; 663 int amount; 664 665 if (!rz_ssi_stream_is_valid(ssi, strm)) 666 return -EINVAL; 667 668 runtime = substream->runtime; 669 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 670 /* 671 * Stream is ending, so do not queue up any more DMA 672 * transfers otherwise we play partial sound clips 673 * because we can't shut off the DMA quick enough. 674 */ 675 return 0; 676 677 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 678 679 /* Always transfer 1 period */ 680 amount = runtime->period_size; 681 682 /* DMA physical address and size */ 683 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 684 strm->dma_buffer_pos); 685 dma_size = frames_to_bytes(runtime, amount); 686 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 687 dir, 688 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 689 if (!desc) { 690 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 691 return -ENOMEM; 692 } 693 694 desc->callback = rz_ssi_dma_complete; 695 desc->callback_param = strm; 696 697 if (dmaengine_submit(desc) < 0) { 698 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 699 return -EIO; 700 } 701 702 /* Update DMA pointer */ 703 strm->dma_buffer_pos += amount; 704 if (strm->dma_buffer_pos >= runtime->buffer_size) 705 strm->dma_buffer_pos = 0; 706 707 /* Start DMA */ 708 dma_async_issue_pending(strm->dma_ch); 709 710 return 0; 711 } 712 713 static void rz_ssi_dma_complete(void *data) 714 { 715 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 716 717 if (!strm->running || !strm->substream || !strm->substream->runtime) 718 return; 719 720 /* Note that next DMA transaction has probably already started */ 721 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 722 723 /* Queue up another DMA transaction */ 724 rz_ssi_dma_transfer(strm->priv, strm); 725 } 726 727 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 728 { 729 if (ssi->playback.dma_ch) { 730 dma_release_channel(ssi->playback.dma_ch); 731 ssi->playback.dma_ch = NULL; 732 if (ssi->dma_rt) 733 ssi->dma_rt = false; 734 } 735 736 if (ssi->capture.dma_ch) { 737 dma_release_channel(ssi->capture.dma_ch); 738 ssi->capture.dma_ch = NULL; 739 } 740 } 741 742 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 743 { 744 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 745 if (IS_ERR(ssi->playback.dma_ch)) 746 ssi->playback.dma_ch = NULL; 747 748 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 749 if (IS_ERR(ssi->capture.dma_ch)) 750 ssi->capture.dma_ch = NULL; 751 752 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 753 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 754 if (IS_ERR(ssi->playback.dma_ch)) { 755 ssi->playback.dma_ch = NULL; 756 goto no_dma; 757 } 758 759 ssi->dma_rt = true; 760 } 761 762 if (!rz_ssi_is_dma_enabled(ssi)) 763 goto no_dma; 764 765 if (ssi->playback.dma_ch && 766 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 767 goto no_dma; 768 769 if (ssi->capture.dma_ch && 770 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 771 goto no_dma; 772 773 return 0; 774 775 no_dma: 776 rz_ssi_release_dma_channels(ssi); 777 778 return -ENODEV; 779 } 780 781 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 782 struct snd_soc_dai *dai) 783 { 784 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 785 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 786 int ret = 0, i, num_transfer = 1; 787 788 switch (cmd) { 789 case SNDRV_PCM_TRIGGER_START: 790 /* Soft Reset */ 791 if (!rz_ssi_is_stream_running(&ssi->playback) && 792 !rz_ssi_is_stream_running(&ssi->capture)) { 793 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 794 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 795 udelay(5); 796 } 797 798 rz_ssi_stream_init(strm, substream); 799 800 if (ssi->dma_rt) { 801 bool is_playback; 802 803 is_playback = rz_ssi_stream_is_play(ssi, substream); 804 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 805 is_playback); 806 /* Fallback to pio */ 807 if (ret < 0) { 808 ssi->playback.transfer = rz_ssi_pio_send; 809 ssi->capture.transfer = rz_ssi_pio_recv; 810 rz_ssi_release_dma_channels(ssi); 811 } 812 } 813 814 /* For DMA, queue up multiple DMA descriptors */ 815 if (rz_ssi_is_dma_enabled(ssi)) 816 num_transfer = 4; 817 818 for (i = 0; i < num_transfer; i++) { 819 ret = strm->transfer(ssi, strm); 820 if (ret) 821 goto done; 822 } 823 824 ret = rz_ssi_start(ssi, strm); 825 break; 826 case SNDRV_PCM_TRIGGER_STOP: 827 rz_ssi_stop(ssi, strm); 828 rz_ssi_stream_quit(ssi, strm); 829 break; 830 } 831 832 done: 833 return ret; 834 } 835 836 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 837 { 838 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 839 840 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 841 case SND_SOC_DAIFMT_BP_FP: 842 break; 843 default: 844 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 845 return -EINVAL; 846 } 847 848 /* 849 * set clock polarity 850 * 851 * "normal" BCLK = Signal is available at rising edge of BCLK 852 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 853 */ 854 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 855 case SND_SOC_DAIFMT_NB_NF: 856 ssi->bckp_rise = false; 857 ssi->lrckp_fsync_fall = false; 858 break; 859 case SND_SOC_DAIFMT_NB_IF: 860 ssi->bckp_rise = false; 861 ssi->lrckp_fsync_fall = true; 862 break; 863 case SND_SOC_DAIFMT_IB_NF: 864 ssi->bckp_rise = true; 865 ssi->lrckp_fsync_fall = false; 866 break; 867 case SND_SOC_DAIFMT_IB_IF: 868 ssi->bckp_rise = true; 869 ssi->lrckp_fsync_fall = true; 870 break; 871 default: 872 return -EINVAL; 873 } 874 875 /* only i2s support */ 876 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 877 case SND_SOC_DAIFMT_I2S: 878 break; 879 default: 880 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 881 return -EINVAL; 882 } 883 884 return 0; 885 } 886 887 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 888 unsigned int channels, 889 unsigned int sample_width, 890 unsigned int sample_bits) 891 { 892 if (ssi->hw_params_cache.rate != rate || 893 ssi->hw_params_cache.channels != channels || 894 ssi->hw_params_cache.sample_width != sample_width || 895 ssi->hw_params_cache.sample_bits != sample_bits) 896 return false; 897 898 return true; 899 } 900 901 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 902 unsigned int channels, 903 unsigned int sample_width, 904 unsigned int sample_bits) 905 { 906 ssi->hw_params_cache.rate = rate; 907 ssi->hw_params_cache.channels = channels; 908 ssi->hw_params_cache.sample_width = sample_width; 909 ssi->hw_params_cache.sample_bits = sample_bits; 910 } 911 912 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 913 struct snd_pcm_hw_params *params, 914 struct snd_soc_dai *dai) 915 { 916 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 917 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 918 unsigned int sample_bits = hw_param_interval(params, 919 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 920 unsigned int channels = params_channels(params); 921 unsigned int rate = params_rate(params); 922 923 if (sample_bits != 16) { 924 dev_err(ssi->dev, "Unsupported sample width: %d\n", 925 sample_bits); 926 return -EINVAL; 927 } 928 929 if (channels != 2) { 930 dev_err(ssi->dev, "Number of channels not matched: %d\n", 931 channels); 932 return -EINVAL; 933 } 934 935 if (rz_ssi_is_stream_running(&ssi->playback) || 936 rz_ssi_is_stream_running(&ssi->capture)) { 937 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 938 strm->sample_width, sample_bits)) 939 return 0; 940 941 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 942 return -EINVAL; 943 } 944 945 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 946 sample_bits); 947 948 return rz_ssi_clk_setup(ssi, rate, channels); 949 } 950 951 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 952 .trigger = rz_ssi_dai_trigger, 953 .set_fmt = rz_ssi_dai_set_fmt, 954 .hw_params = rz_ssi_dai_hw_params, 955 }; 956 957 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 958 .info = SNDRV_PCM_INFO_INTERLEAVED | 959 SNDRV_PCM_INFO_MMAP | 960 SNDRV_PCM_INFO_MMAP_VALID, 961 .buffer_bytes_max = PREALLOC_BUFFER, 962 .period_bytes_min = 32, 963 .period_bytes_max = 8192, 964 .channels_min = SSI_CHAN_MIN, 965 .channels_max = SSI_CHAN_MAX, 966 .periods_min = 1, 967 .periods_max = 32, 968 .fifo_size = 32 * 2, 969 }; 970 971 static int rz_ssi_pcm_open(struct snd_soc_component *component, 972 struct snd_pcm_substream *substream) 973 { 974 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 975 976 return snd_pcm_hw_constraint_integer(substream->runtime, 977 SNDRV_PCM_HW_PARAM_PERIODS); 978 } 979 980 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 981 struct snd_pcm_substream *substream) 982 { 983 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 984 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 985 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 986 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 987 988 return strm->buffer_pos; 989 } 990 991 static int rz_ssi_pcm_new(struct snd_soc_component *component, 992 struct snd_soc_pcm_runtime *rtd) 993 { 994 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 995 rtd->card->snd_card->dev, 996 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 997 return 0; 998 } 999 1000 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1001 { 1002 .name = "rz-ssi-dai", 1003 .playback = { 1004 .rates = SSI_RATES, 1005 .formats = SSI_FMTS, 1006 .channels_min = SSI_CHAN_MIN, 1007 .channels_max = SSI_CHAN_MAX, 1008 }, 1009 .capture = { 1010 .rates = SSI_RATES, 1011 .formats = SSI_FMTS, 1012 .channels_min = SSI_CHAN_MIN, 1013 .channels_max = SSI_CHAN_MAX, 1014 }, 1015 .ops = &rz_ssi_dai_ops, 1016 }, 1017 }; 1018 1019 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1020 .name = "rz-ssi", 1021 .open = rz_ssi_pcm_open, 1022 .pointer = rz_ssi_pcm_pointer, 1023 .pcm_construct = rz_ssi_pcm_new, 1024 .legacy_dai_naming = 1, 1025 }; 1026 1027 static int rz_ssi_probe(struct platform_device *pdev) 1028 { 1029 struct rz_ssi_priv *ssi; 1030 struct clk *audio_clk; 1031 struct resource *res; 1032 int ret; 1033 1034 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 1035 if (!ssi) 1036 return -ENOMEM; 1037 1038 ssi->dev = &pdev->dev; 1039 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1040 if (IS_ERR(ssi->base)) 1041 return PTR_ERR(ssi->base); 1042 1043 ssi->phys = res->start; 1044 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 1045 if (IS_ERR(ssi->clk)) 1046 return PTR_ERR(ssi->clk); 1047 1048 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 1049 if (IS_ERR(ssi->sfr_clk)) 1050 return PTR_ERR(ssi->sfr_clk); 1051 1052 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 1053 if (IS_ERR(audio_clk)) 1054 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1055 "no audio clk1"); 1056 1057 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1058 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 1059 if (IS_ERR(audio_clk)) 1060 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1061 "no audio clk2"); 1062 1063 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1064 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1065 return dev_err_probe(&pdev->dev, -EINVAL, 1066 "no audio clk1 or audio clk2"); 1067 1068 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1069 1070 /* Detect DMA support */ 1071 ret = rz_ssi_dma_request(ssi, &pdev->dev); 1072 if (ret < 0) { 1073 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1074 ssi->playback.transfer = rz_ssi_pio_send; 1075 ssi->capture.transfer = rz_ssi_pio_recv; 1076 } else { 1077 dev_info(&pdev->dev, "DMA enabled"); 1078 ssi->playback.transfer = rz_ssi_dma_transfer; 1079 ssi->capture.transfer = rz_ssi_dma_transfer; 1080 } 1081 1082 ssi->playback.priv = ssi; 1083 ssi->capture.priv = ssi; 1084 1085 spin_lock_init(&ssi->lock); 1086 dev_set_drvdata(&pdev->dev, ssi); 1087 1088 /* Error Interrupt */ 1089 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1090 if (ssi->irq_int < 0) { 1091 rz_ssi_release_dma_channels(ssi); 1092 return ssi->irq_int; 1093 } 1094 1095 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 1096 0, dev_name(&pdev->dev), ssi); 1097 if (ret < 0) { 1098 rz_ssi_release_dma_channels(ssi); 1099 return dev_err_probe(&pdev->dev, ret, 1100 "irq request error (int_req)\n"); 1101 } 1102 1103 if (!rz_ssi_is_dma_enabled(ssi)) { 1104 /* Tx and Rx interrupts (pio only) */ 1105 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1106 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1107 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1108 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1109 if (ssi->irq_rt < 0) 1110 return ssi->irq_rt; 1111 1112 ret = devm_request_irq(&pdev->dev, ssi->irq_rt, 1113 &rz_ssi_interrupt, 0, 1114 dev_name(&pdev->dev), ssi); 1115 if (ret < 0) 1116 return dev_err_probe(&pdev->dev, ret, 1117 "irq request error (dma_rt)\n"); 1118 } else { 1119 if (ssi->irq_tx < 0) 1120 return ssi->irq_tx; 1121 1122 if (ssi->irq_rx < 0) 1123 return ssi->irq_rx; 1124 1125 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1126 &rz_ssi_interrupt, 0, 1127 dev_name(&pdev->dev), ssi); 1128 if (ret < 0) 1129 return dev_err_probe(&pdev->dev, ret, 1130 "irq request error (dma_tx)\n"); 1131 1132 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1133 &rz_ssi_interrupt, 0, 1134 dev_name(&pdev->dev), ssi); 1135 if (ret < 0) 1136 return dev_err_probe(&pdev->dev, ret, 1137 "irq request error (dma_rx)\n"); 1138 } 1139 } 1140 1141 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1142 if (IS_ERR(ssi->rstc)) { 1143 ret = PTR_ERR(ssi->rstc); 1144 goto err_reset; 1145 } 1146 1147 reset_control_deassert(ssi->rstc); 1148 pm_runtime_enable(&pdev->dev); 1149 ret = pm_runtime_resume_and_get(&pdev->dev); 1150 if (ret < 0) { 1151 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1152 goto err_pm; 1153 } 1154 1155 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1156 rz_ssi_soc_dai, 1157 ARRAY_SIZE(rz_ssi_soc_dai)); 1158 if (ret < 0) { 1159 dev_err(&pdev->dev, "failed to register snd component\n"); 1160 goto err_snd_soc; 1161 } 1162 1163 return 0; 1164 1165 err_snd_soc: 1166 pm_runtime_put(ssi->dev); 1167 err_pm: 1168 pm_runtime_disable(ssi->dev); 1169 reset_control_assert(ssi->rstc); 1170 err_reset: 1171 rz_ssi_release_dma_channels(ssi); 1172 1173 return ret; 1174 } 1175 1176 static void rz_ssi_remove(struct platform_device *pdev) 1177 { 1178 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1179 1180 rz_ssi_release_dma_channels(ssi); 1181 1182 pm_runtime_put(ssi->dev); 1183 pm_runtime_disable(ssi->dev); 1184 reset_control_assert(ssi->rstc); 1185 } 1186 1187 static const struct of_device_id rz_ssi_of_match[] = { 1188 { .compatible = "renesas,rz-ssi", }, 1189 {/* Sentinel */}, 1190 }; 1191 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1192 1193 static struct platform_driver rz_ssi_driver = { 1194 .driver = { 1195 .name = "rz-ssi-pcm-audio", 1196 .of_match_table = rz_ssi_of_match, 1197 }, 1198 .probe = rz_ssi_probe, 1199 .remove = rz_ssi_remove, 1200 }; 1201 1202 module_platform_driver(rz_ssi_driver); 1203 1204 MODULE_LICENSE("GPL v2"); 1205 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1206 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1207