1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/soc.h> 17 18 /* REGISTER OFFSET */ 19 #define SSICR 0x000 20 #define SSISR 0x004 21 #define SSIFCR 0x010 22 #define SSIFSR 0x014 23 #define SSIFTDR 0x018 24 #define SSIFRDR 0x01c 25 #define SSIOFR 0x020 26 #define SSISCR 0x024 27 28 /* SSI REGISTER BITS */ 29 #define SSICR_DWL(x) (((x) & 0x7) << 19) 30 #define SSICR_SWL(x) (((x) & 0x7) << 16) 31 32 #define SSICR_CKS BIT(30) 33 #define SSICR_TUIEN BIT(29) 34 #define SSICR_TOIEN BIT(28) 35 #define SSICR_RUIEN BIT(27) 36 #define SSICR_ROIEN BIT(26) 37 #define SSICR_MST BIT(14) 38 #define SSICR_BCKP BIT(13) 39 #define SSICR_LRCKP BIT(12) 40 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 41 #define SSICR_TEN BIT(1) 42 #define SSICR_REN BIT(0) 43 44 #define SSISR_TUIRQ BIT(29) 45 #define SSISR_TOIRQ BIT(28) 46 #define SSISR_RUIRQ BIT(27) 47 #define SSISR_ROIRQ BIT(26) 48 #define SSISR_IIRQ BIT(25) 49 50 #define SSIFCR_AUCKE BIT(31) 51 #define SSIFCR_SSIRST BIT(16) 52 #define SSIFCR_TIE BIT(3) 53 #define SSIFCR_RIE BIT(2) 54 #define SSIFCR_TFRST BIT(1) 55 #define SSIFCR_RFRST BIT(0) 56 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 57 58 #define SSIFSR_TDC_MASK 0x3f 59 #define SSIFSR_TDC_SHIFT 24 60 #define SSIFSR_RDC_MASK 0x3f 61 #define SSIFSR_RDC_SHIFT 8 62 63 #define SSIFSR_TDE BIT(16) 64 #define SSIFSR_RDF BIT(0) 65 66 #define SSIOFR_LRCONT BIT(8) 67 68 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 69 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 70 71 /* Pre allocated buffers sizes */ 72 #define PREALLOC_BUFFER (SZ_32K) 73 #define PREALLOC_BUFFER_MAX (SZ_32K) 74 75 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 76 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 77 #define SSI_CHAN_MIN 2 78 #define SSI_CHAN_MAX 2 79 #define SSI_FIFO_DEPTH 32 80 81 struct rz_ssi_priv; 82 83 struct rz_ssi_stream { 84 struct rz_ssi_priv *priv; 85 struct snd_pcm_substream *substream; 86 int fifo_sample_size; /* sample capacity of SSI FIFO */ 87 int dma_buffer_pos; /* The address for the next DMA descriptor */ 88 int period_counter; /* for keeping track of periods transferred */ 89 int sample_width; 90 int buffer_pos; /* current frame position in the buffer */ 91 int running; /* 0=stopped, 1=running */ 92 93 int uerr_num; 94 int oerr_num; 95 96 struct dma_chan *dma_ch; 97 98 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 99 }; 100 101 struct rz_ssi_priv { 102 void __iomem *base; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 /* Full duplex communication support */ 136 struct { 137 unsigned int rate; 138 unsigned int channels; 139 unsigned int sample_width; 140 unsigned int sample_bits; 141 } hw_params_cache; 142 }; 143 144 static void rz_ssi_dma_complete(void *data); 145 146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 147 { 148 writel(data, (priv->base + reg)); 149 } 150 151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 152 { 153 return readl(priv->base + reg); 154 } 155 156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 157 u32 bclr, u32 bset) 158 { 159 u32 val; 160 161 val = readl(priv->base + reg); 162 val = (val & ~bclr) | bset; 163 writel(val, (priv->base + reg)); 164 } 165 166 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream) 167 { 168 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 169 } 170 171 static inline struct rz_ssi_stream * 172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 173 { 174 struct rz_ssi_stream *stream = &ssi->playback; 175 176 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 177 stream = &ssi->capture; 178 179 return stream; 180 } 181 182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 183 { 184 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 185 } 186 187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 188 struct snd_pcm_substream *substream) 189 { 190 struct rz_ssi_priv *ssi = strm->priv; 191 unsigned long flags; 192 193 spin_lock_irqsave(&ssi->lock, flags); 194 strm->substream = substream; 195 spin_unlock_irqrestore(&ssi->lock, flags); 196 } 197 198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 199 struct rz_ssi_stream *strm) 200 { 201 unsigned long flags; 202 bool ret; 203 204 spin_lock_irqsave(&ssi->lock, flags); 205 ret = strm->substream && strm->substream->runtime; 206 spin_unlock_irqrestore(&ssi->lock, flags); 207 208 return ret; 209 } 210 211 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 212 { 213 return strm->substream && strm->running; 214 } 215 216 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 217 struct snd_pcm_substream *substream) 218 { 219 struct snd_pcm_runtime *runtime = substream->runtime; 220 221 rz_ssi_set_substream(strm, substream); 222 strm->sample_width = samples_to_bytes(runtime, 1); 223 strm->dma_buffer_pos = 0; 224 strm->period_counter = 0; 225 strm->buffer_pos = 0; 226 227 strm->oerr_num = 0; 228 strm->uerr_num = 0; 229 strm->running = 0; 230 231 /* fifo init */ 232 strm->fifo_sample_size = SSI_FIFO_DEPTH; 233 } 234 235 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 236 struct rz_ssi_stream *strm) 237 { 238 struct device *dev = ssi->dev; 239 240 rz_ssi_set_substream(strm, NULL); 241 242 if (strm->oerr_num > 0) 243 dev_info(dev, "overrun = %d\n", strm->oerr_num); 244 245 if (strm->uerr_num > 0) 246 dev_info(dev, "underrun = %d\n", strm->uerr_num); 247 } 248 249 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 250 unsigned int channels) 251 { 252 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 253 unsigned int channel_bits = 32; /* System Word Length */ 254 unsigned long bclk_rate = rate * channels * channel_bits; 255 unsigned int div; 256 unsigned int i; 257 u32 ssicr = 0; 258 u32 clk_ckdv; 259 260 /* Clear AUCKE so we can set MST */ 261 rz_ssi_reg_writel(ssi, SSIFCR, 0); 262 263 /* Continue to output LRCK pin even when idle */ 264 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 265 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 266 if (ssi->audio_clk_1 % bclk_rate) 267 ssi->audio_mck = ssi->audio_clk_2; 268 else 269 ssi->audio_mck = ssi->audio_clk_1; 270 } 271 272 /* Clock setting */ 273 ssicr |= SSICR_MST; 274 if (ssi->audio_mck == ssi->audio_clk_1) 275 ssicr |= SSICR_CKS; 276 if (ssi->bckp_rise) 277 ssicr |= SSICR_BCKP; 278 if (ssi->lrckp_fsync_fall) 279 ssicr |= SSICR_LRCKP; 280 281 /* Determine the clock divider */ 282 clk_ckdv = 0; 283 div = ssi->audio_mck / bclk_rate; 284 /* try to find an match */ 285 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 286 if (ckdv[i] == div) { 287 clk_ckdv = i; 288 break; 289 } 290 } 291 292 if (i == ARRAY_SIZE(ckdv)) { 293 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 294 return -EINVAL; 295 } 296 297 /* 298 * DWL: Data Word Length = 16 bits 299 * SWL: System Word Length = 32 bits 300 */ 301 ssicr |= SSICR_CKDV(clk_ckdv); 302 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 303 rz_ssi_reg_writel(ssi, SSICR, ssicr); 304 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 305 306 return 0; 307 } 308 309 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 310 { 311 u32 tmp; 312 int ret; 313 314 /* Disable irqs */ 315 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 316 SSICR_RUIEN | SSICR_ROIEN, 0); 317 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 318 319 /* Clear all error flags */ 320 rz_ssi_reg_mask_setl(ssi, SSISR, 321 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 322 SSISR_RUIRQ), 0); 323 324 /* Wait for idle */ 325 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100); 326 if (ret) 327 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n"); 328 329 /* Hold FIFOs in reset */ 330 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 331 } 332 333 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 334 { 335 bool is_play = rz_ssi_stream_is_play(strm->substream); 336 bool is_full_duplex; 337 u32 ssicr, ssifcr; 338 339 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 340 rz_ssi_is_stream_running(&ssi->capture); 341 ssicr = rz_ssi_reg_readl(ssi, SSICR); 342 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 343 if (!is_full_duplex) { 344 ssifcr &= ~0xF; 345 } else { 346 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 347 rz_ssi_set_idle(ssi); 348 ssifcr &= ~SSIFCR_FIFO_RST; 349 } 350 351 /* FIFO interrupt thresholds */ 352 if (rz_ssi_is_dma_enabled(ssi)) 353 rz_ssi_reg_writel(ssi, SSISCR, 0); 354 else 355 rz_ssi_reg_writel(ssi, SSISCR, 356 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 357 SSISCR_RDFS(0)); 358 359 /* enable IRQ */ 360 if (is_play) { 361 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 362 ssifcr |= SSIFCR_TIE; 363 if (!is_full_duplex) 364 ssifcr |= SSIFCR_RFRST; 365 } else { 366 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 367 ssifcr |= SSIFCR_RIE; 368 if (!is_full_duplex) 369 ssifcr |= SSIFCR_TFRST; 370 } 371 372 rz_ssi_reg_writel(ssi, SSICR, ssicr); 373 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 374 375 /* Clear all error flags */ 376 rz_ssi_reg_mask_setl(ssi, SSISR, 377 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 378 SSISR_RUIRQ), 0); 379 380 strm->running = 1; 381 if (is_full_duplex) 382 ssicr |= SSICR_TEN | SSICR_REN; 383 else 384 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 385 386 rz_ssi_reg_writel(ssi, SSICR, ssicr); 387 388 return 0; 389 } 390 391 static int rz_ssi_swreset(struct rz_ssi_priv *ssi) 392 { 393 u32 tmp; 394 395 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 396 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 397 return readl_poll_timeout_atomic(ssi->base + SSIFCR, tmp, !(tmp & SSIFCR_SSIRST), 1, 5); 398 } 399 400 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 401 { 402 strm->running = 0; 403 404 if (rz_ssi_is_stream_running(&ssi->playback) || 405 rz_ssi_is_stream_running(&ssi->capture)) 406 return 0; 407 408 /* Disable TX/RX */ 409 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 410 411 /* Cancel all remaining DMA transactions */ 412 if (rz_ssi_is_dma_enabled(ssi)) { 413 if (ssi->playback.dma_ch) 414 dmaengine_terminate_async(ssi->playback.dma_ch); 415 if (ssi->capture.dma_ch) 416 dmaengine_terminate_async(ssi->capture.dma_ch); 417 } 418 419 rz_ssi_set_idle(ssi); 420 421 return 0; 422 } 423 424 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 425 { 426 struct snd_pcm_substream *substream = strm->substream; 427 struct snd_pcm_runtime *runtime; 428 int current_period; 429 430 if (!strm->running || !substream || !substream->runtime) 431 return; 432 433 runtime = substream->runtime; 434 strm->buffer_pos += frames; 435 WARN_ON(strm->buffer_pos > runtime->buffer_size); 436 437 /* ring buffer */ 438 if (strm->buffer_pos == runtime->buffer_size) 439 strm->buffer_pos = 0; 440 441 current_period = strm->buffer_pos / runtime->period_size; 442 if (strm->period_counter != current_period) { 443 snd_pcm_period_elapsed(strm->substream); 444 strm->period_counter = current_period; 445 } 446 } 447 448 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 449 { 450 struct snd_pcm_substream *substream = strm->substream; 451 struct snd_pcm_runtime *runtime; 452 u16 *buf; 453 int fifo_samples; 454 int frames_left; 455 int samples; 456 int i; 457 458 if (!rz_ssi_stream_is_valid(ssi, strm)) 459 return -EINVAL; 460 461 runtime = substream->runtime; 462 463 do { 464 /* frames left in this period */ 465 frames_left = runtime->period_size - 466 (strm->buffer_pos % runtime->period_size); 467 if (!frames_left) 468 frames_left = runtime->period_size; 469 470 /* Samples in RX FIFO */ 471 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 472 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 473 474 /* Only read full frames at a time */ 475 samples = 0; 476 while (frames_left && (fifo_samples >= runtime->channels)) { 477 samples += runtime->channels; 478 fifo_samples -= runtime->channels; 479 frames_left--; 480 } 481 482 /* not enough samples yet */ 483 if (!samples) 484 break; 485 486 /* calculate new buffer index */ 487 buf = (u16 *)runtime->dma_area; 488 buf += strm->buffer_pos * runtime->channels; 489 490 /* Note, only supports 16-bit samples */ 491 for (i = 0; i < samples; i++) 492 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 493 494 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 495 rz_ssi_pointer_update(strm, samples / runtime->channels); 496 } while (!frames_left && fifo_samples >= runtime->channels); 497 498 return 0; 499 } 500 501 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 502 { 503 struct snd_pcm_substream *substream = strm->substream; 504 struct snd_pcm_runtime *runtime = substream->runtime; 505 int sample_space; 506 int samples = 0; 507 int frames_left; 508 int i; 509 u32 ssifsr; 510 u16 *buf; 511 512 if (!rz_ssi_stream_is_valid(ssi, strm)) 513 return -EINVAL; 514 515 /* frames left in this period */ 516 frames_left = runtime->period_size - (strm->buffer_pos % 517 runtime->period_size); 518 if (frames_left == 0) 519 frames_left = runtime->period_size; 520 521 sample_space = strm->fifo_sample_size; 522 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 523 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 524 if (sample_space < 0) 525 return -EINVAL; 526 527 /* Only add full frames at a time */ 528 while (frames_left && (sample_space >= runtime->channels)) { 529 samples += runtime->channels; 530 sample_space -= runtime->channels; 531 frames_left--; 532 } 533 534 /* no space to send anything right now */ 535 if (samples == 0) 536 return 0; 537 538 /* calculate new buffer index */ 539 buf = (u16 *)(runtime->dma_area); 540 buf += strm->buffer_pos * runtime->channels; 541 542 /* Note, only supports 16-bit samples */ 543 for (i = 0; i < samples; i++) 544 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 545 546 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 547 rz_ssi_pointer_update(strm, samples / runtime->channels); 548 549 return 0; 550 } 551 552 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 553 { 554 struct rz_ssi_stream *strm_playback = NULL; 555 struct rz_ssi_stream *strm_capture = NULL; 556 struct rz_ssi_priv *ssi = data; 557 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 558 559 if (ssi->playback.substream) 560 strm_playback = &ssi->playback; 561 if (ssi->capture.substream) 562 strm_capture = &ssi->capture; 563 564 if (!strm_playback && !strm_capture) 565 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 566 567 if (irq == ssi->irq_int) { /* error or idle */ 568 bool is_stopped = false; 569 int i, count; 570 571 if (rz_ssi_is_dma_enabled(ssi)) 572 count = 4; 573 else 574 count = 1; 575 576 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 577 is_stopped = true; 578 579 if (ssi->capture.substream && is_stopped) { 580 if (ssisr & SSISR_RUIRQ) 581 strm_capture->uerr_num++; 582 if (ssisr & SSISR_ROIRQ) 583 strm_capture->oerr_num++; 584 585 rz_ssi_stop(ssi, strm_capture); 586 } 587 588 if (ssi->playback.substream && is_stopped) { 589 if (ssisr & SSISR_TUIRQ) 590 strm_playback->uerr_num++; 591 if (ssisr & SSISR_TOIRQ) 592 strm_playback->oerr_num++; 593 594 rz_ssi_stop(ssi, strm_playback); 595 } 596 597 /* Clear all flags */ 598 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 599 SSISR_ROIRQ | SSISR_RUIRQ, 0); 600 601 /* Add/remove more data */ 602 if (ssi->capture.substream && is_stopped) { 603 for (i = 0; i < count; i++) 604 strm_capture->transfer(ssi, strm_capture); 605 } 606 607 if (ssi->playback.substream && is_stopped) { 608 for (i = 0; i < count; i++) 609 strm_playback->transfer(ssi, strm_playback); 610 } 611 612 /* Resume */ 613 if (ssi->playback.substream && is_stopped) 614 rz_ssi_start(ssi, &ssi->playback); 615 if (ssi->capture.substream && is_stopped) 616 rz_ssi_start(ssi, &ssi->capture); 617 } 618 619 if (!rz_ssi_is_stream_running(&ssi->playback) && 620 !rz_ssi_is_stream_running(&ssi->capture)) 621 return IRQ_HANDLED; 622 623 /* tx data empty */ 624 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 625 strm_playback->transfer(ssi, &ssi->playback); 626 627 /* rx data full */ 628 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 629 strm_capture->transfer(ssi, &ssi->capture); 630 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 631 } 632 633 if (irq == ssi->irq_rt) { 634 if (ssi->playback.substream) { 635 strm_playback->transfer(ssi, &ssi->playback); 636 } else { 637 strm_capture->transfer(ssi, &ssi->capture); 638 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 639 } 640 } 641 642 return IRQ_HANDLED; 643 } 644 645 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 646 struct dma_chan *dma_ch, bool is_play) 647 { 648 struct dma_slave_config cfg; 649 650 memset(&cfg, 0, sizeof(cfg)); 651 652 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 653 cfg.dst_addr = ssi->phys + SSIFTDR; 654 cfg.src_addr = ssi->phys + SSIFRDR; 655 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 656 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 657 658 return dmaengine_slave_config(dma_ch, &cfg); 659 } 660 661 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 662 struct rz_ssi_stream *strm) 663 { 664 struct snd_pcm_substream *substream = strm->substream; 665 struct dma_async_tx_descriptor *desc; 666 struct snd_pcm_runtime *runtime; 667 enum dma_transfer_direction dir; 668 u32 dma_paddr, dma_size; 669 int amount; 670 671 if (!rz_ssi_stream_is_valid(ssi, strm)) 672 return -EINVAL; 673 674 runtime = substream->runtime; 675 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 676 /* 677 * Stream is ending, so do not queue up any more DMA 678 * transfers otherwise we play partial sound clips 679 * because we can't shut off the DMA quick enough. 680 */ 681 return 0; 682 683 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 684 685 /* Always transfer 1 period */ 686 amount = runtime->period_size; 687 688 /* DMA physical address and size */ 689 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 690 strm->dma_buffer_pos); 691 dma_size = frames_to_bytes(runtime, amount); 692 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 693 dir, 694 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 695 if (!desc) { 696 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 697 return -ENOMEM; 698 } 699 700 desc->callback = rz_ssi_dma_complete; 701 desc->callback_param = strm; 702 703 if (dmaengine_submit(desc) < 0) { 704 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 705 return -EIO; 706 } 707 708 /* Update DMA pointer */ 709 strm->dma_buffer_pos += amount; 710 if (strm->dma_buffer_pos >= runtime->buffer_size) 711 strm->dma_buffer_pos = 0; 712 713 /* Start DMA */ 714 dma_async_issue_pending(strm->dma_ch); 715 716 return 0; 717 } 718 719 static void rz_ssi_dma_complete(void *data) 720 { 721 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 722 723 if (!strm->running || !strm->substream || !strm->substream->runtime) 724 return; 725 726 /* Note that next DMA transaction has probably already started */ 727 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 728 729 /* Queue up another DMA transaction */ 730 rz_ssi_dma_transfer(strm->priv, strm); 731 } 732 733 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 734 { 735 if (ssi->playback.dma_ch) { 736 dma_release_channel(ssi->playback.dma_ch); 737 ssi->playback.dma_ch = NULL; 738 if (ssi->dma_rt) 739 ssi->dma_rt = false; 740 } 741 742 if (ssi->capture.dma_ch) { 743 dma_release_channel(ssi->capture.dma_ch); 744 ssi->capture.dma_ch = NULL; 745 } 746 } 747 748 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 749 { 750 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 751 if (IS_ERR(ssi->playback.dma_ch)) 752 ssi->playback.dma_ch = NULL; 753 754 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 755 if (IS_ERR(ssi->capture.dma_ch)) 756 ssi->capture.dma_ch = NULL; 757 758 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 759 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 760 if (IS_ERR(ssi->playback.dma_ch)) { 761 ssi->playback.dma_ch = NULL; 762 goto no_dma; 763 } 764 765 ssi->dma_rt = true; 766 } 767 768 if (!rz_ssi_is_dma_enabled(ssi)) 769 goto no_dma; 770 771 if (ssi->playback.dma_ch && 772 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 773 goto no_dma; 774 775 if (ssi->capture.dma_ch && 776 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 777 goto no_dma; 778 779 return 0; 780 781 no_dma: 782 rz_ssi_release_dma_channels(ssi); 783 784 return -ENODEV; 785 } 786 787 static int rz_ssi_trigger_resume(struct rz_ssi_priv *ssi) 788 { 789 int ret; 790 791 if (rz_ssi_is_stream_running(&ssi->playback) || 792 rz_ssi_is_stream_running(&ssi->capture)) 793 return 0; 794 795 ret = rz_ssi_swreset(ssi); 796 if (ret) 797 return ret; 798 799 return rz_ssi_clk_setup(ssi, ssi->hw_params_cache.rate, 800 ssi->hw_params_cache.channels); 801 } 802 803 static void rz_ssi_streams_suspend(struct rz_ssi_priv *ssi) 804 { 805 if (rz_ssi_is_stream_running(&ssi->playback) || 806 rz_ssi_is_stream_running(&ssi->capture)) 807 return; 808 809 ssi->playback.dma_buffer_pos = 0; 810 ssi->capture.dma_buffer_pos = 0; 811 } 812 813 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 814 struct snd_soc_dai *dai) 815 { 816 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 817 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 818 int ret = 0, i, num_transfer = 1; 819 820 switch (cmd) { 821 case SNDRV_PCM_TRIGGER_RESUME: 822 ret = rz_ssi_trigger_resume(ssi); 823 if (ret) 824 return ret; 825 826 fallthrough; 827 828 case SNDRV_PCM_TRIGGER_START: 829 if (cmd == SNDRV_PCM_TRIGGER_START) 830 rz_ssi_stream_init(strm, substream); 831 832 if (ssi->dma_rt) { 833 bool is_playback; 834 835 is_playback = rz_ssi_stream_is_play(substream); 836 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 837 is_playback); 838 /* Fallback to pio */ 839 if (ret < 0) { 840 ssi->playback.transfer = rz_ssi_pio_send; 841 ssi->capture.transfer = rz_ssi_pio_recv; 842 rz_ssi_release_dma_channels(ssi); 843 } 844 } 845 846 /* For DMA, queue up multiple DMA descriptors */ 847 if (rz_ssi_is_dma_enabled(ssi)) 848 num_transfer = 4; 849 850 for (i = 0; i < num_transfer; i++) { 851 ret = strm->transfer(ssi, strm); 852 if (ret) 853 goto done; 854 } 855 856 ret = rz_ssi_start(ssi, strm); 857 break; 858 859 case SNDRV_PCM_TRIGGER_SUSPEND: 860 rz_ssi_stop(ssi, strm); 861 rz_ssi_streams_suspend(ssi); 862 break; 863 864 case SNDRV_PCM_TRIGGER_STOP: 865 rz_ssi_stop(ssi, strm); 866 rz_ssi_stream_quit(ssi, strm); 867 break; 868 } 869 870 done: 871 return ret; 872 } 873 874 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 875 { 876 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 877 878 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 879 case SND_SOC_DAIFMT_BP_FP: 880 break; 881 default: 882 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 883 return -EINVAL; 884 } 885 886 /* 887 * set clock polarity 888 * 889 * "normal" BCLK = Signal is available at rising edge of BCLK 890 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 891 */ 892 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 893 case SND_SOC_DAIFMT_NB_NF: 894 ssi->bckp_rise = false; 895 ssi->lrckp_fsync_fall = false; 896 break; 897 case SND_SOC_DAIFMT_NB_IF: 898 ssi->bckp_rise = false; 899 ssi->lrckp_fsync_fall = true; 900 break; 901 case SND_SOC_DAIFMT_IB_NF: 902 ssi->bckp_rise = true; 903 ssi->lrckp_fsync_fall = false; 904 break; 905 case SND_SOC_DAIFMT_IB_IF: 906 ssi->bckp_rise = true; 907 ssi->lrckp_fsync_fall = true; 908 break; 909 default: 910 return -EINVAL; 911 } 912 913 /* only i2s support */ 914 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 915 case SND_SOC_DAIFMT_I2S: 916 break; 917 default: 918 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 919 return -EINVAL; 920 } 921 922 return 0; 923 } 924 925 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 926 unsigned int channels, 927 unsigned int sample_width, 928 unsigned int sample_bits) 929 { 930 if (ssi->hw_params_cache.rate != rate || 931 ssi->hw_params_cache.channels != channels || 932 ssi->hw_params_cache.sample_width != sample_width || 933 ssi->hw_params_cache.sample_bits != sample_bits) 934 return false; 935 936 return true; 937 } 938 939 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 940 unsigned int channels, 941 unsigned int sample_width, 942 unsigned int sample_bits) 943 { 944 ssi->hw_params_cache.rate = rate; 945 ssi->hw_params_cache.channels = channels; 946 ssi->hw_params_cache.sample_width = sample_width; 947 ssi->hw_params_cache.sample_bits = sample_bits; 948 } 949 950 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 951 struct snd_pcm_hw_params *params, 952 struct snd_soc_dai *dai) 953 { 954 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 955 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 956 unsigned int sample_bits = hw_param_interval(params, 957 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 958 unsigned int channels = params_channels(params); 959 unsigned int rate = params_rate(params); 960 int ret; 961 962 if (sample_bits != 16) { 963 dev_err(ssi->dev, "Unsupported sample width: %d\n", 964 sample_bits); 965 return -EINVAL; 966 } 967 968 if (channels != 2) { 969 dev_err(ssi->dev, "Number of channels not matched: %d\n", 970 channels); 971 return -EINVAL; 972 } 973 974 if (rz_ssi_is_stream_running(&ssi->playback) || 975 rz_ssi_is_stream_running(&ssi->capture)) { 976 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 977 strm->sample_width, sample_bits)) 978 return 0; 979 980 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 981 return -EINVAL; 982 } 983 984 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 985 sample_bits); 986 987 ret = rz_ssi_swreset(ssi); 988 if (ret) 989 return ret; 990 991 return rz_ssi_clk_setup(ssi, rate, channels); 992 } 993 994 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 995 .trigger = rz_ssi_dai_trigger, 996 .set_fmt = rz_ssi_dai_set_fmt, 997 .hw_params = rz_ssi_dai_hw_params, 998 }; 999 1000 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 1001 .info = SNDRV_PCM_INFO_INTERLEAVED | 1002 SNDRV_PCM_INFO_MMAP | 1003 SNDRV_PCM_INFO_MMAP_VALID | 1004 SNDRV_PCM_INFO_RESUME, 1005 .buffer_bytes_max = PREALLOC_BUFFER, 1006 .period_bytes_min = 32, 1007 .period_bytes_max = 8192, 1008 .channels_min = SSI_CHAN_MIN, 1009 .channels_max = SSI_CHAN_MAX, 1010 .periods_min = 1, 1011 .periods_max = 32, 1012 .fifo_size = 32 * 2, 1013 }; 1014 1015 static int rz_ssi_pcm_open(struct snd_soc_component *component, 1016 struct snd_pcm_substream *substream) 1017 { 1018 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 1019 1020 return snd_pcm_hw_constraint_integer(substream->runtime, 1021 SNDRV_PCM_HW_PARAM_PERIODS); 1022 } 1023 1024 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 1025 struct snd_pcm_substream *substream) 1026 { 1027 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 1028 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 1029 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 1030 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 1031 1032 return strm->buffer_pos; 1033 } 1034 1035 static int rz_ssi_pcm_new(struct snd_soc_component *component, 1036 struct snd_soc_pcm_runtime *rtd) 1037 { 1038 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 1039 rtd->card->snd_card->dev, 1040 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1041 return 0; 1042 } 1043 1044 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1045 { 1046 .name = "rz-ssi-dai", 1047 .playback = { 1048 .rates = SSI_RATES, 1049 .formats = SSI_FMTS, 1050 .channels_min = SSI_CHAN_MIN, 1051 .channels_max = SSI_CHAN_MAX, 1052 }, 1053 .capture = { 1054 .rates = SSI_RATES, 1055 .formats = SSI_FMTS, 1056 .channels_min = SSI_CHAN_MIN, 1057 .channels_max = SSI_CHAN_MAX, 1058 }, 1059 .ops = &rz_ssi_dai_ops, 1060 }, 1061 }; 1062 1063 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1064 .name = "rz-ssi", 1065 .open = rz_ssi_pcm_open, 1066 .pointer = rz_ssi_pcm_pointer, 1067 .pcm_construct = rz_ssi_pcm_new, 1068 .legacy_dai_naming = 1, 1069 }; 1070 1071 static int rz_ssi_probe(struct platform_device *pdev) 1072 { 1073 struct device *dev = &pdev->dev; 1074 struct rz_ssi_priv *ssi; 1075 struct clk *audio_clk; 1076 struct resource *res; 1077 int ret; 1078 1079 ssi = devm_kzalloc(dev, sizeof(*ssi), GFP_KERNEL); 1080 if (!ssi) 1081 return -ENOMEM; 1082 1083 ssi->dev = dev; 1084 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1085 if (IS_ERR(ssi->base)) 1086 return PTR_ERR(ssi->base); 1087 1088 ssi->phys = res->start; 1089 ssi->clk = devm_clk_get(dev, "ssi"); 1090 if (IS_ERR(ssi->clk)) 1091 return PTR_ERR(ssi->clk); 1092 1093 ssi->sfr_clk = devm_clk_get(dev, "ssi_sfr"); 1094 if (IS_ERR(ssi->sfr_clk)) 1095 return PTR_ERR(ssi->sfr_clk); 1096 1097 audio_clk = devm_clk_get(dev, "audio_clk1"); 1098 if (IS_ERR(audio_clk)) 1099 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1100 "no audio clk1"); 1101 1102 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1103 audio_clk = devm_clk_get(dev, "audio_clk2"); 1104 if (IS_ERR(audio_clk)) 1105 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1106 "no audio clk2"); 1107 1108 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1109 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1110 return dev_err_probe(&pdev->dev, -EINVAL, 1111 "no audio clk1 or audio clk2"); 1112 1113 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1114 1115 /* Detect DMA support */ 1116 ret = rz_ssi_dma_request(ssi, dev); 1117 if (ret < 0) { 1118 dev_warn(dev, "DMA not available, using PIO\n"); 1119 ssi->playback.transfer = rz_ssi_pio_send; 1120 ssi->capture.transfer = rz_ssi_pio_recv; 1121 } else { 1122 dev_info(dev, "DMA enabled"); 1123 ssi->playback.transfer = rz_ssi_dma_transfer; 1124 ssi->capture.transfer = rz_ssi_dma_transfer; 1125 } 1126 1127 ssi->playback.priv = ssi; 1128 ssi->capture.priv = ssi; 1129 1130 spin_lock_init(&ssi->lock); 1131 dev_set_drvdata(dev, ssi); 1132 1133 /* Error Interrupt */ 1134 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1135 if (ssi->irq_int < 0) { 1136 ret = ssi->irq_int; 1137 goto err_release_dma_chs; 1138 } 1139 1140 ret = devm_request_irq(dev, ssi->irq_int, &rz_ssi_interrupt, 1141 0, dev_name(dev), ssi); 1142 if (ret < 0) { 1143 dev_err_probe(dev, ret, "irq request error (int_req)\n"); 1144 goto err_release_dma_chs; 1145 } 1146 1147 if (!rz_ssi_is_dma_enabled(ssi)) { 1148 /* Tx and Rx interrupts (pio only) */ 1149 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1150 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1151 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1152 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1153 if (ssi->irq_rt < 0) 1154 return ssi->irq_rt; 1155 1156 ret = devm_request_irq(dev, ssi->irq_rt, 1157 &rz_ssi_interrupt, 0, 1158 dev_name(dev), ssi); 1159 if (ret < 0) 1160 return dev_err_probe(dev, ret, 1161 "irq request error (dma_rt)\n"); 1162 } else { 1163 if (ssi->irq_tx < 0) 1164 return ssi->irq_tx; 1165 1166 if (ssi->irq_rx < 0) 1167 return ssi->irq_rx; 1168 1169 ret = devm_request_irq(dev, ssi->irq_tx, 1170 &rz_ssi_interrupt, 0, 1171 dev_name(dev), ssi); 1172 if (ret < 0) 1173 return dev_err_probe(dev, ret, 1174 "irq request error (dma_tx)\n"); 1175 1176 ret = devm_request_irq(dev, ssi->irq_rx, 1177 &rz_ssi_interrupt, 0, 1178 dev_name(dev), ssi); 1179 if (ret < 0) 1180 return dev_err_probe(dev, ret, 1181 "irq request error (dma_rx)\n"); 1182 } 1183 } 1184 1185 ssi->rstc = devm_reset_control_get_exclusive(dev, NULL); 1186 if (IS_ERR(ssi->rstc)) { 1187 ret = PTR_ERR(ssi->rstc); 1188 goto err_release_dma_chs; 1189 } 1190 1191 /* Default 0 for power saving. Can be overridden via sysfs. */ 1192 pm_runtime_set_autosuspend_delay(dev, 0); 1193 pm_runtime_use_autosuspend(dev); 1194 ret = devm_pm_runtime_enable(dev); 1195 if (ret < 0) { 1196 dev_err(dev, "Failed to enable runtime PM!\n"); 1197 goto err_release_dma_chs; 1198 } 1199 1200 ret = devm_snd_soc_register_component(dev, &rz_ssi_soc_component, 1201 rz_ssi_soc_dai, 1202 ARRAY_SIZE(rz_ssi_soc_dai)); 1203 if (ret < 0) { 1204 dev_err(dev, "failed to register snd component\n"); 1205 goto err_release_dma_chs; 1206 } 1207 1208 return 0; 1209 1210 err_release_dma_chs: 1211 rz_ssi_release_dma_channels(ssi); 1212 1213 return ret; 1214 } 1215 1216 static void rz_ssi_remove(struct platform_device *pdev) 1217 { 1218 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1219 1220 rz_ssi_release_dma_channels(ssi); 1221 1222 reset_control_assert(ssi->rstc); 1223 } 1224 1225 static const struct of_device_id rz_ssi_of_match[] = { 1226 { .compatible = "renesas,rz-ssi", }, 1227 {/* Sentinel */}, 1228 }; 1229 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1230 1231 static int rz_ssi_runtime_suspend(struct device *dev) 1232 { 1233 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1234 1235 return reset_control_assert(ssi->rstc); 1236 } 1237 1238 static int rz_ssi_runtime_resume(struct device *dev) 1239 { 1240 struct rz_ssi_priv *ssi = dev_get_drvdata(dev); 1241 1242 return reset_control_deassert(ssi->rstc); 1243 } 1244 1245 static const struct dev_pm_ops rz_ssi_pm_ops = { 1246 RUNTIME_PM_OPS(rz_ssi_runtime_suspend, rz_ssi_runtime_resume, NULL) 1247 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1248 }; 1249 1250 static struct platform_driver rz_ssi_driver = { 1251 .driver = { 1252 .name = "rz-ssi-pcm-audio", 1253 .of_match_table = rz_ssi_of_match, 1254 .pm = pm_ptr(&rz_ssi_pm_ops), 1255 }, 1256 .probe = rz_ssi_probe, 1257 .remove = rz_ssi_remove, 1258 }; 1259 1260 module_platform_driver(rz_ssi_driver); 1261 1262 MODULE_LICENSE("GPL v2"); 1263 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1264 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1265