1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 #include <sound/soc.h> 16 17 /* REGISTER OFFSET */ 18 #define SSICR 0x000 19 #define SSISR 0x004 20 #define SSIFCR 0x010 21 #define SSIFSR 0x014 22 #define SSIFTDR 0x018 23 #define SSIFRDR 0x01c 24 #define SSIOFR 0x020 25 #define SSISCR 0x024 26 27 /* SSI REGISTER BITS */ 28 #define SSICR_DWL(x) (((x) & 0x7) << 19) 29 #define SSICR_SWL(x) (((x) & 0x7) << 16) 30 31 #define SSICR_CKS BIT(30) 32 #define SSICR_TUIEN BIT(29) 33 #define SSICR_TOIEN BIT(28) 34 #define SSICR_RUIEN BIT(27) 35 #define SSICR_ROIEN BIT(26) 36 #define SSICR_MST BIT(14) 37 #define SSICR_BCKP BIT(13) 38 #define SSICR_LRCKP BIT(12) 39 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 40 #define SSICR_TEN BIT(1) 41 #define SSICR_REN BIT(0) 42 43 #define SSISR_TUIRQ BIT(29) 44 #define SSISR_TOIRQ BIT(28) 45 #define SSISR_RUIRQ BIT(27) 46 #define SSISR_ROIRQ BIT(26) 47 #define SSISR_IIRQ BIT(25) 48 49 #define SSIFCR_AUCKE BIT(31) 50 #define SSIFCR_SSIRST BIT(16) 51 #define SSIFCR_TIE BIT(3) 52 #define SSIFCR_RIE BIT(2) 53 #define SSIFCR_TFRST BIT(1) 54 #define SSIFCR_RFRST BIT(0) 55 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 56 57 #define SSIFSR_TDC_MASK 0x3f 58 #define SSIFSR_TDC_SHIFT 24 59 #define SSIFSR_RDC_MASK 0x3f 60 #define SSIFSR_RDC_SHIFT 8 61 62 #define SSIFSR_TDE BIT(16) 63 #define SSIFSR_RDF BIT(0) 64 65 #define SSIOFR_LRCONT BIT(8) 66 67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 69 70 /* Pre allocated buffers sizes */ 71 #define PREALLOC_BUFFER (SZ_32K) 72 #define PREALLOC_BUFFER_MAX (SZ_32K) 73 74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */ 75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 76 #define SSI_CHAN_MIN 2 77 #define SSI_CHAN_MAX 2 78 #define SSI_FIFO_DEPTH 32 79 80 struct rz_ssi_priv; 81 82 struct rz_ssi_stream { 83 struct rz_ssi_priv *priv; 84 struct snd_pcm_substream *substream; 85 int fifo_sample_size; /* sample capacity of SSI FIFO */ 86 int dma_buffer_pos; /* The address for the next DMA descriptor */ 87 int period_counter; /* for keeping track of periods transferred */ 88 int sample_width; 89 int buffer_pos; /* current frame position in the buffer */ 90 int running; /* 0=stopped, 1=running */ 91 92 int uerr_num; 93 int oerr_num; 94 95 struct dma_chan *dma_ch; 96 97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 98 }; 99 100 struct rz_ssi_priv { 101 void __iomem *base; 102 struct platform_device *pdev; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 /* Full duplex communication support */ 136 struct { 137 unsigned int rate; 138 unsigned int channels; 139 unsigned int sample_width; 140 unsigned int sample_bits; 141 } hw_params_cache; 142 }; 143 144 static void rz_ssi_dma_complete(void *data); 145 146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 147 { 148 writel(data, (priv->base + reg)); 149 } 150 151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 152 { 153 return readl(priv->base + reg); 154 } 155 156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 157 u32 bclr, u32 bset) 158 { 159 u32 val; 160 161 val = readl(priv->base + reg); 162 val = (val & ~bclr) | bset; 163 writel(val, (priv->base + reg)); 164 } 165 166 static inline struct snd_soc_dai * 167 rz_ssi_get_dai(struct snd_pcm_substream *substream) 168 { 169 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 170 171 return snd_soc_rtd_to_cpu(rtd, 0); 172 } 173 174 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi, 175 struct snd_pcm_substream *substream) 176 { 177 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 178 } 179 180 static inline struct rz_ssi_stream * 181 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 182 { 183 struct rz_ssi_stream *stream = &ssi->playback; 184 185 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 186 stream = &ssi->capture; 187 188 return stream; 189 } 190 191 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 192 { 193 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 194 } 195 196 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 197 struct snd_pcm_substream *substream) 198 { 199 struct rz_ssi_priv *ssi = strm->priv; 200 unsigned long flags; 201 202 spin_lock_irqsave(&ssi->lock, flags); 203 strm->substream = substream; 204 spin_unlock_irqrestore(&ssi->lock, flags); 205 } 206 207 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 208 struct rz_ssi_stream *strm) 209 { 210 unsigned long flags; 211 bool ret; 212 213 spin_lock_irqsave(&ssi->lock, flags); 214 ret = strm->substream && strm->substream->runtime; 215 spin_unlock_irqrestore(&ssi->lock, flags); 216 217 return ret; 218 } 219 220 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 221 { 222 return strm->substream && strm->running; 223 } 224 225 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 226 struct snd_pcm_substream *substream) 227 { 228 struct snd_pcm_runtime *runtime = substream->runtime; 229 230 rz_ssi_set_substream(strm, substream); 231 strm->sample_width = samples_to_bytes(runtime, 1); 232 strm->dma_buffer_pos = 0; 233 strm->period_counter = 0; 234 strm->buffer_pos = 0; 235 236 strm->oerr_num = 0; 237 strm->uerr_num = 0; 238 strm->running = 0; 239 240 /* fifo init */ 241 strm->fifo_sample_size = SSI_FIFO_DEPTH; 242 } 243 244 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 245 struct rz_ssi_stream *strm) 246 { 247 struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream); 248 249 rz_ssi_set_substream(strm, NULL); 250 251 if (strm->oerr_num > 0) 252 dev_info(dai->dev, "overrun = %d\n", strm->oerr_num); 253 254 if (strm->uerr_num > 0) 255 dev_info(dai->dev, "underrun = %d\n", strm->uerr_num); 256 } 257 258 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 259 unsigned int channels) 260 { 261 static s8 ckdv[16] = { 1, 2, 4, 8, 16, 32, 64, 128, 262 6, 12, 24, 48, 96, -1, -1, -1 }; 263 unsigned int channel_bits = 32; /* System Word Length */ 264 unsigned long bclk_rate = rate * channels * channel_bits; 265 unsigned int div; 266 unsigned int i; 267 u32 ssicr = 0; 268 u32 clk_ckdv; 269 270 /* Clear AUCKE so we can set MST */ 271 rz_ssi_reg_writel(ssi, SSIFCR, 0); 272 273 /* Continue to output LRCK pin even when idle */ 274 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 275 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 276 if (ssi->audio_clk_1 % bclk_rate) 277 ssi->audio_mck = ssi->audio_clk_2; 278 else 279 ssi->audio_mck = ssi->audio_clk_1; 280 } 281 282 /* Clock setting */ 283 ssicr |= SSICR_MST; 284 if (ssi->audio_mck == ssi->audio_clk_1) 285 ssicr |= SSICR_CKS; 286 if (ssi->bckp_rise) 287 ssicr |= SSICR_BCKP; 288 if (ssi->lrckp_fsync_fall) 289 ssicr |= SSICR_LRCKP; 290 291 /* Determine the clock divider */ 292 clk_ckdv = 0; 293 div = ssi->audio_mck / bclk_rate; 294 /* try to find an match */ 295 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 296 if (ckdv[i] == div) { 297 clk_ckdv = i; 298 break; 299 } 300 } 301 302 if (i == ARRAY_SIZE(ckdv)) { 303 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 304 return -EINVAL; 305 } 306 307 /* 308 * DWL: Data Word Length = 16 bits 309 * SWL: System Word Length = 32 bits 310 */ 311 ssicr |= SSICR_CKDV(clk_ckdv); 312 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 313 rz_ssi_reg_writel(ssi, SSICR, ssicr); 314 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 315 316 return 0; 317 } 318 319 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 320 { 321 int timeout; 322 323 /* Disable irqs */ 324 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 325 SSICR_RUIEN | SSICR_ROIEN, 0); 326 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 327 328 /* Clear all error flags */ 329 rz_ssi_reg_mask_setl(ssi, SSISR, 330 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 331 SSISR_RUIRQ), 0); 332 333 /* Wait for idle */ 334 timeout = 100; 335 while (--timeout) { 336 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ) 337 break; 338 udelay(1); 339 } 340 341 if (!timeout) 342 dev_info(ssi->dev, "timeout waiting for SSI idle\n"); 343 344 /* Hold FIFOs in reset */ 345 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 346 } 347 348 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 349 { 350 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream); 351 bool is_full_duplex; 352 u32 ssicr, ssifcr; 353 354 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 355 rz_ssi_is_stream_running(&ssi->capture); 356 ssicr = rz_ssi_reg_readl(ssi, SSICR); 357 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 358 if (!is_full_duplex) { 359 ssifcr &= ~0xF; 360 } else { 361 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 362 rz_ssi_set_idle(ssi); 363 ssifcr &= ~SSIFCR_FIFO_RST; 364 } 365 366 /* FIFO interrupt thresholds */ 367 if (rz_ssi_is_dma_enabled(ssi)) 368 rz_ssi_reg_writel(ssi, SSISCR, 0); 369 else 370 rz_ssi_reg_writel(ssi, SSISCR, 371 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 372 SSISCR_RDFS(0)); 373 374 /* enable IRQ */ 375 if (is_play) { 376 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 377 ssifcr |= SSIFCR_TIE; 378 if (!is_full_duplex) 379 ssifcr |= SSIFCR_RFRST; 380 } else { 381 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 382 ssifcr |= SSIFCR_RIE; 383 if (!is_full_duplex) 384 ssifcr |= SSIFCR_TFRST; 385 } 386 387 rz_ssi_reg_writel(ssi, SSICR, ssicr); 388 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 389 390 /* Clear all error flags */ 391 rz_ssi_reg_mask_setl(ssi, SSISR, 392 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 393 SSISR_RUIRQ), 0); 394 395 strm->running = 1; 396 if (is_full_duplex) 397 ssicr |= SSICR_TEN | SSICR_REN; 398 else 399 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 400 401 rz_ssi_reg_writel(ssi, SSICR, ssicr); 402 403 return 0; 404 } 405 406 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 407 { 408 strm->running = 0; 409 410 if (rz_ssi_is_stream_running(&ssi->playback) || 411 rz_ssi_is_stream_running(&ssi->capture)) 412 return 0; 413 414 /* Disable TX/RX */ 415 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 416 417 /* Cancel all remaining DMA transactions */ 418 if (rz_ssi_is_dma_enabled(ssi)) 419 dmaengine_terminate_async(strm->dma_ch); 420 421 rz_ssi_set_idle(ssi); 422 423 return 0; 424 } 425 426 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 427 { 428 struct snd_pcm_substream *substream = strm->substream; 429 struct snd_pcm_runtime *runtime; 430 int current_period; 431 432 if (!strm->running || !substream || !substream->runtime) 433 return; 434 435 runtime = substream->runtime; 436 strm->buffer_pos += frames; 437 WARN_ON(strm->buffer_pos > runtime->buffer_size); 438 439 /* ring buffer */ 440 if (strm->buffer_pos == runtime->buffer_size) 441 strm->buffer_pos = 0; 442 443 current_period = strm->buffer_pos / runtime->period_size; 444 if (strm->period_counter != current_period) { 445 snd_pcm_period_elapsed(strm->substream); 446 strm->period_counter = current_period; 447 } 448 } 449 450 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 451 { 452 struct snd_pcm_substream *substream = strm->substream; 453 struct snd_pcm_runtime *runtime; 454 u16 *buf; 455 int fifo_samples; 456 int frames_left; 457 int samples; 458 int i; 459 460 if (!rz_ssi_stream_is_valid(ssi, strm)) 461 return -EINVAL; 462 463 runtime = substream->runtime; 464 465 do { 466 /* frames left in this period */ 467 frames_left = runtime->period_size - 468 (strm->buffer_pos % runtime->period_size); 469 if (!frames_left) 470 frames_left = runtime->period_size; 471 472 /* Samples in RX FIFO */ 473 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 474 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 475 476 /* Only read full frames at a time */ 477 samples = 0; 478 while (frames_left && (fifo_samples >= runtime->channels)) { 479 samples += runtime->channels; 480 fifo_samples -= runtime->channels; 481 frames_left--; 482 } 483 484 /* not enough samples yet */ 485 if (!samples) 486 break; 487 488 /* calculate new buffer index */ 489 buf = (u16 *)runtime->dma_area; 490 buf += strm->buffer_pos * runtime->channels; 491 492 /* Note, only supports 16-bit samples */ 493 for (i = 0; i < samples; i++) 494 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 495 496 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 497 rz_ssi_pointer_update(strm, samples / runtime->channels); 498 } while (!frames_left && fifo_samples >= runtime->channels); 499 500 return 0; 501 } 502 503 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 504 { 505 struct snd_pcm_substream *substream = strm->substream; 506 struct snd_pcm_runtime *runtime = substream->runtime; 507 int sample_space; 508 int samples = 0; 509 int frames_left; 510 int i; 511 u32 ssifsr; 512 u16 *buf; 513 514 if (!rz_ssi_stream_is_valid(ssi, strm)) 515 return -EINVAL; 516 517 /* frames left in this period */ 518 frames_left = runtime->period_size - (strm->buffer_pos % 519 runtime->period_size); 520 if (frames_left == 0) 521 frames_left = runtime->period_size; 522 523 sample_space = strm->fifo_sample_size; 524 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 525 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 526 527 /* Only add full frames at a time */ 528 while (frames_left && (sample_space >= runtime->channels)) { 529 samples += runtime->channels; 530 sample_space -= runtime->channels; 531 frames_left--; 532 } 533 534 /* no space to send anything right now */ 535 if (samples == 0) 536 return 0; 537 538 /* calculate new buffer index */ 539 buf = (u16 *)(runtime->dma_area); 540 buf += strm->buffer_pos * runtime->channels; 541 542 /* Note, only supports 16-bit samples */ 543 for (i = 0; i < samples; i++) 544 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 545 546 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 547 rz_ssi_pointer_update(strm, samples / runtime->channels); 548 549 return 0; 550 } 551 552 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 553 { 554 struct rz_ssi_stream *strm_playback = NULL; 555 struct rz_ssi_stream *strm_capture = NULL; 556 struct rz_ssi_priv *ssi = data; 557 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 558 559 if (ssi->playback.substream) 560 strm_playback = &ssi->playback; 561 if (ssi->capture.substream) 562 strm_capture = &ssi->capture; 563 564 if (!strm_playback && !strm_capture) 565 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 566 567 if (irq == ssi->irq_int) { /* error or idle */ 568 bool is_stopped = false; 569 int i, count; 570 571 if (rz_ssi_is_dma_enabled(ssi)) 572 count = 4; 573 else 574 count = 1; 575 576 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 577 is_stopped = true; 578 579 if (ssi->capture.substream && is_stopped) { 580 if (ssisr & SSISR_RUIRQ) 581 strm_capture->uerr_num++; 582 if (ssisr & SSISR_ROIRQ) 583 strm_capture->oerr_num++; 584 585 rz_ssi_stop(ssi, strm_capture); 586 } 587 588 if (ssi->playback.substream && is_stopped) { 589 if (ssisr & SSISR_TUIRQ) 590 strm_playback->uerr_num++; 591 if (ssisr & SSISR_TOIRQ) 592 strm_playback->oerr_num++; 593 594 rz_ssi_stop(ssi, strm_playback); 595 } 596 597 /* Clear all flags */ 598 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 599 SSISR_ROIRQ | SSISR_RUIRQ, 0); 600 601 /* Add/remove more data */ 602 if (ssi->capture.substream && is_stopped) { 603 for (i = 0; i < count; i++) 604 strm_capture->transfer(ssi, strm_capture); 605 } 606 607 if (ssi->playback.substream && is_stopped) { 608 for (i = 0; i < count; i++) 609 strm_playback->transfer(ssi, strm_playback); 610 } 611 612 /* Resume */ 613 if (ssi->playback.substream && is_stopped) 614 rz_ssi_start(ssi, &ssi->playback); 615 if (ssi->capture.substream && is_stopped) 616 rz_ssi_start(ssi, &ssi->capture); 617 } 618 619 if (!rz_ssi_is_stream_running(&ssi->playback) && 620 !rz_ssi_is_stream_running(&ssi->capture)) 621 return IRQ_HANDLED; 622 623 /* tx data empty */ 624 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 625 strm_playback->transfer(ssi, &ssi->playback); 626 627 /* rx data full */ 628 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 629 strm_capture->transfer(ssi, &ssi->capture); 630 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 631 } 632 633 if (irq == ssi->irq_rt) { 634 if (ssi->playback.substream) { 635 strm_playback->transfer(ssi, &ssi->playback); 636 } else { 637 strm_capture->transfer(ssi, &ssi->capture); 638 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 639 } 640 } 641 642 return IRQ_HANDLED; 643 } 644 645 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 646 struct dma_chan *dma_ch, bool is_play) 647 { 648 struct dma_slave_config cfg; 649 650 memset(&cfg, 0, sizeof(cfg)); 651 652 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 653 cfg.dst_addr = ssi->phys + SSIFTDR; 654 cfg.src_addr = ssi->phys + SSIFRDR; 655 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 656 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 657 658 return dmaengine_slave_config(dma_ch, &cfg); 659 } 660 661 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 662 struct rz_ssi_stream *strm) 663 { 664 struct snd_pcm_substream *substream = strm->substream; 665 struct dma_async_tx_descriptor *desc; 666 struct snd_pcm_runtime *runtime; 667 enum dma_transfer_direction dir; 668 u32 dma_paddr, dma_size; 669 int amount; 670 671 if (!rz_ssi_stream_is_valid(ssi, strm)) 672 return -EINVAL; 673 674 runtime = substream->runtime; 675 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 676 /* 677 * Stream is ending, so do not queue up any more DMA 678 * transfers otherwise we play partial sound clips 679 * because we can't shut off the DMA quick enough. 680 */ 681 return 0; 682 683 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 684 685 /* Always transfer 1 period */ 686 amount = runtime->period_size; 687 688 /* DMA physical address and size */ 689 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 690 strm->dma_buffer_pos); 691 dma_size = frames_to_bytes(runtime, amount); 692 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 693 dir, 694 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 695 if (!desc) { 696 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 697 return -ENOMEM; 698 } 699 700 desc->callback = rz_ssi_dma_complete; 701 desc->callback_param = strm; 702 703 if (dmaengine_submit(desc) < 0) { 704 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 705 return -EIO; 706 } 707 708 /* Update DMA pointer */ 709 strm->dma_buffer_pos += amount; 710 if (strm->dma_buffer_pos >= runtime->buffer_size) 711 strm->dma_buffer_pos = 0; 712 713 /* Start DMA */ 714 dma_async_issue_pending(strm->dma_ch); 715 716 return 0; 717 } 718 719 static void rz_ssi_dma_complete(void *data) 720 { 721 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 722 723 if (!strm->running || !strm->substream || !strm->substream->runtime) 724 return; 725 726 /* Note that next DMA transaction has probably already started */ 727 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 728 729 /* Queue up another DMA transaction */ 730 rz_ssi_dma_transfer(strm->priv, strm); 731 } 732 733 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 734 { 735 if (ssi->playback.dma_ch) { 736 dma_release_channel(ssi->playback.dma_ch); 737 ssi->playback.dma_ch = NULL; 738 if (ssi->dma_rt) 739 ssi->dma_rt = false; 740 } 741 742 if (ssi->capture.dma_ch) { 743 dma_release_channel(ssi->capture.dma_ch); 744 ssi->capture.dma_ch = NULL; 745 } 746 } 747 748 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 749 { 750 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 751 if (IS_ERR(ssi->playback.dma_ch)) 752 ssi->playback.dma_ch = NULL; 753 754 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 755 if (IS_ERR(ssi->capture.dma_ch)) 756 ssi->capture.dma_ch = NULL; 757 758 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 759 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 760 if (IS_ERR(ssi->playback.dma_ch)) { 761 ssi->playback.dma_ch = NULL; 762 goto no_dma; 763 } 764 765 ssi->dma_rt = true; 766 } 767 768 if (!rz_ssi_is_dma_enabled(ssi)) 769 goto no_dma; 770 771 if (ssi->playback.dma_ch && 772 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 773 goto no_dma; 774 775 if (ssi->capture.dma_ch && 776 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 777 goto no_dma; 778 779 return 0; 780 781 no_dma: 782 rz_ssi_release_dma_channels(ssi); 783 784 return -ENODEV; 785 } 786 787 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 788 struct snd_soc_dai *dai) 789 { 790 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 791 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 792 int ret = 0, i, num_transfer = 1; 793 794 switch (cmd) { 795 case SNDRV_PCM_TRIGGER_START: 796 /* Soft Reset */ 797 if (!rz_ssi_is_stream_running(&ssi->playback) && 798 !rz_ssi_is_stream_running(&ssi->capture)) { 799 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 800 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 801 udelay(5); 802 } 803 804 rz_ssi_stream_init(strm, substream); 805 806 if (ssi->dma_rt) { 807 bool is_playback; 808 809 is_playback = rz_ssi_stream_is_play(ssi, substream); 810 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 811 is_playback); 812 /* Fallback to pio */ 813 if (ret < 0) { 814 ssi->playback.transfer = rz_ssi_pio_send; 815 ssi->capture.transfer = rz_ssi_pio_recv; 816 rz_ssi_release_dma_channels(ssi); 817 } 818 } 819 820 /* For DMA, queue up multiple DMA descriptors */ 821 if (rz_ssi_is_dma_enabled(ssi)) 822 num_transfer = 4; 823 824 for (i = 0; i < num_transfer; i++) { 825 ret = strm->transfer(ssi, strm); 826 if (ret) 827 goto done; 828 } 829 830 ret = rz_ssi_start(ssi, strm); 831 break; 832 case SNDRV_PCM_TRIGGER_STOP: 833 rz_ssi_stop(ssi, strm); 834 rz_ssi_stream_quit(ssi, strm); 835 break; 836 } 837 838 done: 839 return ret; 840 } 841 842 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 843 { 844 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 845 846 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 847 case SND_SOC_DAIFMT_BP_FP: 848 break; 849 default: 850 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 851 return -EINVAL; 852 } 853 854 /* 855 * set clock polarity 856 * 857 * "normal" BCLK = Signal is available at rising edge of BCLK 858 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 859 */ 860 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 861 case SND_SOC_DAIFMT_NB_NF: 862 ssi->bckp_rise = false; 863 ssi->lrckp_fsync_fall = false; 864 break; 865 case SND_SOC_DAIFMT_NB_IF: 866 ssi->bckp_rise = false; 867 ssi->lrckp_fsync_fall = true; 868 break; 869 case SND_SOC_DAIFMT_IB_NF: 870 ssi->bckp_rise = true; 871 ssi->lrckp_fsync_fall = false; 872 break; 873 case SND_SOC_DAIFMT_IB_IF: 874 ssi->bckp_rise = true; 875 ssi->lrckp_fsync_fall = true; 876 break; 877 default: 878 return -EINVAL; 879 } 880 881 /* only i2s support */ 882 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 883 case SND_SOC_DAIFMT_I2S: 884 break; 885 default: 886 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 887 return -EINVAL; 888 } 889 890 return 0; 891 } 892 893 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 894 unsigned int channels, 895 unsigned int sample_width, 896 unsigned int sample_bits) 897 { 898 if (ssi->hw_params_cache.rate != rate || 899 ssi->hw_params_cache.channels != channels || 900 ssi->hw_params_cache.sample_width != sample_width || 901 ssi->hw_params_cache.sample_bits != sample_bits) 902 return false; 903 904 return true; 905 } 906 907 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 908 unsigned int channels, 909 unsigned int sample_width, 910 unsigned int sample_bits) 911 { 912 ssi->hw_params_cache.rate = rate; 913 ssi->hw_params_cache.channels = channels; 914 ssi->hw_params_cache.sample_width = sample_width; 915 ssi->hw_params_cache.sample_bits = sample_bits; 916 } 917 918 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 919 struct snd_pcm_hw_params *params, 920 struct snd_soc_dai *dai) 921 { 922 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 923 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 924 unsigned int sample_bits = hw_param_interval(params, 925 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 926 unsigned int channels = params_channels(params); 927 unsigned int rate = params_rate(params); 928 929 if (sample_bits != 16) { 930 dev_err(ssi->dev, "Unsupported sample width: %d\n", 931 sample_bits); 932 return -EINVAL; 933 } 934 935 if (channels != 2) { 936 dev_err(ssi->dev, "Number of channels not matched: %d\n", 937 channels); 938 return -EINVAL; 939 } 940 941 if (rz_ssi_is_stream_running(&ssi->playback) || 942 rz_ssi_is_stream_running(&ssi->capture)) { 943 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 944 strm->sample_width, sample_bits)) 945 return 0; 946 947 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 948 return -EINVAL; 949 } 950 951 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 952 sample_bits); 953 954 return rz_ssi_clk_setup(ssi, rate, channels); 955 } 956 957 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 958 .trigger = rz_ssi_dai_trigger, 959 .set_fmt = rz_ssi_dai_set_fmt, 960 .hw_params = rz_ssi_dai_hw_params, 961 }; 962 963 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 964 .info = SNDRV_PCM_INFO_INTERLEAVED | 965 SNDRV_PCM_INFO_MMAP | 966 SNDRV_PCM_INFO_MMAP_VALID, 967 .buffer_bytes_max = PREALLOC_BUFFER, 968 .period_bytes_min = 32, 969 .period_bytes_max = 8192, 970 .channels_min = SSI_CHAN_MIN, 971 .channels_max = SSI_CHAN_MAX, 972 .periods_min = 1, 973 .periods_max = 32, 974 .fifo_size = 32 * 2, 975 }; 976 977 static int rz_ssi_pcm_open(struct snd_soc_component *component, 978 struct snd_pcm_substream *substream) 979 { 980 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 981 982 return snd_pcm_hw_constraint_integer(substream->runtime, 983 SNDRV_PCM_HW_PARAM_PERIODS); 984 } 985 986 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 987 struct snd_pcm_substream *substream) 988 { 989 struct snd_soc_dai *dai = rz_ssi_get_dai(substream); 990 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 991 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 992 993 return strm->buffer_pos; 994 } 995 996 static int rz_ssi_pcm_new(struct snd_soc_component *component, 997 struct snd_soc_pcm_runtime *rtd) 998 { 999 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 1000 rtd->card->snd_card->dev, 1001 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1002 return 0; 1003 } 1004 1005 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1006 { 1007 .name = "rz-ssi-dai", 1008 .playback = { 1009 .rates = SSI_RATES, 1010 .formats = SSI_FMTS, 1011 .channels_min = SSI_CHAN_MIN, 1012 .channels_max = SSI_CHAN_MAX, 1013 }, 1014 .capture = { 1015 .rates = SSI_RATES, 1016 .formats = SSI_FMTS, 1017 .channels_min = SSI_CHAN_MIN, 1018 .channels_max = SSI_CHAN_MAX, 1019 }, 1020 .ops = &rz_ssi_dai_ops, 1021 }, 1022 }; 1023 1024 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1025 .name = "rz-ssi", 1026 .open = rz_ssi_pcm_open, 1027 .pointer = rz_ssi_pcm_pointer, 1028 .pcm_construct = rz_ssi_pcm_new, 1029 .legacy_dai_naming = 1, 1030 }; 1031 1032 static int rz_ssi_probe(struct platform_device *pdev) 1033 { 1034 struct rz_ssi_priv *ssi; 1035 struct clk *audio_clk; 1036 struct resource *res; 1037 int ret; 1038 1039 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 1040 if (!ssi) 1041 return -ENOMEM; 1042 1043 ssi->pdev = pdev; 1044 ssi->dev = &pdev->dev; 1045 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1046 if (IS_ERR(ssi->base)) 1047 return PTR_ERR(ssi->base); 1048 1049 ssi->phys = res->start; 1050 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 1051 if (IS_ERR(ssi->clk)) 1052 return PTR_ERR(ssi->clk); 1053 1054 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 1055 if (IS_ERR(ssi->sfr_clk)) 1056 return PTR_ERR(ssi->sfr_clk); 1057 1058 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 1059 if (IS_ERR(audio_clk)) 1060 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1061 "no audio clk1"); 1062 1063 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1064 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 1065 if (IS_ERR(audio_clk)) 1066 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1067 "no audio clk2"); 1068 1069 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1070 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1071 return dev_err_probe(&pdev->dev, -EINVAL, 1072 "no audio clk1 or audio clk2"); 1073 1074 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1075 1076 /* Detect DMA support */ 1077 ret = rz_ssi_dma_request(ssi, &pdev->dev); 1078 if (ret < 0) { 1079 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1080 ssi->playback.transfer = rz_ssi_pio_send; 1081 ssi->capture.transfer = rz_ssi_pio_recv; 1082 } else { 1083 dev_info(&pdev->dev, "DMA enabled"); 1084 ssi->playback.transfer = rz_ssi_dma_transfer; 1085 ssi->capture.transfer = rz_ssi_dma_transfer; 1086 } 1087 1088 ssi->playback.priv = ssi; 1089 ssi->capture.priv = ssi; 1090 1091 spin_lock_init(&ssi->lock); 1092 dev_set_drvdata(&pdev->dev, ssi); 1093 1094 /* Error Interrupt */ 1095 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1096 if (ssi->irq_int < 0) { 1097 rz_ssi_release_dma_channels(ssi); 1098 return ssi->irq_int; 1099 } 1100 1101 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 1102 0, dev_name(&pdev->dev), ssi); 1103 if (ret < 0) { 1104 rz_ssi_release_dma_channels(ssi); 1105 return dev_err_probe(&pdev->dev, ret, 1106 "irq request error (int_req)\n"); 1107 } 1108 1109 if (!rz_ssi_is_dma_enabled(ssi)) { 1110 /* Tx and Rx interrupts (pio only) */ 1111 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1112 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1113 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1114 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1115 if (ssi->irq_rt < 0) 1116 return ssi->irq_rt; 1117 1118 ret = devm_request_irq(&pdev->dev, ssi->irq_rt, 1119 &rz_ssi_interrupt, 0, 1120 dev_name(&pdev->dev), ssi); 1121 if (ret < 0) 1122 return dev_err_probe(&pdev->dev, ret, 1123 "irq request error (dma_rt)\n"); 1124 } else { 1125 if (ssi->irq_tx < 0) 1126 return ssi->irq_tx; 1127 1128 if (ssi->irq_rx < 0) 1129 return ssi->irq_rx; 1130 1131 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1132 &rz_ssi_interrupt, 0, 1133 dev_name(&pdev->dev), ssi); 1134 if (ret < 0) 1135 return dev_err_probe(&pdev->dev, ret, 1136 "irq request error (dma_tx)\n"); 1137 1138 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1139 &rz_ssi_interrupt, 0, 1140 dev_name(&pdev->dev), ssi); 1141 if (ret < 0) 1142 return dev_err_probe(&pdev->dev, ret, 1143 "irq request error (dma_rx)\n"); 1144 } 1145 } 1146 1147 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1148 if (IS_ERR(ssi->rstc)) { 1149 ret = PTR_ERR(ssi->rstc); 1150 goto err_reset; 1151 } 1152 1153 reset_control_deassert(ssi->rstc); 1154 pm_runtime_enable(&pdev->dev); 1155 ret = pm_runtime_resume_and_get(&pdev->dev); 1156 if (ret < 0) { 1157 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1158 goto err_pm; 1159 } 1160 1161 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1162 rz_ssi_soc_dai, 1163 ARRAY_SIZE(rz_ssi_soc_dai)); 1164 if (ret < 0) { 1165 dev_err(&pdev->dev, "failed to register snd component\n"); 1166 goto err_snd_soc; 1167 } 1168 1169 return 0; 1170 1171 err_snd_soc: 1172 pm_runtime_put(ssi->dev); 1173 err_pm: 1174 pm_runtime_disable(ssi->dev); 1175 reset_control_assert(ssi->rstc); 1176 err_reset: 1177 rz_ssi_release_dma_channels(ssi); 1178 1179 return ret; 1180 } 1181 1182 static void rz_ssi_remove(struct platform_device *pdev) 1183 { 1184 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1185 1186 rz_ssi_release_dma_channels(ssi); 1187 1188 pm_runtime_put(ssi->dev); 1189 pm_runtime_disable(ssi->dev); 1190 reset_control_assert(ssi->rstc); 1191 } 1192 1193 static const struct of_device_id rz_ssi_of_match[] = { 1194 { .compatible = "renesas,rz-ssi", }, 1195 {/* Sentinel */}, 1196 }; 1197 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1198 1199 static struct platform_driver rz_ssi_driver = { 1200 .driver = { 1201 .name = "rz-ssi-pcm-audio", 1202 .of_match_table = rz_ssi_of_match, 1203 }, 1204 .probe = rz_ssi_probe, 1205 .remove = rz_ssi_remove, 1206 }; 1207 1208 module_platform_driver(rz_ssi_driver); 1209 1210 MODULE_LICENSE("GPL v2"); 1211 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1212 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1213