1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 #include <sound/soc.h> 16 17 /* REGISTER OFFSET */ 18 #define SSICR 0x000 19 #define SSISR 0x004 20 #define SSIFCR 0x010 21 #define SSIFSR 0x014 22 #define SSIFTDR 0x018 23 #define SSIFRDR 0x01c 24 #define SSIOFR 0x020 25 #define SSISCR 0x024 26 27 /* SSI REGISTER BITS */ 28 #define SSICR_DWL(x) (((x) & 0x7) << 19) 29 #define SSICR_SWL(x) (((x) & 0x7) << 16) 30 31 #define SSICR_CKS BIT(30) 32 #define SSICR_TUIEN BIT(29) 33 #define SSICR_TOIEN BIT(28) 34 #define SSICR_RUIEN BIT(27) 35 #define SSICR_ROIEN BIT(26) 36 #define SSICR_MST BIT(14) 37 #define SSICR_BCKP BIT(13) 38 #define SSICR_LRCKP BIT(12) 39 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 40 #define SSICR_TEN BIT(1) 41 #define SSICR_REN BIT(0) 42 43 #define SSISR_TUIRQ BIT(29) 44 #define SSISR_TOIRQ BIT(28) 45 #define SSISR_RUIRQ BIT(27) 46 #define SSISR_ROIRQ BIT(26) 47 #define SSISR_IIRQ BIT(25) 48 49 #define SSIFCR_AUCKE BIT(31) 50 #define SSIFCR_SSIRST BIT(16) 51 #define SSIFCR_TIE BIT(3) 52 #define SSIFCR_RIE BIT(2) 53 #define SSIFCR_TFRST BIT(1) 54 #define SSIFCR_RFRST BIT(0) 55 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 56 57 #define SSIFSR_TDC_MASK 0x3f 58 #define SSIFSR_TDC_SHIFT 24 59 #define SSIFSR_RDC_MASK 0x3f 60 #define SSIFSR_RDC_SHIFT 8 61 62 #define SSIFSR_TDE BIT(16) 63 #define SSIFSR_RDF BIT(0) 64 65 #define SSIOFR_LRCONT BIT(8) 66 67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 69 70 /* Pre allocated buffers sizes */ 71 #define PREALLOC_BUFFER (SZ_32K) 72 #define PREALLOC_BUFFER_MAX (SZ_32K) 73 74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-44.1kHz */ 75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 76 #define SSI_CHAN_MIN 2 77 #define SSI_CHAN_MAX 2 78 #define SSI_FIFO_DEPTH 32 79 80 struct rz_ssi_priv; 81 82 struct rz_ssi_stream { 83 struct rz_ssi_priv *priv; 84 struct snd_pcm_substream *substream; 85 int fifo_sample_size; /* sample capacity of SSI FIFO */ 86 int dma_buffer_pos; /* The address for the next DMA descriptor */ 87 int period_counter; /* for keeping track of periods transferred */ 88 int sample_width; 89 int buffer_pos; /* current frame position in the buffer */ 90 int running; /* 0=stopped, 1=running */ 91 92 int uerr_num; 93 int oerr_num; 94 95 struct dma_chan *dma_ch; 96 97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 98 }; 99 100 struct rz_ssi_priv { 101 void __iomem *base; 102 struct platform_device *pdev; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 /* Full duplex communication support */ 136 struct { 137 unsigned int rate; 138 unsigned int channels; 139 unsigned int sample_width; 140 unsigned int sample_bits; 141 } hw_params_cache; 142 }; 143 144 static void rz_ssi_dma_complete(void *data); 145 146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 147 { 148 writel(data, (priv->base + reg)); 149 } 150 151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 152 { 153 return readl(priv->base + reg); 154 } 155 156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 157 u32 bclr, u32 bset) 158 { 159 u32 val; 160 161 val = readl(priv->base + reg); 162 val = (val & ~bclr) | bset; 163 writel(val, (priv->base + reg)); 164 } 165 166 static inline struct snd_soc_dai * 167 rz_ssi_get_dai(struct snd_pcm_substream *substream) 168 { 169 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 170 171 return snd_soc_rtd_to_cpu(rtd, 0); 172 } 173 174 static inline bool rz_ssi_stream_is_play(struct rz_ssi_priv *ssi, 175 struct snd_pcm_substream *substream) 176 { 177 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 178 } 179 180 static inline struct rz_ssi_stream * 181 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 182 { 183 struct rz_ssi_stream *stream = &ssi->playback; 184 185 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 186 stream = &ssi->capture; 187 188 return stream; 189 } 190 191 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 192 { 193 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 194 } 195 196 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 197 struct snd_pcm_substream *substream) 198 { 199 struct rz_ssi_priv *ssi = strm->priv; 200 unsigned long flags; 201 202 spin_lock_irqsave(&ssi->lock, flags); 203 strm->substream = substream; 204 spin_unlock_irqrestore(&ssi->lock, flags); 205 } 206 207 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 208 struct rz_ssi_stream *strm) 209 { 210 unsigned long flags; 211 bool ret; 212 213 spin_lock_irqsave(&ssi->lock, flags); 214 ret = strm->substream && strm->substream->runtime; 215 spin_unlock_irqrestore(&ssi->lock, flags); 216 217 return ret; 218 } 219 220 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 221 { 222 return strm->substream && strm->running; 223 } 224 225 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 226 struct snd_pcm_substream *substream) 227 { 228 struct snd_pcm_runtime *runtime = substream->runtime; 229 230 rz_ssi_set_substream(strm, substream); 231 strm->sample_width = samples_to_bytes(runtime, 1); 232 strm->dma_buffer_pos = 0; 233 strm->period_counter = 0; 234 strm->buffer_pos = 0; 235 236 strm->oerr_num = 0; 237 strm->uerr_num = 0; 238 strm->running = 0; 239 240 /* fifo init */ 241 strm->fifo_sample_size = SSI_FIFO_DEPTH; 242 } 243 244 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 245 struct rz_ssi_stream *strm) 246 { 247 struct snd_soc_dai *dai = rz_ssi_get_dai(strm->substream); 248 249 rz_ssi_set_substream(strm, NULL); 250 251 if (strm->oerr_num > 0) 252 dev_info(dai->dev, "overrun = %d\n", strm->oerr_num); 253 254 if (strm->uerr_num > 0) 255 dev_info(dai->dev, "underrun = %d\n", strm->uerr_num); 256 } 257 258 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 259 unsigned int channels) 260 { 261 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 262 unsigned int channel_bits = 32; /* System Word Length */ 263 unsigned long bclk_rate = rate * channels * channel_bits; 264 unsigned int div; 265 unsigned int i; 266 u32 ssicr = 0; 267 u32 clk_ckdv; 268 269 /* Clear AUCKE so we can set MST */ 270 rz_ssi_reg_writel(ssi, SSIFCR, 0); 271 272 /* Continue to output LRCK pin even when idle */ 273 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 274 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 275 if (ssi->audio_clk_1 % bclk_rate) 276 ssi->audio_mck = ssi->audio_clk_2; 277 else 278 ssi->audio_mck = ssi->audio_clk_1; 279 } 280 281 /* Clock setting */ 282 ssicr |= SSICR_MST; 283 if (ssi->audio_mck == ssi->audio_clk_1) 284 ssicr |= SSICR_CKS; 285 if (ssi->bckp_rise) 286 ssicr |= SSICR_BCKP; 287 if (ssi->lrckp_fsync_fall) 288 ssicr |= SSICR_LRCKP; 289 290 /* Determine the clock divider */ 291 clk_ckdv = 0; 292 div = ssi->audio_mck / bclk_rate; 293 /* try to find an match */ 294 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 295 if (ckdv[i] == div) { 296 clk_ckdv = i; 297 break; 298 } 299 } 300 301 if (i == ARRAY_SIZE(ckdv)) { 302 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 303 return -EINVAL; 304 } 305 306 /* 307 * DWL: Data Word Length = 16 bits 308 * SWL: System Word Length = 32 bits 309 */ 310 ssicr |= SSICR_CKDV(clk_ckdv); 311 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 312 rz_ssi_reg_writel(ssi, SSICR, ssicr); 313 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 314 315 return 0; 316 } 317 318 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 319 { 320 int timeout; 321 322 /* Disable irqs */ 323 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 324 SSICR_RUIEN | SSICR_ROIEN, 0); 325 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 326 327 /* Clear all error flags */ 328 rz_ssi_reg_mask_setl(ssi, SSISR, 329 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 330 SSISR_RUIRQ), 0); 331 332 /* Wait for idle */ 333 timeout = 100; 334 while (--timeout) { 335 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ) 336 break; 337 udelay(1); 338 } 339 340 if (!timeout) 341 dev_info(ssi->dev, "timeout waiting for SSI idle\n"); 342 343 /* Hold FIFOs in reset */ 344 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 345 } 346 347 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 348 { 349 bool is_play = rz_ssi_stream_is_play(ssi, strm->substream); 350 bool is_full_duplex; 351 u32 ssicr, ssifcr; 352 353 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 354 rz_ssi_is_stream_running(&ssi->capture); 355 ssicr = rz_ssi_reg_readl(ssi, SSICR); 356 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 357 if (!is_full_duplex) { 358 ssifcr &= ~0xF; 359 } else { 360 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 361 rz_ssi_set_idle(ssi); 362 ssifcr &= ~SSIFCR_FIFO_RST; 363 } 364 365 /* FIFO interrupt thresholds */ 366 if (rz_ssi_is_dma_enabled(ssi)) 367 rz_ssi_reg_writel(ssi, SSISCR, 0); 368 else 369 rz_ssi_reg_writel(ssi, SSISCR, 370 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 371 SSISCR_RDFS(0)); 372 373 /* enable IRQ */ 374 if (is_play) { 375 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 376 ssifcr |= SSIFCR_TIE; 377 if (!is_full_duplex) 378 ssifcr |= SSIFCR_RFRST; 379 } else { 380 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 381 ssifcr |= SSIFCR_RIE; 382 if (!is_full_duplex) 383 ssifcr |= SSIFCR_TFRST; 384 } 385 386 rz_ssi_reg_writel(ssi, SSICR, ssicr); 387 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 388 389 /* Clear all error flags */ 390 rz_ssi_reg_mask_setl(ssi, SSISR, 391 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 392 SSISR_RUIRQ), 0); 393 394 strm->running = 1; 395 if (is_full_duplex) 396 ssicr |= SSICR_TEN | SSICR_REN; 397 else 398 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 399 400 rz_ssi_reg_writel(ssi, SSICR, ssicr); 401 402 return 0; 403 } 404 405 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 406 { 407 strm->running = 0; 408 409 if (rz_ssi_is_stream_running(&ssi->playback) || 410 rz_ssi_is_stream_running(&ssi->capture)) 411 return 0; 412 413 /* Disable TX/RX */ 414 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 415 416 /* Cancel all remaining DMA transactions */ 417 if (rz_ssi_is_dma_enabled(ssi)) { 418 if (ssi->playback.dma_ch) 419 dmaengine_terminate_async(ssi->playback.dma_ch); 420 if (ssi->capture.dma_ch) 421 dmaengine_terminate_async(ssi->capture.dma_ch); 422 } 423 424 rz_ssi_set_idle(ssi); 425 426 return 0; 427 } 428 429 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 430 { 431 struct snd_pcm_substream *substream = strm->substream; 432 struct snd_pcm_runtime *runtime; 433 int current_period; 434 435 if (!strm->running || !substream || !substream->runtime) 436 return; 437 438 runtime = substream->runtime; 439 strm->buffer_pos += frames; 440 WARN_ON(strm->buffer_pos > runtime->buffer_size); 441 442 /* ring buffer */ 443 if (strm->buffer_pos == runtime->buffer_size) 444 strm->buffer_pos = 0; 445 446 current_period = strm->buffer_pos / runtime->period_size; 447 if (strm->period_counter != current_period) { 448 snd_pcm_period_elapsed(strm->substream); 449 strm->period_counter = current_period; 450 } 451 } 452 453 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 454 { 455 struct snd_pcm_substream *substream = strm->substream; 456 struct snd_pcm_runtime *runtime; 457 u16 *buf; 458 int fifo_samples; 459 int frames_left; 460 int samples; 461 int i; 462 463 if (!rz_ssi_stream_is_valid(ssi, strm)) 464 return -EINVAL; 465 466 runtime = substream->runtime; 467 468 do { 469 /* frames left in this period */ 470 frames_left = runtime->period_size - 471 (strm->buffer_pos % runtime->period_size); 472 if (!frames_left) 473 frames_left = runtime->period_size; 474 475 /* Samples in RX FIFO */ 476 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 477 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 478 479 /* Only read full frames at a time */ 480 samples = 0; 481 while (frames_left && (fifo_samples >= runtime->channels)) { 482 samples += runtime->channels; 483 fifo_samples -= runtime->channels; 484 frames_left--; 485 } 486 487 /* not enough samples yet */ 488 if (!samples) 489 break; 490 491 /* calculate new buffer index */ 492 buf = (u16 *)runtime->dma_area; 493 buf += strm->buffer_pos * runtime->channels; 494 495 /* Note, only supports 16-bit samples */ 496 for (i = 0; i < samples; i++) 497 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 498 499 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 500 rz_ssi_pointer_update(strm, samples / runtime->channels); 501 } while (!frames_left && fifo_samples >= runtime->channels); 502 503 return 0; 504 } 505 506 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 507 { 508 struct snd_pcm_substream *substream = strm->substream; 509 struct snd_pcm_runtime *runtime = substream->runtime; 510 int sample_space; 511 int samples = 0; 512 int frames_left; 513 int i; 514 u32 ssifsr; 515 u16 *buf; 516 517 if (!rz_ssi_stream_is_valid(ssi, strm)) 518 return -EINVAL; 519 520 /* frames left in this period */ 521 frames_left = runtime->period_size - (strm->buffer_pos % 522 runtime->period_size); 523 if (frames_left == 0) 524 frames_left = runtime->period_size; 525 526 sample_space = strm->fifo_sample_size; 527 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 528 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 529 530 /* Only add full frames at a time */ 531 while (frames_left && (sample_space >= runtime->channels)) { 532 samples += runtime->channels; 533 sample_space -= runtime->channels; 534 frames_left--; 535 } 536 537 /* no space to send anything right now */ 538 if (samples == 0) 539 return 0; 540 541 /* calculate new buffer index */ 542 buf = (u16 *)(runtime->dma_area); 543 buf += strm->buffer_pos * runtime->channels; 544 545 /* Note, only supports 16-bit samples */ 546 for (i = 0; i < samples; i++) 547 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 548 549 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 550 rz_ssi_pointer_update(strm, samples / runtime->channels); 551 552 return 0; 553 } 554 555 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 556 { 557 struct rz_ssi_stream *strm_playback = NULL; 558 struct rz_ssi_stream *strm_capture = NULL; 559 struct rz_ssi_priv *ssi = data; 560 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 561 562 if (ssi->playback.substream) 563 strm_playback = &ssi->playback; 564 if (ssi->capture.substream) 565 strm_capture = &ssi->capture; 566 567 if (!strm_playback && !strm_capture) 568 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 569 570 if (irq == ssi->irq_int) { /* error or idle */ 571 bool is_stopped = false; 572 int i, count; 573 574 if (rz_ssi_is_dma_enabled(ssi)) 575 count = 4; 576 else 577 count = 1; 578 579 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 580 is_stopped = true; 581 582 if (ssi->capture.substream && is_stopped) { 583 if (ssisr & SSISR_RUIRQ) 584 strm_capture->uerr_num++; 585 if (ssisr & SSISR_ROIRQ) 586 strm_capture->oerr_num++; 587 588 rz_ssi_stop(ssi, strm_capture); 589 } 590 591 if (ssi->playback.substream && is_stopped) { 592 if (ssisr & SSISR_TUIRQ) 593 strm_playback->uerr_num++; 594 if (ssisr & SSISR_TOIRQ) 595 strm_playback->oerr_num++; 596 597 rz_ssi_stop(ssi, strm_playback); 598 } 599 600 /* Clear all flags */ 601 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 602 SSISR_ROIRQ | SSISR_RUIRQ, 0); 603 604 /* Add/remove more data */ 605 if (ssi->capture.substream && is_stopped) { 606 for (i = 0; i < count; i++) 607 strm_capture->transfer(ssi, strm_capture); 608 } 609 610 if (ssi->playback.substream && is_stopped) { 611 for (i = 0; i < count; i++) 612 strm_playback->transfer(ssi, strm_playback); 613 } 614 615 /* Resume */ 616 if (ssi->playback.substream && is_stopped) 617 rz_ssi_start(ssi, &ssi->playback); 618 if (ssi->capture.substream && is_stopped) 619 rz_ssi_start(ssi, &ssi->capture); 620 } 621 622 if (!rz_ssi_is_stream_running(&ssi->playback) && 623 !rz_ssi_is_stream_running(&ssi->capture)) 624 return IRQ_HANDLED; 625 626 /* tx data empty */ 627 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 628 strm_playback->transfer(ssi, &ssi->playback); 629 630 /* rx data full */ 631 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 632 strm_capture->transfer(ssi, &ssi->capture); 633 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 634 } 635 636 if (irq == ssi->irq_rt) { 637 if (ssi->playback.substream) { 638 strm_playback->transfer(ssi, &ssi->playback); 639 } else { 640 strm_capture->transfer(ssi, &ssi->capture); 641 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 642 } 643 } 644 645 return IRQ_HANDLED; 646 } 647 648 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 649 struct dma_chan *dma_ch, bool is_play) 650 { 651 struct dma_slave_config cfg; 652 653 memset(&cfg, 0, sizeof(cfg)); 654 655 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 656 cfg.dst_addr = ssi->phys + SSIFTDR; 657 cfg.src_addr = ssi->phys + SSIFRDR; 658 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 659 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 660 661 return dmaengine_slave_config(dma_ch, &cfg); 662 } 663 664 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 665 struct rz_ssi_stream *strm) 666 { 667 struct snd_pcm_substream *substream = strm->substream; 668 struct dma_async_tx_descriptor *desc; 669 struct snd_pcm_runtime *runtime; 670 enum dma_transfer_direction dir; 671 u32 dma_paddr, dma_size; 672 int amount; 673 674 if (!rz_ssi_stream_is_valid(ssi, strm)) 675 return -EINVAL; 676 677 runtime = substream->runtime; 678 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 679 /* 680 * Stream is ending, so do not queue up any more DMA 681 * transfers otherwise we play partial sound clips 682 * because we can't shut off the DMA quick enough. 683 */ 684 return 0; 685 686 dir = rz_ssi_stream_is_play(ssi, substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 687 688 /* Always transfer 1 period */ 689 amount = runtime->period_size; 690 691 /* DMA physical address and size */ 692 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 693 strm->dma_buffer_pos); 694 dma_size = frames_to_bytes(runtime, amount); 695 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 696 dir, 697 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 698 if (!desc) { 699 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 700 return -ENOMEM; 701 } 702 703 desc->callback = rz_ssi_dma_complete; 704 desc->callback_param = strm; 705 706 if (dmaengine_submit(desc) < 0) { 707 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 708 return -EIO; 709 } 710 711 /* Update DMA pointer */ 712 strm->dma_buffer_pos += amount; 713 if (strm->dma_buffer_pos >= runtime->buffer_size) 714 strm->dma_buffer_pos = 0; 715 716 /* Start DMA */ 717 dma_async_issue_pending(strm->dma_ch); 718 719 return 0; 720 } 721 722 static void rz_ssi_dma_complete(void *data) 723 { 724 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 725 726 if (!strm->running || !strm->substream || !strm->substream->runtime) 727 return; 728 729 /* Note that next DMA transaction has probably already started */ 730 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 731 732 /* Queue up another DMA transaction */ 733 rz_ssi_dma_transfer(strm->priv, strm); 734 } 735 736 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 737 { 738 if (ssi->playback.dma_ch) { 739 dma_release_channel(ssi->playback.dma_ch); 740 ssi->playback.dma_ch = NULL; 741 if (ssi->dma_rt) 742 ssi->dma_rt = false; 743 } 744 745 if (ssi->capture.dma_ch) { 746 dma_release_channel(ssi->capture.dma_ch); 747 ssi->capture.dma_ch = NULL; 748 } 749 } 750 751 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 752 { 753 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 754 if (IS_ERR(ssi->playback.dma_ch)) 755 ssi->playback.dma_ch = NULL; 756 757 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 758 if (IS_ERR(ssi->capture.dma_ch)) 759 ssi->capture.dma_ch = NULL; 760 761 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 762 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 763 if (IS_ERR(ssi->playback.dma_ch)) { 764 ssi->playback.dma_ch = NULL; 765 goto no_dma; 766 } 767 768 ssi->dma_rt = true; 769 } 770 771 if (!rz_ssi_is_dma_enabled(ssi)) 772 goto no_dma; 773 774 if (ssi->playback.dma_ch && 775 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 776 goto no_dma; 777 778 if (ssi->capture.dma_ch && 779 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 780 goto no_dma; 781 782 return 0; 783 784 no_dma: 785 rz_ssi_release_dma_channels(ssi); 786 787 return -ENODEV; 788 } 789 790 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 791 struct snd_soc_dai *dai) 792 { 793 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 794 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 795 int ret = 0, i, num_transfer = 1; 796 797 switch (cmd) { 798 case SNDRV_PCM_TRIGGER_START: 799 /* Soft Reset */ 800 if (!rz_ssi_is_stream_running(&ssi->playback) && 801 !rz_ssi_is_stream_running(&ssi->capture)) { 802 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 803 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 804 udelay(5); 805 } 806 807 rz_ssi_stream_init(strm, substream); 808 809 if (ssi->dma_rt) { 810 bool is_playback; 811 812 is_playback = rz_ssi_stream_is_play(ssi, substream); 813 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 814 is_playback); 815 /* Fallback to pio */ 816 if (ret < 0) { 817 ssi->playback.transfer = rz_ssi_pio_send; 818 ssi->capture.transfer = rz_ssi_pio_recv; 819 rz_ssi_release_dma_channels(ssi); 820 } 821 } 822 823 /* For DMA, queue up multiple DMA descriptors */ 824 if (rz_ssi_is_dma_enabled(ssi)) 825 num_transfer = 4; 826 827 for (i = 0; i < num_transfer; i++) { 828 ret = strm->transfer(ssi, strm); 829 if (ret) 830 goto done; 831 } 832 833 ret = rz_ssi_start(ssi, strm); 834 break; 835 case SNDRV_PCM_TRIGGER_STOP: 836 rz_ssi_stop(ssi, strm); 837 rz_ssi_stream_quit(ssi, strm); 838 break; 839 } 840 841 done: 842 return ret; 843 } 844 845 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 846 { 847 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 848 849 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 850 case SND_SOC_DAIFMT_BP_FP: 851 break; 852 default: 853 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 854 return -EINVAL; 855 } 856 857 /* 858 * set clock polarity 859 * 860 * "normal" BCLK = Signal is available at rising edge of BCLK 861 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 862 */ 863 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 864 case SND_SOC_DAIFMT_NB_NF: 865 ssi->bckp_rise = false; 866 ssi->lrckp_fsync_fall = false; 867 break; 868 case SND_SOC_DAIFMT_NB_IF: 869 ssi->bckp_rise = false; 870 ssi->lrckp_fsync_fall = true; 871 break; 872 case SND_SOC_DAIFMT_IB_NF: 873 ssi->bckp_rise = true; 874 ssi->lrckp_fsync_fall = false; 875 break; 876 case SND_SOC_DAIFMT_IB_IF: 877 ssi->bckp_rise = true; 878 ssi->lrckp_fsync_fall = true; 879 break; 880 default: 881 return -EINVAL; 882 } 883 884 /* only i2s support */ 885 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 886 case SND_SOC_DAIFMT_I2S: 887 break; 888 default: 889 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 890 return -EINVAL; 891 } 892 893 return 0; 894 } 895 896 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 897 unsigned int channels, 898 unsigned int sample_width, 899 unsigned int sample_bits) 900 { 901 if (ssi->hw_params_cache.rate != rate || 902 ssi->hw_params_cache.channels != channels || 903 ssi->hw_params_cache.sample_width != sample_width || 904 ssi->hw_params_cache.sample_bits != sample_bits) 905 return false; 906 907 return true; 908 } 909 910 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 911 unsigned int channels, 912 unsigned int sample_width, 913 unsigned int sample_bits) 914 { 915 ssi->hw_params_cache.rate = rate; 916 ssi->hw_params_cache.channels = channels; 917 ssi->hw_params_cache.sample_width = sample_width; 918 ssi->hw_params_cache.sample_bits = sample_bits; 919 } 920 921 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 922 struct snd_pcm_hw_params *params, 923 struct snd_soc_dai *dai) 924 { 925 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 926 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 927 unsigned int sample_bits = hw_param_interval(params, 928 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 929 unsigned int channels = params_channels(params); 930 unsigned int rate = params_rate(params); 931 932 if (sample_bits != 16) { 933 dev_err(ssi->dev, "Unsupported sample width: %d\n", 934 sample_bits); 935 return -EINVAL; 936 } 937 938 if (channels != 2) { 939 dev_err(ssi->dev, "Number of channels not matched: %d\n", 940 channels); 941 return -EINVAL; 942 } 943 944 if (rz_ssi_is_stream_running(&ssi->playback) || 945 rz_ssi_is_stream_running(&ssi->capture)) { 946 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 947 strm->sample_width, sample_bits)) 948 return 0; 949 950 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 951 return -EINVAL; 952 } 953 954 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 955 sample_bits); 956 957 return rz_ssi_clk_setup(ssi, rate, channels); 958 } 959 960 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 961 .trigger = rz_ssi_dai_trigger, 962 .set_fmt = rz_ssi_dai_set_fmt, 963 .hw_params = rz_ssi_dai_hw_params, 964 }; 965 966 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 967 .info = SNDRV_PCM_INFO_INTERLEAVED | 968 SNDRV_PCM_INFO_MMAP | 969 SNDRV_PCM_INFO_MMAP_VALID, 970 .buffer_bytes_max = PREALLOC_BUFFER, 971 .period_bytes_min = 32, 972 .period_bytes_max = 8192, 973 .channels_min = SSI_CHAN_MIN, 974 .channels_max = SSI_CHAN_MAX, 975 .periods_min = 1, 976 .periods_max = 32, 977 .fifo_size = 32 * 2, 978 }; 979 980 static int rz_ssi_pcm_open(struct snd_soc_component *component, 981 struct snd_pcm_substream *substream) 982 { 983 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 984 985 return snd_pcm_hw_constraint_integer(substream->runtime, 986 SNDRV_PCM_HW_PARAM_PERIODS); 987 } 988 989 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 990 struct snd_pcm_substream *substream) 991 { 992 struct snd_soc_dai *dai = rz_ssi_get_dai(substream); 993 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 994 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 995 996 return strm->buffer_pos; 997 } 998 999 static int rz_ssi_pcm_new(struct snd_soc_component *component, 1000 struct snd_soc_pcm_runtime *rtd) 1001 { 1002 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 1003 rtd->card->snd_card->dev, 1004 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 1005 return 0; 1006 } 1007 1008 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1009 { 1010 .name = "rz-ssi-dai", 1011 .playback = { 1012 .rates = SSI_RATES, 1013 .formats = SSI_FMTS, 1014 .channels_min = SSI_CHAN_MIN, 1015 .channels_max = SSI_CHAN_MAX, 1016 }, 1017 .capture = { 1018 .rates = SSI_RATES, 1019 .formats = SSI_FMTS, 1020 .channels_min = SSI_CHAN_MIN, 1021 .channels_max = SSI_CHAN_MAX, 1022 }, 1023 .ops = &rz_ssi_dai_ops, 1024 }, 1025 }; 1026 1027 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1028 .name = "rz-ssi", 1029 .open = rz_ssi_pcm_open, 1030 .pointer = rz_ssi_pcm_pointer, 1031 .pcm_construct = rz_ssi_pcm_new, 1032 .legacy_dai_naming = 1, 1033 }; 1034 1035 static int rz_ssi_probe(struct platform_device *pdev) 1036 { 1037 struct rz_ssi_priv *ssi; 1038 struct clk *audio_clk; 1039 struct resource *res; 1040 int ret; 1041 1042 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 1043 if (!ssi) 1044 return -ENOMEM; 1045 1046 ssi->pdev = pdev; 1047 ssi->dev = &pdev->dev; 1048 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1049 if (IS_ERR(ssi->base)) 1050 return PTR_ERR(ssi->base); 1051 1052 ssi->phys = res->start; 1053 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 1054 if (IS_ERR(ssi->clk)) 1055 return PTR_ERR(ssi->clk); 1056 1057 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 1058 if (IS_ERR(ssi->sfr_clk)) 1059 return PTR_ERR(ssi->sfr_clk); 1060 1061 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 1062 if (IS_ERR(audio_clk)) 1063 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1064 "no audio clk1"); 1065 1066 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1067 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 1068 if (IS_ERR(audio_clk)) 1069 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1070 "no audio clk2"); 1071 1072 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1073 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1074 return dev_err_probe(&pdev->dev, -EINVAL, 1075 "no audio clk1 or audio clk2"); 1076 1077 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1078 1079 /* Detect DMA support */ 1080 ret = rz_ssi_dma_request(ssi, &pdev->dev); 1081 if (ret < 0) { 1082 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1083 ssi->playback.transfer = rz_ssi_pio_send; 1084 ssi->capture.transfer = rz_ssi_pio_recv; 1085 } else { 1086 dev_info(&pdev->dev, "DMA enabled"); 1087 ssi->playback.transfer = rz_ssi_dma_transfer; 1088 ssi->capture.transfer = rz_ssi_dma_transfer; 1089 } 1090 1091 ssi->playback.priv = ssi; 1092 ssi->capture.priv = ssi; 1093 1094 spin_lock_init(&ssi->lock); 1095 dev_set_drvdata(&pdev->dev, ssi); 1096 1097 /* Error Interrupt */ 1098 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1099 if (ssi->irq_int < 0) { 1100 rz_ssi_release_dma_channels(ssi); 1101 return ssi->irq_int; 1102 } 1103 1104 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 1105 0, dev_name(&pdev->dev), ssi); 1106 if (ret < 0) { 1107 rz_ssi_release_dma_channels(ssi); 1108 return dev_err_probe(&pdev->dev, ret, 1109 "irq request error (int_req)\n"); 1110 } 1111 1112 if (!rz_ssi_is_dma_enabled(ssi)) { 1113 /* Tx and Rx interrupts (pio only) */ 1114 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1115 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1116 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1117 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1118 if (ssi->irq_rt < 0) 1119 return ssi->irq_rt; 1120 1121 ret = devm_request_irq(&pdev->dev, ssi->irq_rt, 1122 &rz_ssi_interrupt, 0, 1123 dev_name(&pdev->dev), ssi); 1124 if (ret < 0) 1125 return dev_err_probe(&pdev->dev, ret, 1126 "irq request error (dma_rt)\n"); 1127 } else { 1128 if (ssi->irq_tx < 0) 1129 return ssi->irq_tx; 1130 1131 if (ssi->irq_rx < 0) 1132 return ssi->irq_rx; 1133 1134 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1135 &rz_ssi_interrupt, 0, 1136 dev_name(&pdev->dev), ssi); 1137 if (ret < 0) 1138 return dev_err_probe(&pdev->dev, ret, 1139 "irq request error (dma_tx)\n"); 1140 1141 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1142 &rz_ssi_interrupt, 0, 1143 dev_name(&pdev->dev), ssi); 1144 if (ret < 0) 1145 return dev_err_probe(&pdev->dev, ret, 1146 "irq request error (dma_rx)\n"); 1147 } 1148 } 1149 1150 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1151 if (IS_ERR(ssi->rstc)) { 1152 ret = PTR_ERR(ssi->rstc); 1153 goto err_reset; 1154 } 1155 1156 reset_control_deassert(ssi->rstc); 1157 pm_runtime_enable(&pdev->dev); 1158 ret = pm_runtime_resume_and_get(&pdev->dev); 1159 if (ret < 0) { 1160 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1161 goto err_pm; 1162 } 1163 1164 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1165 rz_ssi_soc_dai, 1166 ARRAY_SIZE(rz_ssi_soc_dai)); 1167 if (ret < 0) { 1168 dev_err(&pdev->dev, "failed to register snd component\n"); 1169 goto err_snd_soc; 1170 } 1171 1172 return 0; 1173 1174 err_snd_soc: 1175 pm_runtime_put(ssi->dev); 1176 err_pm: 1177 pm_runtime_disable(ssi->dev); 1178 reset_control_assert(ssi->rstc); 1179 err_reset: 1180 rz_ssi_release_dma_channels(ssi); 1181 1182 return ret; 1183 } 1184 1185 static void rz_ssi_remove(struct platform_device *pdev) 1186 { 1187 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1188 1189 rz_ssi_release_dma_channels(ssi); 1190 1191 pm_runtime_put(ssi->dev); 1192 pm_runtime_disable(ssi->dev); 1193 reset_control_assert(ssi->rstc); 1194 } 1195 1196 static const struct of_device_id rz_ssi_of_match[] = { 1197 { .compatible = "renesas,rz-ssi", }, 1198 {/* Sentinel */}, 1199 }; 1200 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1201 1202 static struct platform_driver rz_ssi_driver = { 1203 .driver = { 1204 .name = "rz-ssi-pcm-audio", 1205 .of_match_table = rz_ssi_of_match, 1206 }, 1207 .probe = rz_ssi_probe, 1208 .remove = rz_ssi_remove, 1209 }; 1210 1211 module_platform_driver(rz_ssi_driver); 1212 1213 MODULE_LICENSE("GPL v2"); 1214 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1215 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1216