1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/iopoll.h> 13 #include <linux/module.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/soc.h> 17 18 /* REGISTER OFFSET */ 19 #define SSICR 0x000 20 #define SSISR 0x004 21 #define SSIFCR 0x010 22 #define SSIFSR 0x014 23 #define SSIFTDR 0x018 24 #define SSIFRDR 0x01c 25 #define SSIOFR 0x020 26 #define SSISCR 0x024 27 28 /* SSI REGISTER BITS */ 29 #define SSICR_DWL(x) (((x) & 0x7) << 19) 30 #define SSICR_SWL(x) (((x) & 0x7) << 16) 31 32 #define SSICR_CKS BIT(30) 33 #define SSICR_TUIEN BIT(29) 34 #define SSICR_TOIEN BIT(28) 35 #define SSICR_RUIEN BIT(27) 36 #define SSICR_ROIEN BIT(26) 37 #define SSICR_MST BIT(14) 38 #define SSICR_BCKP BIT(13) 39 #define SSICR_LRCKP BIT(12) 40 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 41 #define SSICR_TEN BIT(1) 42 #define SSICR_REN BIT(0) 43 44 #define SSISR_TUIRQ BIT(29) 45 #define SSISR_TOIRQ BIT(28) 46 #define SSISR_RUIRQ BIT(27) 47 #define SSISR_ROIRQ BIT(26) 48 #define SSISR_IIRQ BIT(25) 49 50 #define SSIFCR_AUCKE BIT(31) 51 #define SSIFCR_SSIRST BIT(16) 52 #define SSIFCR_TIE BIT(3) 53 #define SSIFCR_RIE BIT(2) 54 #define SSIFCR_TFRST BIT(1) 55 #define SSIFCR_RFRST BIT(0) 56 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 57 58 #define SSIFSR_TDC_MASK 0x3f 59 #define SSIFSR_TDC_SHIFT 24 60 #define SSIFSR_RDC_MASK 0x3f 61 #define SSIFSR_RDC_SHIFT 8 62 63 #define SSIFSR_TDE BIT(16) 64 #define SSIFSR_RDF BIT(0) 65 66 #define SSIOFR_LRCONT BIT(8) 67 68 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 69 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 70 71 /* Pre allocated buffers sizes */ 72 #define PREALLOC_BUFFER (SZ_32K) 73 #define PREALLOC_BUFFER_MAX (SZ_32K) 74 75 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 76 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 77 #define SSI_CHAN_MIN 2 78 #define SSI_CHAN_MAX 2 79 #define SSI_FIFO_DEPTH 32 80 81 struct rz_ssi_priv; 82 83 struct rz_ssi_stream { 84 struct rz_ssi_priv *priv; 85 struct snd_pcm_substream *substream; 86 int fifo_sample_size; /* sample capacity of SSI FIFO */ 87 int dma_buffer_pos; /* The address for the next DMA descriptor */ 88 int period_counter; /* for keeping track of periods transferred */ 89 int sample_width; 90 int buffer_pos; /* current frame position in the buffer */ 91 int running; /* 0=stopped, 1=running */ 92 93 int uerr_num; 94 int oerr_num; 95 96 struct dma_chan *dma_ch; 97 98 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 99 }; 100 101 struct rz_ssi_priv { 102 void __iomem *base; 103 struct reset_control *rstc; 104 struct device *dev; 105 struct clk *sfr_clk; 106 struct clk *clk; 107 108 phys_addr_t phys; 109 int irq_int; 110 int irq_tx; 111 int irq_rx; 112 int irq_rt; 113 114 spinlock_t lock; 115 116 /* 117 * The SSI supports full-duplex transmission and reception. 118 * However, if an error occurs, channel reset (both transmission 119 * and reception reset) is required. 120 * So it is better to use as half-duplex (playing and recording 121 * should be done on separate channels). 122 */ 123 struct rz_ssi_stream playback; 124 struct rz_ssi_stream capture; 125 126 /* clock */ 127 unsigned long audio_mck; 128 unsigned long audio_clk_1; 129 unsigned long audio_clk_2; 130 131 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 132 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 133 bool dma_rt; 134 135 /* Full duplex communication support */ 136 struct { 137 unsigned int rate; 138 unsigned int channels; 139 unsigned int sample_width; 140 unsigned int sample_bits; 141 } hw_params_cache; 142 }; 143 144 static void rz_ssi_dma_complete(void *data); 145 146 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 147 { 148 writel(data, (priv->base + reg)); 149 } 150 151 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 152 { 153 return readl(priv->base + reg); 154 } 155 156 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 157 u32 bclr, u32 bset) 158 { 159 u32 val; 160 161 val = readl(priv->base + reg); 162 val = (val & ~bclr) | bset; 163 writel(val, (priv->base + reg)); 164 } 165 166 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream) 167 { 168 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 169 } 170 171 static inline struct rz_ssi_stream * 172 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 173 { 174 struct rz_ssi_stream *stream = &ssi->playback; 175 176 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 177 stream = &ssi->capture; 178 179 return stream; 180 } 181 182 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 183 { 184 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 185 } 186 187 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 188 struct snd_pcm_substream *substream) 189 { 190 struct rz_ssi_priv *ssi = strm->priv; 191 unsigned long flags; 192 193 spin_lock_irqsave(&ssi->lock, flags); 194 strm->substream = substream; 195 spin_unlock_irqrestore(&ssi->lock, flags); 196 } 197 198 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 199 struct rz_ssi_stream *strm) 200 { 201 unsigned long flags; 202 bool ret; 203 204 spin_lock_irqsave(&ssi->lock, flags); 205 ret = strm->substream && strm->substream->runtime; 206 spin_unlock_irqrestore(&ssi->lock, flags); 207 208 return ret; 209 } 210 211 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 212 { 213 return strm->substream && strm->running; 214 } 215 216 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 217 struct snd_pcm_substream *substream) 218 { 219 struct snd_pcm_runtime *runtime = substream->runtime; 220 221 rz_ssi_set_substream(strm, substream); 222 strm->sample_width = samples_to_bytes(runtime, 1); 223 strm->dma_buffer_pos = 0; 224 strm->period_counter = 0; 225 strm->buffer_pos = 0; 226 227 strm->oerr_num = 0; 228 strm->uerr_num = 0; 229 strm->running = 0; 230 231 /* fifo init */ 232 strm->fifo_sample_size = SSI_FIFO_DEPTH; 233 } 234 235 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 236 struct rz_ssi_stream *strm) 237 { 238 struct device *dev = ssi->dev; 239 240 rz_ssi_set_substream(strm, NULL); 241 242 if (strm->oerr_num > 0) 243 dev_info(dev, "overrun = %d\n", strm->oerr_num); 244 245 if (strm->uerr_num > 0) 246 dev_info(dev, "underrun = %d\n", strm->uerr_num); 247 } 248 249 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 250 unsigned int channels) 251 { 252 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 253 unsigned int channel_bits = 32; /* System Word Length */ 254 unsigned long bclk_rate = rate * channels * channel_bits; 255 unsigned int div; 256 unsigned int i; 257 u32 ssicr = 0; 258 u32 clk_ckdv; 259 260 /* Clear AUCKE so we can set MST */ 261 rz_ssi_reg_writel(ssi, SSIFCR, 0); 262 263 /* Continue to output LRCK pin even when idle */ 264 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 265 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 266 if (ssi->audio_clk_1 % bclk_rate) 267 ssi->audio_mck = ssi->audio_clk_2; 268 else 269 ssi->audio_mck = ssi->audio_clk_1; 270 } 271 272 /* Clock setting */ 273 ssicr |= SSICR_MST; 274 if (ssi->audio_mck == ssi->audio_clk_1) 275 ssicr |= SSICR_CKS; 276 if (ssi->bckp_rise) 277 ssicr |= SSICR_BCKP; 278 if (ssi->lrckp_fsync_fall) 279 ssicr |= SSICR_LRCKP; 280 281 /* Determine the clock divider */ 282 clk_ckdv = 0; 283 div = ssi->audio_mck / bclk_rate; 284 /* try to find an match */ 285 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 286 if (ckdv[i] == div) { 287 clk_ckdv = i; 288 break; 289 } 290 } 291 292 if (i == ARRAY_SIZE(ckdv)) { 293 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 294 return -EINVAL; 295 } 296 297 /* 298 * DWL: Data Word Length = 16 bits 299 * SWL: System Word Length = 32 bits 300 */ 301 ssicr |= SSICR_CKDV(clk_ckdv); 302 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 303 rz_ssi_reg_writel(ssi, SSICR, ssicr); 304 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 305 306 return 0; 307 } 308 309 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 310 { 311 u32 tmp; 312 int ret; 313 314 /* Disable irqs */ 315 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 316 SSICR_RUIEN | SSICR_ROIEN, 0); 317 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 318 319 /* Clear all error flags */ 320 rz_ssi_reg_mask_setl(ssi, SSISR, 321 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 322 SSISR_RUIRQ), 0); 323 324 /* Wait for idle */ 325 ret = readl_poll_timeout_atomic(ssi->base + SSISR, tmp, (tmp & SSISR_IIRQ), 1, 100); 326 if (ret) 327 dev_warn_ratelimited(ssi->dev, "timeout waiting for SSI idle\n"); 328 329 /* Hold FIFOs in reset */ 330 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 331 } 332 333 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 334 { 335 bool is_play = rz_ssi_stream_is_play(strm->substream); 336 bool is_full_duplex; 337 u32 ssicr, ssifcr; 338 339 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 340 rz_ssi_is_stream_running(&ssi->capture); 341 ssicr = rz_ssi_reg_readl(ssi, SSICR); 342 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 343 if (!is_full_duplex) { 344 ssifcr &= ~0xF; 345 } else { 346 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 347 rz_ssi_set_idle(ssi); 348 ssifcr &= ~SSIFCR_FIFO_RST; 349 } 350 351 /* FIFO interrupt thresholds */ 352 if (rz_ssi_is_dma_enabled(ssi)) 353 rz_ssi_reg_writel(ssi, SSISCR, 0); 354 else 355 rz_ssi_reg_writel(ssi, SSISCR, 356 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 357 SSISCR_RDFS(0)); 358 359 /* enable IRQ */ 360 if (is_play) { 361 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 362 ssifcr |= SSIFCR_TIE; 363 if (!is_full_duplex) 364 ssifcr |= SSIFCR_RFRST; 365 } else { 366 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 367 ssifcr |= SSIFCR_RIE; 368 if (!is_full_duplex) 369 ssifcr |= SSIFCR_TFRST; 370 } 371 372 rz_ssi_reg_writel(ssi, SSICR, ssicr); 373 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 374 375 /* Clear all error flags */ 376 rz_ssi_reg_mask_setl(ssi, SSISR, 377 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 378 SSISR_RUIRQ), 0); 379 380 strm->running = 1; 381 if (is_full_duplex) 382 ssicr |= SSICR_TEN | SSICR_REN; 383 else 384 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 385 386 rz_ssi_reg_writel(ssi, SSICR, ssicr); 387 388 return 0; 389 } 390 391 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 392 { 393 strm->running = 0; 394 395 if (rz_ssi_is_stream_running(&ssi->playback) || 396 rz_ssi_is_stream_running(&ssi->capture)) 397 return 0; 398 399 /* Disable TX/RX */ 400 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 401 402 /* Cancel all remaining DMA transactions */ 403 if (rz_ssi_is_dma_enabled(ssi)) { 404 if (ssi->playback.dma_ch) 405 dmaengine_terminate_async(ssi->playback.dma_ch); 406 if (ssi->capture.dma_ch) 407 dmaengine_terminate_async(ssi->capture.dma_ch); 408 } 409 410 rz_ssi_set_idle(ssi); 411 412 return 0; 413 } 414 415 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 416 { 417 struct snd_pcm_substream *substream = strm->substream; 418 struct snd_pcm_runtime *runtime; 419 int current_period; 420 421 if (!strm->running || !substream || !substream->runtime) 422 return; 423 424 runtime = substream->runtime; 425 strm->buffer_pos += frames; 426 WARN_ON(strm->buffer_pos > runtime->buffer_size); 427 428 /* ring buffer */ 429 if (strm->buffer_pos == runtime->buffer_size) 430 strm->buffer_pos = 0; 431 432 current_period = strm->buffer_pos / runtime->period_size; 433 if (strm->period_counter != current_period) { 434 snd_pcm_period_elapsed(strm->substream); 435 strm->period_counter = current_period; 436 } 437 } 438 439 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 440 { 441 struct snd_pcm_substream *substream = strm->substream; 442 struct snd_pcm_runtime *runtime; 443 u16 *buf; 444 int fifo_samples; 445 int frames_left; 446 int samples; 447 int i; 448 449 if (!rz_ssi_stream_is_valid(ssi, strm)) 450 return -EINVAL; 451 452 runtime = substream->runtime; 453 454 do { 455 /* frames left in this period */ 456 frames_left = runtime->period_size - 457 (strm->buffer_pos % runtime->period_size); 458 if (!frames_left) 459 frames_left = runtime->period_size; 460 461 /* Samples in RX FIFO */ 462 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 463 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 464 465 /* Only read full frames at a time */ 466 samples = 0; 467 while (frames_left && (fifo_samples >= runtime->channels)) { 468 samples += runtime->channels; 469 fifo_samples -= runtime->channels; 470 frames_left--; 471 } 472 473 /* not enough samples yet */ 474 if (!samples) 475 break; 476 477 /* calculate new buffer index */ 478 buf = (u16 *)runtime->dma_area; 479 buf += strm->buffer_pos * runtime->channels; 480 481 /* Note, only supports 16-bit samples */ 482 for (i = 0; i < samples; i++) 483 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 484 485 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 486 rz_ssi_pointer_update(strm, samples / runtime->channels); 487 } while (!frames_left && fifo_samples >= runtime->channels); 488 489 return 0; 490 } 491 492 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 493 { 494 struct snd_pcm_substream *substream = strm->substream; 495 struct snd_pcm_runtime *runtime = substream->runtime; 496 int sample_space; 497 int samples = 0; 498 int frames_left; 499 int i; 500 u32 ssifsr; 501 u16 *buf; 502 503 if (!rz_ssi_stream_is_valid(ssi, strm)) 504 return -EINVAL; 505 506 /* frames left in this period */ 507 frames_left = runtime->period_size - (strm->buffer_pos % 508 runtime->period_size); 509 if (frames_left == 0) 510 frames_left = runtime->period_size; 511 512 sample_space = strm->fifo_sample_size; 513 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 514 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 515 516 /* Only add full frames at a time */ 517 while (frames_left && (sample_space >= runtime->channels)) { 518 samples += runtime->channels; 519 sample_space -= runtime->channels; 520 frames_left--; 521 } 522 523 /* no space to send anything right now */ 524 if (samples == 0) 525 return 0; 526 527 /* calculate new buffer index */ 528 buf = (u16 *)(runtime->dma_area); 529 buf += strm->buffer_pos * runtime->channels; 530 531 /* Note, only supports 16-bit samples */ 532 for (i = 0; i < samples; i++) 533 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 534 535 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 536 rz_ssi_pointer_update(strm, samples / runtime->channels); 537 538 return 0; 539 } 540 541 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 542 { 543 struct rz_ssi_stream *strm_playback = NULL; 544 struct rz_ssi_stream *strm_capture = NULL; 545 struct rz_ssi_priv *ssi = data; 546 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 547 548 if (ssi->playback.substream) 549 strm_playback = &ssi->playback; 550 if (ssi->capture.substream) 551 strm_capture = &ssi->capture; 552 553 if (!strm_playback && !strm_capture) 554 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 555 556 if (irq == ssi->irq_int) { /* error or idle */ 557 bool is_stopped = false; 558 int i, count; 559 560 if (rz_ssi_is_dma_enabled(ssi)) 561 count = 4; 562 else 563 count = 1; 564 565 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 566 is_stopped = true; 567 568 if (ssi->capture.substream && is_stopped) { 569 if (ssisr & SSISR_RUIRQ) 570 strm_capture->uerr_num++; 571 if (ssisr & SSISR_ROIRQ) 572 strm_capture->oerr_num++; 573 574 rz_ssi_stop(ssi, strm_capture); 575 } 576 577 if (ssi->playback.substream && is_stopped) { 578 if (ssisr & SSISR_TUIRQ) 579 strm_playback->uerr_num++; 580 if (ssisr & SSISR_TOIRQ) 581 strm_playback->oerr_num++; 582 583 rz_ssi_stop(ssi, strm_playback); 584 } 585 586 /* Clear all flags */ 587 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 588 SSISR_ROIRQ | SSISR_RUIRQ, 0); 589 590 /* Add/remove more data */ 591 if (ssi->capture.substream && is_stopped) { 592 for (i = 0; i < count; i++) 593 strm_capture->transfer(ssi, strm_capture); 594 } 595 596 if (ssi->playback.substream && is_stopped) { 597 for (i = 0; i < count; i++) 598 strm_playback->transfer(ssi, strm_playback); 599 } 600 601 /* Resume */ 602 if (ssi->playback.substream && is_stopped) 603 rz_ssi_start(ssi, &ssi->playback); 604 if (ssi->capture.substream && is_stopped) 605 rz_ssi_start(ssi, &ssi->capture); 606 } 607 608 if (!rz_ssi_is_stream_running(&ssi->playback) && 609 !rz_ssi_is_stream_running(&ssi->capture)) 610 return IRQ_HANDLED; 611 612 /* tx data empty */ 613 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 614 strm_playback->transfer(ssi, &ssi->playback); 615 616 /* rx data full */ 617 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 618 strm_capture->transfer(ssi, &ssi->capture); 619 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 620 } 621 622 if (irq == ssi->irq_rt) { 623 if (ssi->playback.substream) { 624 strm_playback->transfer(ssi, &ssi->playback); 625 } else { 626 strm_capture->transfer(ssi, &ssi->capture); 627 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 628 } 629 } 630 631 return IRQ_HANDLED; 632 } 633 634 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 635 struct dma_chan *dma_ch, bool is_play) 636 { 637 struct dma_slave_config cfg; 638 639 memset(&cfg, 0, sizeof(cfg)); 640 641 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 642 cfg.dst_addr = ssi->phys + SSIFTDR; 643 cfg.src_addr = ssi->phys + SSIFRDR; 644 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 645 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 646 647 return dmaengine_slave_config(dma_ch, &cfg); 648 } 649 650 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 651 struct rz_ssi_stream *strm) 652 { 653 struct snd_pcm_substream *substream = strm->substream; 654 struct dma_async_tx_descriptor *desc; 655 struct snd_pcm_runtime *runtime; 656 enum dma_transfer_direction dir; 657 u32 dma_paddr, dma_size; 658 int amount; 659 660 if (!rz_ssi_stream_is_valid(ssi, strm)) 661 return -EINVAL; 662 663 runtime = substream->runtime; 664 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 665 /* 666 * Stream is ending, so do not queue up any more DMA 667 * transfers otherwise we play partial sound clips 668 * because we can't shut off the DMA quick enough. 669 */ 670 return 0; 671 672 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 673 674 /* Always transfer 1 period */ 675 amount = runtime->period_size; 676 677 /* DMA physical address and size */ 678 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 679 strm->dma_buffer_pos); 680 dma_size = frames_to_bytes(runtime, amount); 681 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 682 dir, 683 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 684 if (!desc) { 685 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 686 return -ENOMEM; 687 } 688 689 desc->callback = rz_ssi_dma_complete; 690 desc->callback_param = strm; 691 692 if (dmaengine_submit(desc) < 0) { 693 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 694 return -EIO; 695 } 696 697 /* Update DMA pointer */ 698 strm->dma_buffer_pos += amount; 699 if (strm->dma_buffer_pos >= runtime->buffer_size) 700 strm->dma_buffer_pos = 0; 701 702 /* Start DMA */ 703 dma_async_issue_pending(strm->dma_ch); 704 705 return 0; 706 } 707 708 static void rz_ssi_dma_complete(void *data) 709 { 710 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 711 712 if (!strm->running || !strm->substream || !strm->substream->runtime) 713 return; 714 715 /* Note that next DMA transaction has probably already started */ 716 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 717 718 /* Queue up another DMA transaction */ 719 rz_ssi_dma_transfer(strm->priv, strm); 720 } 721 722 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 723 { 724 if (ssi->playback.dma_ch) { 725 dma_release_channel(ssi->playback.dma_ch); 726 ssi->playback.dma_ch = NULL; 727 if (ssi->dma_rt) 728 ssi->dma_rt = false; 729 } 730 731 if (ssi->capture.dma_ch) { 732 dma_release_channel(ssi->capture.dma_ch); 733 ssi->capture.dma_ch = NULL; 734 } 735 } 736 737 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 738 { 739 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 740 if (IS_ERR(ssi->playback.dma_ch)) 741 ssi->playback.dma_ch = NULL; 742 743 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 744 if (IS_ERR(ssi->capture.dma_ch)) 745 ssi->capture.dma_ch = NULL; 746 747 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 748 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 749 if (IS_ERR(ssi->playback.dma_ch)) { 750 ssi->playback.dma_ch = NULL; 751 goto no_dma; 752 } 753 754 ssi->dma_rt = true; 755 } 756 757 if (!rz_ssi_is_dma_enabled(ssi)) 758 goto no_dma; 759 760 if (ssi->playback.dma_ch && 761 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 762 goto no_dma; 763 764 if (ssi->capture.dma_ch && 765 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 766 goto no_dma; 767 768 return 0; 769 770 no_dma: 771 rz_ssi_release_dma_channels(ssi); 772 773 return -ENODEV; 774 } 775 776 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 777 struct snd_soc_dai *dai) 778 { 779 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 780 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 781 int ret = 0, i, num_transfer = 1; 782 783 switch (cmd) { 784 case SNDRV_PCM_TRIGGER_START: 785 /* Soft Reset */ 786 if (!rz_ssi_is_stream_running(&ssi->playback) && 787 !rz_ssi_is_stream_running(&ssi->capture)) { 788 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 789 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 790 udelay(5); 791 } 792 793 rz_ssi_stream_init(strm, substream); 794 795 if (ssi->dma_rt) { 796 bool is_playback; 797 798 is_playback = rz_ssi_stream_is_play(substream); 799 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 800 is_playback); 801 /* Fallback to pio */ 802 if (ret < 0) { 803 ssi->playback.transfer = rz_ssi_pio_send; 804 ssi->capture.transfer = rz_ssi_pio_recv; 805 rz_ssi_release_dma_channels(ssi); 806 } 807 } 808 809 /* For DMA, queue up multiple DMA descriptors */ 810 if (rz_ssi_is_dma_enabled(ssi)) 811 num_transfer = 4; 812 813 for (i = 0; i < num_transfer; i++) { 814 ret = strm->transfer(ssi, strm); 815 if (ret) 816 goto done; 817 } 818 819 ret = rz_ssi_start(ssi, strm); 820 break; 821 case SNDRV_PCM_TRIGGER_STOP: 822 rz_ssi_stop(ssi, strm); 823 rz_ssi_stream_quit(ssi, strm); 824 break; 825 } 826 827 done: 828 return ret; 829 } 830 831 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 832 { 833 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 834 835 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 836 case SND_SOC_DAIFMT_BP_FP: 837 break; 838 default: 839 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 840 return -EINVAL; 841 } 842 843 /* 844 * set clock polarity 845 * 846 * "normal" BCLK = Signal is available at rising edge of BCLK 847 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 848 */ 849 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 850 case SND_SOC_DAIFMT_NB_NF: 851 ssi->bckp_rise = false; 852 ssi->lrckp_fsync_fall = false; 853 break; 854 case SND_SOC_DAIFMT_NB_IF: 855 ssi->bckp_rise = false; 856 ssi->lrckp_fsync_fall = true; 857 break; 858 case SND_SOC_DAIFMT_IB_NF: 859 ssi->bckp_rise = true; 860 ssi->lrckp_fsync_fall = false; 861 break; 862 case SND_SOC_DAIFMT_IB_IF: 863 ssi->bckp_rise = true; 864 ssi->lrckp_fsync_fall = true; 865 break; 866 default: 867 return -EINVAL; 868 } 869 870 /* only i2s support */ 871 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 872 case SND_SOC_DAIFMT_I2S: 873 break; 874 default: 875 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 876 return -EINVAL; 877 } 878 879 return 0; 880 } 881 882 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 883 unsigned int channels, 884 unsigned int sample_width, 885 unsigned int sample_bits) 886 { 887 if (ssi->hw_params_cache.rate != rate || 888 ssi->hw_params_cache.channels != channels || 889 ssi->hw_params_cache.sample_width != sample_width || 890 ssi->hw_params_cache.sample_bits != sample_bits) 891 return false; 892 893 return true; 894 } 895 896 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 897 unsigned int channels, 898 unsigned int sample_width, 899 unsigned int sample_bits) 900 { 901 ssi->hw_params_cache.rate = rate; 902 ssi->hw_params_cache.channels = channels; 903 ssi->hw_params_cache.sample_width = sample_width; 904 ssi->hw_params_cache.sample_bits = sample_bits; 905 } 906 907 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 908 struct snd_pcm_hw_params *params, 909 struct snd_soc_dai *dai) 910 { 911 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 912 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 913 unsigned int sample_bits = hw_param_interval(params, 914 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 915 unsigned int channels = params_channels(params); 916 unsigned int rate = params_rate(params); 917 918 if (sample_bits != 16) { 919 dev_err(ssi->dev, "Unsupported sample width: %d\n", 920 sample_bits); 921 return -EINVAL; 922 } 923 924 if (channels != 2) { 925 dev_err(ssi->dev, "Number of channels not matched: %d\n", 926 channels); 927 return -EINVAL; 928 } 929 930 if (rz_ssi_is_stream_running(&ssi->playback) || 931 rz_ssi_is_stream_running(&ssi->capture)) { 932 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 933 strm->sample_width, sample_bits)) 934 return 0; 935 936 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 937 return -EINVAL; 938 } 939 940 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 941 sample_bits); 942 943 return rz_ssi_clk_setup(ssi, rate, channels); 944 } 945 946 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 947 .trigger = rz_ssi_dai_trigger, 948 .set_fmt = rz_ssi_dai_set_fmt, 949 .hw_params = rz_ssi_dai_hw_params, 950 }; 951 952 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 953 .info = SNDRV_PCM_INFO_INTERLEAVED | 954 SNDRV_PCM_INFO_MMAP | 955 SNDRV_PCM_INFO_MMAP_VALID, 956 .buffer_bytes_max = PREALLOC_BUFFER, 957 .period_bytes_min = 32, 958 .period_bytes_max = 8192, 959 .channels_min = SSI_CHAN_MIN, 960 .channels_max = SSI_CHAN_MAX, 961 .periods_min = 1, 962 .periods_max = 32, 963 .fifo_size = 32 * 2, 964 }; 965 966 static int rz_ssi_pcm_open(struct snd_soc_component *component, 967 struct snd_pcm_substream *substream) 968 { 969 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 970 971 return snd_pcm_hw_constraint_integer(substream->runtime, 972 SNDRV_PCM_HW_PARAM_PERIODS); 973 } 974 975 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 976 struct snd_pcm_substream *substream) 977 { 978 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 979 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 980 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 981 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 982 983 return strm->buffer_pos; 984 } 985 986 static int rz_ssi_pcm_new(struct snd_soc_component *component, 987 struct snd_soc_pcm_runtime *rtd) 988 { 989 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 990 rtd->card->snd_card->dev, 991 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 992 return 0; 993 } 994 995 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 996 { 997 .name = "rz-ssi-dai", 998 .playback = { 999 .rates = SSI_RATES, 1000 .formats = SSI_FMTS, 1001 .channels_min = SSI_CHAN_MIN, 1002 .channels_max = SSI_CHAN_MAX, 1003 }, 1004 .capture = { 1005 .rates = SSI_RATES, 1006 .formats = SSI_FMTS, 1007 .channels_min = SSI_CHAN_MIN, 1008 .channels_max = SSI_CHAN_MAX, 1009 }, 1010 .ops = &rz_ssi_dai_ops, 1011 }, 1012 }; 1013 1014 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1015 .name = "rz-ssi", 1016 .open = rz_ssi_pcm_open, 1017 .pointer = rz_ssi_pcm_pointer, 1018 .pcm_construct = rz_ssi_pcm_new, 1019 .legacy_dai_naming = 1, 1020 }; 1021 1022 static int rz_ssi_probe(struct platform_device *pdev) 1023 { 1024 struct rz_ssi_priv *ssi; 1025 struct clk *audio_clk; 1026 struct resource *res; 1027 int ret; 1028 1029 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 1030 if (!ssi) 1031 return -ENOMEM; 1032 1033 ssi->dev = &pdev->dev; 1034 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1035 if (IS_ERR(ssi->base)) 1036 return PTR_ERR(ssi->base); 1037 1038 ssi->phys = res->start; 1039 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 1040 if (IS_ERR(ssi->clk)) 1041 return PTR_ERR(ssi->clk); 1042 1043 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 1044 if (IS_ERR(ssi->sfr_clk)) 1045 return PTR_ERR(ssi->sfr_clk); 1046 1047 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 1048 if (IS_ERR(audio_clk)) 1049 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1050 "no audio clk1"); 1051 1052 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1053 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 1054 if (IS_ERR(audio_clk)) 1055 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1056 "no audio clk2"); 1057 1058 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1059 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1060 return dev_err_probe(&pdev->dev, -EINVAL, 1061 "no audio clk1 or audio clk2"); 1062 1063 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1064 1065 /* Detect DMA support */ 1066 ret = rz_ssi_dma_request(ssi, &pdev->dev); 1067 if (ret < 0) { 1068 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1069 ssi->playback.transfer = rz_ssi_pio_send; 1070 ssi->capture.transfer = rz_ssi_pio_recv; 1071 } else { 1072 dev_info(&pdev->dev, "DMA enabled"); 1073 ssi->playback.transfer = rz_ssi_dma_transfer; 1074 ssi->capture.transfer = rz_ssi_dma_transfer; 1075 } 1076 1077 ssi->playback.priv = ssi; 1078 ssi->capture.priv = ssi; 1079 1080 spin_lock_init(&ssi->lock); 1081 dev_set_drvdata(&pdev->dev, ssi); 1082 1083 /* Error Interrupt */ 1084 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1085 if (ssi->irq_int < 0) { 1086 rz_ssi_release_dma_channels(ssi); 1087 return ssi->irq_int; 1088 } 1089 1090 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 1091 0, dev_name(&pdev->dev), ssi); 1092 if (ret < 0) { 1093 rz_ssi_release_dma_channels(ssi); 1094 return dev_err_probe(&pdev->dev, ret, 1095 "irq request error (int_req)\n"); 1096 } 1097 1098 if (!rz_ssi_is_dma_enabled(ssi)) { 1099 /* Tx and Rx interrupts (pio only) */ 1100 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1101 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1102 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1103 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1104 if (ssi->irq_rt < 0) 1105 return ssi->irq_rt; 1106 1107 ret = devm_request_irq(&pdev->dev, ssi->irq_rt, 1108 &rz_ssi_interrupt, 0, 1109 dev_name(&pdev->dev), ssi); 1110 if (ret < 0) 1111 return dev_err_probe(&pdev->dev, ret, 1112 "irq request error (dma_rt)\n"); 1113 } else { 1114 if (ssi->irq_tx < 0) 1115 return ssi->irq_tx; 1116 1117 if (ssi->irq_rx < 0) 1118 return ssi->irq_rx; 1119 1120 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1121 &rz_ssi_interrupt, 0, 1122 dev_name(&pdev->dev), ssi); 1123 if (ret < 0) 1124 return dev_err_probe(&pdev->dev, ret, 1125 "irq request error (dma_tx)\n"); 1126 1127 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1128 &rz_ssi_interrupt, 0, 1129 dev_name(&pdev->dev), ssi); 1130 if (ret < 0) 1131 return dev_err_probe(&pdev->dev, ret, 1132 "irq request error (dma_rx)\n"); 1133 } 1134 } 1135 1136 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1137 if (IS_ERR(ssi->rstc)) { 1138 ret = PTR_ERR(ssi->rstc); 1139 goto err_reset; 1140 } 1141 1142 reset_control_deassert(ssi->rstc); 1143 pm_runtime_enable(&pdev->dev); 1144 ret = pm_runtime_resume_and_get(&pdev->dev); 1145 if (ret < 0) { 1146 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1147 goto err_pm; 1148 } 1149 1150 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1151 rz_ssi_soc_dai, 1152 ARRAY_SIZE(rz_ssi_soc_dai)); 1153 if (ret < 0) { 1154 dev_err(&pdev->dev, "failed to register snd component\n"); 1155 goto err_snd_soc; 1156 } 1157 1158 return 0; 1159 1160 err_snd_soc: 1161 pm_runtime_put(ssi->dev); 1162 err_pm: 1163 pm_runtime_disable(ssi->dev); 1164 reset_control_assert(ssi->rstc); 1165 err_reset: 1166 rz_ssi_release_dma_channels(ssi); 1167 1168 return ret; 1169 } 1170 1171 static void rz_ssi_remove(struct platform_device *pdev) 1172 { 1173 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1174 1175 rz_ssi_release_dma_channels(ssi); 1176 1177 pm_runtime_put(ssi->dev); 1178 pm_runtime_disable(ssi->dev); 1179 reset_control_assert(ssi->rstc); 1180 } 1181 1182 static const struct of_device_id rz_ssi_of_match[] = { 1183 { .compatible = "renesas,rz-ssi", }, 1184 {/* Sentinel */}, 1185 }; 1186 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1187 1188 static struct platform_driver rz_ssi_driver = { 1189 .driver = { 1190 .name = "rz-ssi-pcm-audio", 1191 .of_match_table = rz_ssi_of_match, 1192 }, 1193 .probe = rz_ssi_probe, 1194 .remove = rz_ssi_remove, 1195 }; 1196 1197 module_platform_driver(rz_ssi_driver); 1198 1199 MODULE_LICENSE("GPL v2"); 1200 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1201 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1202