1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Renesas RZ/G2L ASoC Serial Sound Interface (SSIF-2) Driver 4 // 5 // Copyright (C) 2021 Renesas Electronics Corp. 6 // Copyright (C) 2019 Chris Brandt. 7 // 8 9 #include <linux/clk.h> 10 #include <linux/dmaengine.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 #include <sound/soc.h> 16 17 /* REGISTER OFFSET */ 18 #define SSICR 0x000 19 #define SSISR 0x004 20 #define SSIFCR 0x010 21 #define SSIFSR 0x014 22 #define SSIFTDR 0x018 23 #define SSIFRDR 0x01c 24 #define SSIOFR 0x020 25 #define SSISCR 0x024 26 27 /* SSI REGISTER BITS */ 28 #define SSICR_DWL(x) (((x) & 0x7) << 19) 29 #define SSICR_SWL(x) (((x) & 0x7) << 16) 30 31 #define SSICR_CKS BIT(30) 32 #define SSICR_TUIEN BIT(29) 33 #define SSICR_TOIEN BIT(28) 34 #define SSICR_RUIEN BIT(27) 35 #define SSICR_ROIEN BIT(26) 36 #define SSICR_MST BIT(14) 37 #define SSICR_BCKP BIT(13) 38 #define SSICR_LRCKP BIT(12) 39 #define SSICR_CKDV(x) (((x) & 0xf) << 4) 40 #define SSICR_TEN BIT(1) 41 #define SSICR_REN BIT(0) 42 43 #define SSISR_TUIRQ BIT(29) 44 #define SSISR_TOIRQ BIT(28) 45 #define SSISR_RUIRQ BIT(27) 46 #define SSISR_ROIRQ BIT(26) 47 #define SSISR_IIRQ BIT(25) 48 49 #define SSIFCR_AUCKE BIT(31) 50 #define SSIFCR_SSIRST BIT(16) 51 #define SSIFCR_TIE BIT(3) 52 #define SSIFCR_RIE BIT(2) 53 #define SSIFCR_TFRST BIT(1) 54 #define SSIFCR_RFRST BIT(0) 55 #define SSIFCR_FIFO_RST (SSIFCR_TFRST | SSIFCR_RFRST) 56 57 #define SSIFSR_TDC_MASK 0x3f 58 #define SSIFSR_TDC_SHIFT 24 59 #define SSIFSR_RDC_MASK 0x3f 60 #define SSIFSR_RDC_SHIFT 8 61 62 #define SSIFSR_TDE BIT(16) 63 #define SSIFSR_RDF BIT(0) 64 65 #define SSIOFR_LRCONT BIT(8) 66 67 #define SSISCR_TDES(x) (((x) & 0x1f) << 8) 68 #define SSISCR_RDFS(x) (((x) & 0x1f) << 0) 69 70 /* Pre allocated buffers sizes */ 71 #define PREALLOC_BUFFER (SZ_32K) 72 #define PREALLOC_BUFFER_MAX (SZ_32K) 73 74 #define SSI_RATES SNDRV_PCM_RATE_8000_48000 /* 8k-48kHz */ 75 #define SSI_FMTS SNDRV_PCM_FMTBIT_S16_LE 76 #define SSI_CHAN_MIN 2 77 #define SSI_CHAN_MAX 2 78 #define SSI_FIFO_DEPTH 32 79 80 struct rz_ssi_priv; 81 82 struct rz_ssi_stream { 83 struct rz_ssi_priv *priv; 84 struct snd_pcm_substream *substream; 85 int fifo_sample_size; /* sample capacity of SSI FIFO */ 86 int dma_buffer_pos; /* The address for the next DMA descriptor */ 87 int period_counter; /* for keeping track of periods transferred */ 88 int sample_width; 89 int buffer_pos; /* current frame position in the buffer */ 90 int running; /* 0=stopped, 1=running */ 91 92 int uerr_num; 93 int oerr_num; 94 95 struct dma_chan *dma_ch; 96 97 int (*transfer)(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm); 98 }; 99 100 struct rz_ssi_priv { 101 void __iomem *base; 102 struct reset_control *rstc; 103 struct device *dev; 104 struct clk *sfr_clk; 105 struct clk *clk; 106 107 phys_addr_t phys; 108 int irq_int; 109 int irq_tx; 110 int irq_rx; 111 int irq_rt; 112 113 spinlock_t lock; 114 115 /* 116 * The SSI supports full-duplex transmission and reception. 117 * However, if an error occurs, channel reset (both transmission 118 * and reception reset) is required. 119 * So it is better to use as half-duplex (playing and recording 120 * should be done on separate channels). 121 */ 122 struct rz_ssi_stream playback; 123 struct rz_ssi_stream capture; 124 125 /* clock */ 126 unsigned long audio_mck; 127 unsigned long audio_clk_1; 128 unsigned long audio_clk_2; 129 130 bool lrckp_fsync_fall; /* LR clock polarity (SSICR.LRCKP) */ 131 bool bckp_rise; /* Bit clock polarity (SSICR.BCKP) */ 132 bool dma_rt; 133 134 /* Full duplex communication support */ 135 struct { 136 unsigned int rate; 137 unsigned int channels; 138 unsigned int sample_width; 139 unsigned int sample_bits; 140 } hw_params_cache; 141 }; 142 143 static void rz_ssi_dma_complete(void *data); 144 145 static void rz_ssi_reg_writel(struct rz_ssi_priv *priv, uint reg, u32 data) 146 { 147 writel(data, (priv->base + reg)); 148 } 149 150 static u32 rz_ssi_reg_readl(struct rz_ssi_priv *priv, uint reg) 151 { 152 return readl(priv->base + reg); 153 } 154 155 static void rz_ssi_reg_mask_setl(struct rz_ssi_priv *priv, uint reg, 156 u32 bclr, u32 bset) 157 { 158 u32 val; 159 160 val = readl(priv->base + reg); 161 val = (val & ~bclr) | bset; 162 writel(val, (priv->base + reg)); 163 } 164 165 static inline bool rz_ssi_stream_is_play(struct snd_pcm_substream *substream) 166 { 167 return substream->stream == SNDRV_PCM_STREAM_PLAYBACK; 168 } 169 170 static inline struct rz_ssi_stream * 171 rz_ssi_stream_get(struct rz_ssi_priv *ssi, struct snd_pcm_substream *substream) 172 { 173 struct rz_ssi_stream *stream = &ssi->playback; 174 175 if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) 176 stream = &ssi->capture; 177 178 return stream; 179 } 180 181 static inline bool rz_ssi_is_dma_enabled(struct rz_ssi_priv *ssi) 182 { 183 return (ssi->playback.dma_ch && (ssi->dma_rt || ssi->capture.dma_ch)); 184 } 185 186 static void rz_ssi_set_substream(struct rz_ssi_stream *strm, 187 struct snd_pcm_substream *substream) 188 { 189 struct rz_ssi_priv *ssi = strm->priv; 190 unsigned long flags; 191 192 spin_lock_irqsave(&ssi->lock, flags); 193 strm->substream = substream; 194 spin_unlock_irqrestore(&ssi->lock, flags); 195 } 196 197 static bool rz_ssi_stream_is_valid(struct rz_ssi_priv *ssi, 198 struct rz_ssi_stream *strm) 199 { 200 unsigned long flags; 201 bool ret; 202 203 spin_lock_irqsave(&ssi->lock, flags); 204 ret = strm->substream && strm->substream->runtime; 205 spin_unlock_irqrestore(&ssi->lock, flags); 206 207 return ret; 208 } 209 210 static inline bool rz_ssi_is_stream_running(struct rz_ssi_stream *strm) 211 { 212 return strm->substream && strm->running; 213 } 214 215 static void rz_ssi_stream_init(struct rz_ssi_stream *strm, 216 struct snd_pcm_substream *substream) 217 { 218 struct snd_pcm_runtime *runtime = substream->runtime; 219 220 rz_ssi_set_substream(strm, substream); 221 strm->sample_width = samples_to_bytes(runtime, 1); 222 strm->dma_buffer_pos = 0; 223 strm->period_counter = 0; 224 strm->buffer_pos = 0; 225 226 strm->oerr_num = 0; 227 strm->uerr_num = 0; 228 strm->running = 0; 229 230 /* fifo init */ 231 strm->fifo_sample_size = SSI_FIFO_DEPTH; 232 } 233 234 static void rz_ssi_stream_quit(struct rz_ssi_priv *ssi, 235 struct rz_ssi_stream *strm) 236 { 237 struct device *dev = ssi->dev; 238 239 rz_ssi_set_substream(strm, NULL); 240 241 if (strm->oerr_num > 0) 242 dev_info(dev, "overrun = %d\n", strm->oerr_num); 243 244 if (strm->uerr_num > 0) 245 dev_info(dev, "underrun = %d\n", strm->uerr_num); 246 } 247 248 static int rz_ssi_clk_setup(struct rz_ssi_priv *ssi, unsigned int rate, 249 unsigned int channels) 250 { 251 static u8 ckdv[] = { 1, 2, 4, 8, 16, 32, 64, 128, 6, 12, 24, 48, 96 }; 252 unsigned int channel_bits = 32; /* System Word Length */ 253 unsigned long bclk_rate = rate * channels * channel_bits; 254 unsigned int div; 255 unsigned int i; 256 u32 ssicr = 0; 257 u32 clk_ckdv; 258 259 /* Clear AUCKE so we can set MST */ 260 rz_ssi_reg_writel(ssi, SSIFCR, 0); 261 262 /* Continue to output LRCK pin even when idle */ 263 rz_ssi_reg_writel(ssi, SSIOFR, SSIOFR_LRCONT); 264 if (ssi->audio_clk_1 && ssi->audio_clk_2) { 265 if (ssi->audio_clk_1 % bclk_rate) 266 ssi->audio_mck = ssi->audio_clk_2; 267 else 268 ssi->audio_mck = ssi->audio_clk_1; 269 } 270 271 /* Clock setting */ 272 ssicr |= SSICR_MST; 273 if (ssi->audio_mck == ssi->audio_clk_1) 274 ssicr |= SSICR_CKS; 275 if (ssi->bckp_rise) 276 ssicr |= SSICR_BCKP; 277 if (ssi->lrckp_fsync_fall) 278 ssicr |= SSICR_LRCKP; 279 280 /* Determine the clock divider */ 281 clk_ckdv = 0; 282 div = ssi->audio_mck / bclk_rate; 283 /* try to find an match */ 284 for (i = 0; i < ARRAY_SIZE(ckdv); i++) { 285 if (ckdv[i] == div) { 286 clk_ckdv = i; 287 break; 288 } 289 } 290 291 if (i == ARRAY_SIZE(ckdv)) { 292 dev_err(ssi->dev, "Rate not divisible by audio clock source\n"); 293 return -EINVAL; 294 } 295 296 /* 297 * DWL: Data Word Length = 16 bits 298 * SWL: System Word Length = 32 bits 299 */ 300 ssicr |= SSICR_CKDV(clk_ckdv); 301 ssicr |= SSICR_DWL(1) | SSICR_SWL(3); 302 rz_ssi_reg_writel(ssi, SSICR, ssicr); 303 rz_ssi_reg_writel(ssi, SSIFCR, SSIFCR_AUCKE | SSIFCR_FIFO_RST); 304 305 return 0; 306 } 307 308 static void rz_ssi_set_idle(struct rz_ssi_priv *ssi) 309 { 310 int timeout; 311 312 /* Disable irqs */ 313 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TUIEN | SSICR_TOIEN | 314 SSICR_RUIEN | SSICR_ROIEN, 0); 315 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_TIE | SSIFCR_RIE, 0); 316 317 /* Clear all error flags */ 318 rz_ssi_reg_mask_setl(ssi, SSISR, 319 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 320 SSISR_RUIRQ), 0); 321 322 /* Wait for idle */ 323 timeout = 100; 324 while (--timeout) { 325 if (rz_ssi_reg_readl(ssi, SSISR) & SSISR_IIRQ) 326 break; 327 udelay(1); 328 } 329 330 if (!timeout) 331 dev_info(ssi->dev, "timeout waiting for SSI idle\n"); 332 333 /* Hold FIFOs in reset */ 334 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_FIFO_RST); 335 } 336 337 static int rz_ssi_start(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 338 { 339 bool is_play = rz_ssi_stream_is_play(strm->substream); 340 bool is_full_duplex; 341 u32 ssicr, ssifcr; 342 343 is_full_duplex = rz_ssi_is_stream_running(&ssi->playback) || 344 rz_ssi_is_stream_running(&ssi->capture); 345 ssicr = rz_ssi_reg_readl(ssi, SSICR); 346 ssifcr = rz_ssi_reg_readl(ssi, SSIFCR); 347 if (!is_full_duplex) { 348 ssifcr &= ~0xF; 349 } else { 350 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 351 rz_ssi_set_idle(ssi); 352 ssifcr &= ~SSIFCR_FIFO_RST; 353 } 354 355 /* FIFO interrupt thresholds */ 356 if (rz_ssi_is_dma_enabled(ssi)) 357 rz_ssi_reg_writel(ssi, SSISCR, 0); 358 else 359 rz_ssi_reg_writel(ssi, SSISCR, 360 SSISCR_TDES(strm->fifo_sample_size / 2 - 1) | 361 SSISCR_RDFS(0)); 362 363 /* enable IRQ */ 364 if (is_play) { 365 ssicr |= SSICR_TUIEN | SSICR_TOIEN; 366 ssifcr |= SSIFCR_TIE; 367 if (!is_full_duplex) 368 ssifcr |= SSIFCR_RFRST; 369 } else { 370 ssicr |= SSICR_RUIEN | SSICR_ROIEN; 371 ssifcr |= SSIFCR_RIE; 372 if (!is_full_duplex) 373 ssifcr |= SSIFCR_TFRST; 374 } 375 376 rz_ssi_reg_writel(ssi, SSICR, ssicr); 377 rz_ssi_reg_writel(ssi, SSIFCR, ssifcr); 378 379 /* Clear all error flags */ 380 rz_ssi_reg_mask_setl(ssi, SSISR, 381 (SSISR_TOIRQ | SSISR_TUIRQ | SSISR_ROIRQ | 382 SSISR_RUIRQ), 0); 383 384 strm->running = 1; 385 if (is_full_duplex) 386 ssicr |= SSICR_TEN | SSICR_REN; 387 else 388 ssicr |= is_play ? SSICR_TEN : SSICR_REN; 389 390 rz_ssi_reg_writel(ssi, SSICR, ssicr); 391 392 return 0; 393 } 394 395 static int rz_ssi_stop(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 396 { 397 strm->running = 0; 398 399 if (rz_ssi_is_stream_running(&ssi->playback) || 400 rz_ssi_is_stream_running(&ssi->capture)) 401 return 0; 402 403 /* Disable TX/RX */ 404 rz_ssi_reg_mask_setl(ssi, SSICR, SSICR_TEN | SSICR_REN, 0); 405 406 /* Cancel all remaining DMA transactions */ 407 if (rz_ssi_is_dma_enabled(ssi)) { 408 if (ssi->playback.dma_ch) 409 dmaengine_terminate_async(ssi->playback.dma_ch); 410 if (ssi->capture.dma_ch) 411 dmaengine_terminate_async(ssi->capture.dma_ch); 412 } 413 414 rz_ssi_set_idle(ssi); 415 416 return 0; 417 } 418 419 static void rz_ssi_pointer_update(struct rz_ssi_stream *strm, int frames) 420 { 421 struct snd_pcm_substream *substream = strm->substream; 422 struct snd_pcm_runtime *runtime; 423 int current_period; 424 425 if (!strm->running || !substream || !substream->runtime) 426 return; 427 428 runtime = substream->runtime; 429 strm->buffer_pos += frames; 430 WARN_ON(strm->buffer_pos > runtime->buffer_size); 431 432 /* ring buffer */ 433 if (strm->buffer_pos == runtime->buffer_size) 434 strm->buffer_pos = 0; 435 436 current_period = strm->buffer_pos / runtime->period_size; 437 if (strm->period_counter != current_period) { 438 snd_pcm_period_elapsed(strm->substream); 439 strm->period_counter = current_period; 440 } 441 } 442 443 static int rz_ssi_pio_recv(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 444 { 445 struct snd_pcm_substream *substream = strm->substream; 446 struct snd_pcm_runtime *runtime; 447 u16 *buf; 448 int fifo_samples; 449 int frames_left; 450 int samples; 451 int i; 452 453 if (!rz_ssi_stream_is_valid(ssi, strm)) 454 return -EINVAL; 455 456 runtime = substream->runtime; 457 458 do { 459 /* frames left in this period */ 460 frames_left = runtime->period_size - 461 (strm->buffer_pos % runtime->period_size); 462 if (!frames_left) 463 frames_left = runtime->period_size; 464 465 /* Samples in RX FIFO */ 466 fifo_samples = (rz_ssi_reg_readl(ssi, SSIFSR) >> 467 SSIFSR_RDC_SHIFT) & SSIFSR_RDC_MASK; 468 469 /* Only read full frames at a time */ 470 samples = 0; 471 while (frames_left && (fifo_samples >= runtime->channels)) { 472 samples += runtime->channels; 473 fifo_samples -= runtime->channels; 474 frames_left--; 475 } 476 477 /* not enough samples yet */ 478 if (!samples) 479 break; 480 481 /* calculate new buffer index */ 482 buf = (u16 *)runtime->dma_area; 483 buf += strm->buffer_pos * runtime->channels; 484 485 /* Note, only supports 16-bit samples */ 486 for (i = 0; i < samples; i++) 487 *buf++ = (u16)(rz_ssi_reg_readl(ssi, SSIFRDR) >> 16); 488 489 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 490 rz_ssi_pointer_update(strm, samples / runtime->channels); 491 } while (!frames_left && fifo_samples >= runtime->channels); 492 493 return 0; 494 } 495 496 static int rz_ssi_pio_send(struct rz_ssi_priv *ssi, struct rz_ssi_stream *strm) 497 { 498 struct snd_pcm_substream *substream = strm->substream; 499 struct snd_pcm_runtime *runtime = substream->runtime; 500 int sample_space; 501 int samples = 0; 502 int frames_left; 503 int i; 504 u32 ssifsr; 505 u16 *buf; 506 507 if (!rz_ssi_stream_is_valid(ssi, strm)) 508 return -EINVAL; 509 510 /* frames left in this period */ 511 frames_left = runtime->period_size - (strm->buffer_pos % 512 runtime->period_size); 513 if (frames_left == 0) 514 frames_left = runtime->period_size; 515 516 sample_space = strm->fifo_sample_size; 517 ssifsr = rz_ssi_reg_readl(ssi, SSIFSR); 518 sample_space -= (ssifsr >> SSIFSR_TDC_SHIFT) & SSIFSR_TDC_MASK; 519 520 /* Only add full frames at a time */ 521 while (frames_left && (sample_space >= runtime->channels)) { 522 samples += runtime->channels; 523 sample_space -= runtime->channels; 524 frames_left--; 525 } 526 527 /* no space to send anything right now */ 528 if (samples == 0) 529 return 0; 530 531 /* calculate new buffer index */ 532 buf = (u16 *)(runtime->dma_area); 533 buf += strm->buffer_pos * runtime->channels; 534 535 /* Note, only supports 16-bit samples */ 536 for (i = 0; i < samples; i++) 537 rz_ssi_reg_writel(ssi, SSIFTDR, ((u32)(*buf++) << 16)); 538 539 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_TDE, 0); 540 rz_ssi_pointer_update(strm, samples / runtime->channels); 541 542 return 0; 543 } 544 545 static irqreturn_t rz_ssi_interrupt(int irq, void *data) 546 { 547 struct rz_ssi_stream *strm_playback = NULL; 548 struct rz_ssi_stream *strm_capture = NULL; 549 struct rz_ssi_priv *ssi = data; 550 u32 ssisr = rz_ssi_reg_readl(ssi, SSISR); 551 552 if (ssi->playback.substream) 553 strm_playback = &ssi->playback; 554 if (ssi->capture.substream) 555 strm_capture = &ssi->capture; 556 557 if (!strm_playback && !strm_capture) 558 return IRQ_HANDLED; /* Left over TX/RX interrupt */ 559 560 if (irq == ssi->irq_int) { /* error or idle */ 561 bool is_stopped = false; 562 int i, count; 563 564 if (rz_ssi_is_dma_enabled(ssi)) 565 count = 4; 566 else 567 count = 1; 568 569 if (ssisr & (SSISR_RUIRQ | SSISR_ROIRQ | SSISR_TUIRQ | SSISR_TOIRQ)) 570 is_stopped = true; 571 572 if (ssi->capture.substream && is_stopped) { 573 if (ssisr & SSISR_RUIRQ) 574 strm_capture->uerr_num++; 575 if (ssisr & SSISR_ROIRQ) 576 strm_capture->oerr_num++; 577 578 rz_ssi_stop(ssi, strm_capture); 579 } 580 581 if (ssi->playback.substream && is_stopped) { 582 if (ssisr & SSISR_TUIRQ) 583 strm_playback->uerr_num++; 584 if (ssisr & SSISR_TOIRQ) 585 strm_playback->oerr_num++; 586 587 rz_ssi_stop(ssi, strm_playback); 588 } 589 590 /* Clear all flags */ 591 rz_ssi_reg_mask_setl(ssi, SSISR, SSISR_TOIRQ | SSISR_TUIRQ | 592 SSISR_ROIRQ | SSISR_RUIRQ, 0); 593 594 /* Add/remove more data */ 595 if (ssi->capture.substream && is_stopped) { 596 for (i = 0; i < count; i++) 597 strm_capture->transfer(ssi, strm_capture); 598 } 599 600 if (ssi->playback.substream && is_stopped) { 601 for (i = 0; i < count; i++) 602 strm_playback->transfer(ssi, strm_playback); 603 } 604 605 /* Resume */ 606 if (ssi->playback.substream && is_stopped) 607 rz_ssi_start(ssi, &ssi->playback); 608 if (ssi->capture.substream && is_stopped) 609 rz_ssi_start(ssi, &ssi->capture); 610 } 611 612 if (!rz_ssi_is_stream_running(&ssi->playback) && 613 !rz_ssi_is_stream_running(&ssi->capture)) 614 return IRQ_HANDLED; 615 616 /* tx data empty */ 617 if (irq == ssi->irq_tx && rz_ssi_is_stream_running(&ssi->playback)) 618 strm_playback->transfer(ssi, &ssi->playback); 619 620 /* rx data full */ 621 if (irq == ssi->irq_rx && rz_ssi_is_stream_running(&ssi->capture)) { 622 strm_capture->transfer(ssi, &ssi->capture); 623 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 624 } 625 626 if (irq == ssi->irq_rt) { 627 if (ssi->playback.substream) { 628 strm_playback->transfer(ssi, &ssi->playback); 629 } else { 630 strm_capture->transfer(ssi, &ssi->capture); 631 rz_ssi_reg_mask_setl(ssi, SSIFSR, SSIFSR_RDF, 0); 632 } 633 } 634 635 return IRQ_HANDLED; 636 } 637 638 static int rz_ssi_dma_slave_config(struct rz_ssi_priv *ssi, 639 struct dma_chan *dma_ch, bool is_play) 640 { 641 struct dma_slave_config cfg; 642 643 memset(&cfg, 0, sizeof(cfg)); 644 645 cfg.direction = is_play ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 646 cfg.dst_addr = ssi->phys + SSIFTDR; 647 cfg.src_addr = ssi->phys + SSIFRDR; 648 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 649 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 650 651 return dmaengine_slave_config(dma_ch, &cfg); 652 } 653 654 static int rz_ssi_dma_transfer(struct rz_ssi_priv *ssi, 655 struct rz_ssi_stream *strm) 656 { 657 struct snd_pcm_substream *substream = strm->substream; 658 struct dma_async_tx_descriptor *desc; 659 struct snd_pcm_runtime *runtime; 660 enum dma_transfer_direction dir; 661 u32 dma_paddr, dma_size; 662 int amount; 663 664 if (!rz_ssi_stream_is_valid(ssi, strm)) 665 return -EINVAL; 666 667 runtime = substream->runtime; 668 if (runtime->state == SNDRV_PCM_STATE_DRAINING) 669 /* 670 * Stream is ending, so do not queue up any more DMA 671 * transfers otherwise we play partial sound clips 672 * because we can't shut off the DMA quick enough. 673 */ 674 return 0; 675 676 dir = rz_ssi_stream_is_play(substream) ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM; 677 678 /* Always transfer 1 period */ 679 amount = runtime->period_size; 680 681 /* DMA physical address and size */ 682 dma_paddr = runtime->dma_addr + frames_to_bytes(runtime, 683 strm->dma_buffer_pos); 684 dma_size = frames_to_bytes(runtime, amount); 685 desc = dmaengine_prep_slave_single(strm->dma_ch, dma_paddr, dma_size, 686 dir, 687 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 688 if (!desc) { 689 dev_err(ssi->dev, "dmaengine_prep_slave_single() fail\n"); 690 return -ENOMEM; 691 } 692 693 desc->callback = rz_ssi_dma_complete; 694 desc->callback_param = strm; 695 696 if (dmaengine_submit(desc) < 0) { 697 dev_err(ssi->dev, "dmaengine_submit() fail\n"); 698 return -EIO; 699 } 700 701 /* Update DMA pointer */ 702 strm->dma_buffer_pos += amount; 703 if (strm->dma_buffer_pos >= runtime->buffer_size) 704 strm->dma_buffer_pos = 0; 705 706 /* Start DMA */ 707 dma_async_issue_pending(strm->dma_ch); 708 709 return 0; 710 } 711 712 static void rz_ssi_dma_complete(void *data) 713 { 714 struct rz_ssi_stream *strm = (struct rz_ssi_stream *)data; 715 716 if (!strm->running || !strm->substream || !strm->substream->runtime) 717 return; 718 719 /* Note that next DMA transaction has probably already started */ 720 rz_ssi_pointer_update(strm, strm->substream->runtime->period_size); 721 722 /* Queue up another DMA transaction */ 723 rz_ssi_dma_transfer(strm->priv, strm); 724 } 725 726 static void rz_ssi_release_dma_channels(struct rz_ssi_priv *ssi) 727 { 728 if (ssi->playback.dma_ch) { 729 dma_release_channel(ssi->playback.dma_ch); 730 ssi->playback.dma_ch = NULL; 731 if (ssi->dma_rt) 732 ssi->dma_rt = false; 733 } 734 735 if (ssi->capture.dma_ch) { 736 dma_release_channel(ssi->capture.dma_ch); 737 ssi->capture.dma_ch = NULL; 738 } 739 } 740 741 static int rz_ssi_dma_request(struct rz_ssi_priv *ssi, struct device *dev) 742 { 743 ssi->playback.dma_ch = dma_request_chan(dev, "tx"); 744 if (IS_ERR(ssi->playback.dma_ch)) 745 ssi->playback.dma_ch = NULL; 746 747 ssi->capture.dma_ch = dma_request_chan(dev, "rx"); 748 if (IS_ERR(ssi->capture.dma_ch)) 749 ssi->capture.dma_ch = NULL; 750 751 if (!ssi->playback.dma_ch && !ssi->capture.dma_ch) { 752 ssi->playback.dma_ch = dma_request_chan(dev, "rt"); 753 if (IS_ERR(ssi->playback.dma_ch)) { 754 ssi->playback.dma_ch = NULL; 755 goto no_dma; 756 } 757 758 ssi->dma_rt = true; 759 } 760 761 if (!rz_ssi_is_dma_enabled(ssi)) 762 goto no_dma; 763 764 if (ssi->playback.dma_ch && 765 (rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, true) < 0)) 766 goto no_dma; 767 768 if (ssi->capture.dma_ch && 769 (rz_ssi_dma_slave_config(ssi, ssi->capture.dma_ch, false) < 0)) 770 goto no_dma; 771 772 return 0; 773 774 no_dma: 775 rz_ssi_release_dma_channels(ssi); 776 777 return -ENODEV; 778 } 779 780 static int rz_ssi_dai_trigger(struct snd_pcm_substream *substream, int cmd, 781 struct snd_soc_dai *dai) 782 { 783 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 784 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 785 int ret = 0, i, num_transfer = 1; 786 787 switch (cmd) { 788 case SNDRV_PCM_TRIGGER_START: 789 /* Soft Reset */ 790 if (!rz_ssi_is_stream_running(&ssi->playback) && 791 !rz_ssi_is_stream_running(&ssi->capture)) { 792 rz_ssi_reg_mask_setl(ssi, SSIFCR, 0, SSIFCR_SSIRST); 793 rz_ssi_reg_mask_setl(ssi, SSIFCR, SSIFCR_SSIRST, 0); 794 udelay(5); 795 } 796 797 rz_ssi_stream_init(strm, substream); 798 799 if (ssi->dma_rt) { 800 bool is_playback; 801 802 is_playback = rz_ssi_stream_is_play(substream); 803 ret = rz_ssi_dma_slave_config(ssi, ssi->playback.dma_ch, 804 is_playback); 805 /* Fallback to pio */ 806 if (ret < 0) { 807 ssi->playback.transfer = rz_ssi_pio_send; 808 ssi->capture.transfer = rz_ssi_pio_recv; 809 rz_ssi_release_dma_channels(ssi); 810 } 811 } 812 813 /* For DMA, queue up multiple DMA descriptors */ 814 if (rz_ssi_is_dma_enabled(ssi)) 815 num_transfer = 4; 816 817 for (i = 0; i < num_transfer; i++) { 818 ret = strm->transfer(ssi, strm); 819 if (ret) 820 goto done; 821 } 822 823 ret = rz_ssi_start(ssi, strm); 824 break; 825 case SNDRV_PCM_TRIGGER_STOP: 826 rz_ssi_stop(ssi, strm); 827 rz_ssi_stream_quit(ssi, strm); 828 break; 829 } 830 831 done: 832 return ret; 833 } 834 835 static int rz_ssi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 836 { 837 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 838 839 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 840 case SND_SOC_DAIFMT_BP_FP: 841 break; 842 default: 843 dev_err(ssi->dev, "Codec should be clk and frame consumer\n"); 844 return -EINVAL; 845 } 846 847 /* 848 * set clock polarity 849 * 850 * "normal" BCLK = Signal is available at rising edge of BCLK 851 * "normal" FSYNC = (I2S) Left ch starts with falling FSYNC edge 852 */ 853 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 854 case SND_SOC_DAIFMT_NB_NF: 855 ssi->bckp_rise = false; 856 ssi->lrckp_fsync_fall = false; 857 break; 858 case SND_SOC_DAIFMT_NB_IF: 859 ssi->bckp_rise = false; 860 ssi->lrckp_fsync_fall = true; 861 break; 862 case SND_SOC_DAIFMT_IB_NF: 863 ssi->bckp_rise = true; 864 ssi->lrckp_fsync_fall = false; 865 break; 866 case SND_SOC_DAIFMT_IB_IF: 867 ssi->bckp_rise = true; 868 ssi->lrckp_fsync_fall = true; 869 break; 870 default: 871 return -EINVAL; 872 } 873 874 /* only i2s support */ 875 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 876 case SND_SOC_DAIFMT_I2S: 877 break; 878 default: 879 dev_err(ssi->dev, "Only I2S mode is supported.\n"); 880 return -EINVAL; 881 } 882 883 return 0; 884 } 885 886 static bool rz_ssi_is_valid_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 887 unsigned int channels, 888 unsigned int sample_width, 889 unsigned int sample_bits) 890 { 891 if (ssi->hw_params_cache.rate != rate || 892 ssi->hw_params_cache.channels != channels || 893 ssi->hw_params_cache.sample_width != sample_width || 894 ssi->hw_params_cache.sample_bits != sample_bits) 895 return false; 896 897 return true; 898 } 899 900 static void rz_ssi_cache_hw_params(struct rz_ssi_priv *ssi, unsigned int rate, 901 unsigned int channels, 902 unsigned int sample_width, 903 unsigned int sample_bits) 904 { 905 ssi->hw_params_cache.rate = rate; 906 ssi->hw_params_cache.channels = channels; 907 ssi->hw_params_cache.sample_width = sample_width; 908 ssi->hw_params_cache.sample_bits = sample_bits; 909 } 910 911 static int rz_ssi_dai_hw_params(struct snd_pcm_substream *substream, 912 struct snd_pcm_hw_params *params, 913 struct snd_soc_dai *dai) 914 { 915 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 916 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 917 unsigned int sample_bits = hw_param_interval(params, 918 SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min; 919 unsigned int channels = params_channels(params); 920 unsigned int rate = params_rate(params); 921 922 if (sample_bits != 16) { 923 dev_err(ssi->dev, "Unsupported sample width: %d\n", 924 sample_bits); 925 return -EINVAL; 926 } 927 928 if (channels != 2) { 929 dev_err(ssi->dev, "Number of channels not matched: %d\n", 930 channels); 931 return -EINVAL; 932 } 933 934 if (rz_ssi_is_stream_running(&ssi->playback) || 935 rz_ssi_is_stream_running(&ssi->capture)) { 936 if (rz_ssi_is_valid_hw_params(ssi, rate, channels, 937 strm->sample_width, sample_bits)) 938 return 0; 939 940 dev_err(ssi->dev, "Full duplex needs same HW params\n"); 941 return -EINVAL; 942 } 943 944 rz_ssi_cache_hw_params(ssi, rate, channels, strm->sample_width, 945 sample_bits); 946 947 return rz_ssi_clk_setup(ssi, rate, channels); 948 } 949 950 static const struct snd_soc_dai_ops rz_ssi_dai_ops = { 951 .trigger = rz_ssi_dai_trigger, 952 .set_fmt = rz_ssi_dai_set_fmt, 953 .hw_params = rz_ssi_dai_hw_params, 954 }; 955 956 static const struct snd_pcm_hardware rz_ssi_pcm_hardware = { 957 .info = SNDRV_PCM_INFO_INTERLEAVED | 958 SNDRV_PCM_INFO_MMAP | 959 SNDRV_PCM_INFO_MMAP_VALID, 960 .buffer_bytes_max = PREALLOC_BUFFER, 961 .period_bytes_min = 32, 962 .period_bytes_max = 8192, 963 .channels_min = SSI_CHAN_MIN, 964 .channels_max = SSI_CHAN_MAX, 965 .periods_min = 1, 966 .periods_max = 32, 967 .fifo_size = 32 * 2, 968 }; 969 970 static int rz_ssi_pcm_open(struct snd_soc_component *component, 971 struct snd_pcm_substream *substream) 972 { 973 snd_soc_set_runtime_hwparams(substream, &rz_ssi_pcm_hardware); 974 975 return snd_pcm_hw_constraint_integer(substream->runtime, 976 SNDRV_PCM_HW_PARAM_PERIODS); 977 } 978 979 static snd_pcm_uframes_t rz_ssi_pcm_pointer(struct snd_soc_component *component, 980 struct snd_pcm_substream *substream) 981 { 982 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 983 struct snd_soc_dai *dai = snd_soc_rtd_to_cpu(rtd, 0); 984 struct rz_ssi_priv *ssi = snd_soc_dai_get_drvdata(dai); 985 struct rz_ssi_stream *strm = rz_ssi_stream_get(ssi, substream); 986 987 return strm->buffer_pos; 988 } 989 990 static int rz_ssi_pcm_new(struct snd_soc_component *component, 991 struct snd_soc_pcm_runtime *rtd) 992 { 993 snd_pcm_set_managed_buffer_all(rtd->pcm, SNDRV_DMA_TYPE_DEV, 994 rtd->card->snd_card->dev, 995 PREALLOC_BUFFER, PREALLOC_BUFFER_MAX); 996 return 0; 997 } 998 999 static struct snd_soc_dai_driver rz_ssi_soc_dai[] = { 1000 { 1001 .name = "rz-ssi-dai", 1002 .playback = { 1003 .rates = SSI_RATES, 1004 .formats = SSI_FMTS, 1005 .channels_min = SSI_CHAN_MIN, 1006 .channels_max = SSI_CHAN_MAX, 1007 }, 1008 .capture = { 1009 .rates = SSI_RATES, 1010 .formats = SSI_FMTS, 1011 .channels_min = SSI_CHAN_MIN, 1012 .channels_max = SSI_CHAN_MAX, 1013 }, 1014 .ops = &rz_ssi_dai_ops, 1015 }, 1016 }; 1017 1018 static const struct snd_soc_component_driver rz_ssi_soc_component = { 1019 .name = "rz-ssi", 1020 .open = rz_ssi_pcm_open, 1021 .pointer = rz_ssi_pcm_pointer, 1022 .pcm_construct = rz_ssi_pcm_new, 1023 .legacy_dai_naming = 1, 1024 }; 1025 1026 static int rz_ssi_probe(struct platform_device *pdev) 1027 { 1028 struct rz_ssi_priv *ssi; 1029 struct clk *audio_clk; 1030 struct resource *res; 1031 int ret; 1032 1033 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL); 1034 if (!ssi) 1035 return -ENOMEM; 1036 1037 ssi->dev = &pdev->dev; 1038 ssi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1039 if (IS_ERR(ssi->base)) 1040 return PTR_ERR(ssi->base); 1041 1042 ssi->phys = res->start; 1043 ssi->clk = devm_clk_get(&pdev->dev, "ssi"); 1044 if (IS_ERR(ssi->clk)) 1045 return PTR_ERR(ssi->clk); 1046 1047 ssi->sfr_clk = devm_clk_get(&pdev->dev, "ssi_sfr"); 1048 if (IS_ERR(ssi->sfr_clk)) 1049 return PTR_ERR(ssi->sfr_clk); 1050 1051 audio_clk = devm_clk_get(&pdev->dev, "audio_clk1"); 1052 if (IS_ERR(audio_clk)) 1053 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1054 "no audio clk1"); 1055 1056 ssi->audio_clk_1 = clk_get_rate(audio_clk); 1057 audio_clk = devm_clk_get(&pdev->dev, "audio_clk2"); 1058 if (IS_ERR(audio_clk)) 1059 return dev_err_probe(&pdev->dev, PTR_ERR(audio_clk), 1060 "no audio clk2"); 1061 1062 ssi->audio_clk_2 = clk_get_rate(audio_clk); 1063 if (!(ssi->audio_clk_1 || ssi->audio_clk_2)) 1064 return dev_err_probe(&pdev->dev, -EINVAL, 1065 "no audio clk1 or audio clk2"); 1066 1067 ssi->audio_mck = ssi->audio_clk_1 ? ssi->audio_clk_1 : ssi->audio_clk_2; 1068 1069 /* Detect DMA support */ 1070 ret = rz_ssi_dma_request(ssi, &pdev->dev); 1071 if (ret < 0) { 1072 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1073 ssi->playback.transfer = rz_ssi_pio_send; 1074 ssi->capture.transfer = rz_ssi_pio_recv; 1075 } else { 1076 dev_info(&pdev->dev, "DMA enabled"); 1077 ssi->playback.transfer = rz_ssi_dma_transfer; 1078 ssi->capture.transfer = rz_ssi_dma_transfer; 1079 } 1080 1081 ssi->playback.priv = ssi; 1082 ssi->capture.priv = ssi; 1083 1084 spin_lock_init(&ssi->lock); 1085 dev_set_drvdata(&pdev->dev, ssi); 1086 1087 /* Error Interrupt */ 1088 ssi->irq_int = platform_get_irq_byname(pdev, "int_req"); 1089 if (ssi->irq_int < 0) { 1090 rz_ssi_release_dma_channels(ssi); 1091 return ssi->irq_int; 1092 } 1093 1094 ret = devm_request_irq(&pdev->dev, ssi->irq_int, &rz_ssi_interrupt, 1095 0, dev_name(&pdev->dev), ssi); 1096 if (ret < 0) { 1097 rz_ssi_release_dma_channels(ssi); 1098 return dev_err_probe(&pdev->dev, ret, 1099 "irq request error (int_req)\n"); 1100 } 1101 1102 if (!rz_ssi_is_dma_enabled(ssi)) { 1103 /* Tx and Rx interrupts (pio only) */ 1104 ssi->irq_tx = platform_get_irq_byname(pdev, "dma_tx"); 1105 ssi->irq_rx = platform_get_irq_byname(pdev, "dma_rx"); 1106 if (ssi->irq_tx == -ENXIO && ssi->irq_rx == -ENXIO) { 1107 ssi->irq_rt = platform_get_irq_byname(pdev, "dma_rt"); 1108 if (ssi->irq_rt < 0) 1109 return ssi->irq_rt; 1110 1111 ret = devm_request_irq(&pdev->dev, ssi->irq_rt, 1112 &rz_ssi_interrupt, 0, 1113 dev_name(&pdev->dev), ssi); 1114 if (ret < 0) 1115 return dev_err_probe(&pdev->dev, ret, 1116 "irq request error (dma_rt)\n"); 1117 } else { 1118 if (ssi->irq_tx < 0) 1119 return ssi->irq_tx; 1120 1121 if (ssi->irq_rx < 0) 1122 return ssi->irq_rx; 1123 1124 ret = devm_request_irq(&pdev->dev, ssi->irq_tx, 1125 &rz_ssi_interrupt, 0, 1126 dev_name(&pdev->dev), ssi); 1127 if (ret < 0) 1128 return dev_err_probe(&pdev->dev, ret, 1129 "irq request error (dma_tx)\n"); 1130 1131 ret = devm_request_irq(&pdev->dev, ssi->irq_rx, 1132 &rz_ssi_interrupt, 0, 1133 dev_name(&pdev->dev), ssi); 1134 if (ret < 0) 1135 return dev_err_probe(&pdev->dev, ret, 1136 "irq request error (dma_rx)\n"); 1137 } 1138 } 1139 1140 ssi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 1141 if (IS_ERR(ssi->rstc)) { 1142 ret = PTR_ERR(ssi->rstc); 1143 goto err_reset; 1144 } 1145 1146 reset_control_deassert(ssi->rstc); 1147 pm_runtime_enable(&pdev->dev); 1148 ret = pm_runtime_resume_and_get(&pdev->dev); 1149 if (ret < 0) { 1150 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed\n"); 1151 goto err_pm; 1152 } 1153 1154 ret = devm_snd_soc_register_component(&pdev->dev, &rz_ssi_soc_component, 1155 rz_ssi_soc_dai, 1156 ARRAY_SIZE(rz_ssi_soc_dai)); 1157 if (ret < 0) { 1158 dev_err(&pdev->dev, "failed to register snd component\n"); 1159 goto err_snd_soc; 1160 } 1161 1162 return 0; 1163 1164 err_snd_soc: 1165 pm_runtime_put(ssi->dev); 1166 err_pm: 1167 pm_runtime_disable(ssi->dev); 1168 reset_control_assert(ssi->rstc); 1169 err_reset: 1170 rz_ssi_release_dma_channels(ssi); 1171 1172 return ret; 1173 } 1174 1175 static void rz_ssi_remove(struct platform_device *pdev) 1176 { 1177 struct rz_ssi_priv *ssi = dev_get_drvdata(&pdev->dev); 1178 1179 rz_ssi_release_dma_channels(ssi); 1180 1181 pm_runtime_put(ssi->dev); 1182 pm_runtime_disable(ssi->dev); 1183 reset_control_assert(ssi->rstc); 1184 } 1185 1186 static const struct of_device_id rz_ssi_of_match[] = { 1187 { .compatible = "renesas,rz-ssi", }, 1188 {/* Sentinel */}, 1189 }; 1190 MODULE_DEVICE_TABLE(of, rz_ssi_of_match); 1191 1192 static struct platform_driver rz_ssi_driver = { 1193 .driver = { 1194 .name = "rz-ssi-pcm-audio", 1195 .of_match_table = rz_ssi_of_match, 1196 }, 1197 .probe = rz_ssi_probe, 1198 .remove = rz_ssi_remove, 1199 }; 1200 1201 module_platform_driver(rz_ssi_driver); 1202 1203 MODULE_LICENSE("GPL v2"); 1204 MODULE_DESCRIPTION("Renesas RZ/G2L ASoC Serial Sound Interface Driver"); 1205 MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>"); 1206