1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <dt-bindings/sound/qcom,q6afe.h> 6 #include <linux/slab.h> 7 #include <linux/kernel.h> 8 #include <linux/uaccess.h> 9 #include <linux/wait.h> 10 #include <linux/jiffies.h> 11 #include <linux/sched.h> 12 #include <linux/module.h> 13 #include <linux/kref.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/spinlock.h> 17 #include <linux/delay.h> 18 #include <linux/soc/qcom/apr.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dai.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include "q6dsp-errno.h" 24 #include "q6core.h" 25 #include "q6afe.h" 26 27 /* AFE CMDs */ 28 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 29 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 30 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 31 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 32 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 33 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 34 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 35 #define AFE_MODULE_TDM 0x0001028A 36 37 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 38 #define AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS 0x000102A5 39 #define AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT 0x000102AA 40 41 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 42 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 43 44 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 45 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 46 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 47 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 48 #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 49 #define AFE_PARAM_ID_USB_AUDIO_CONFIG 0x000102A4 50 #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 51 #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 52 #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 53 54 /* I2S config specific */ 55 #define AFE_API_VERSION_I2S_CONFIG 0x1 56 #define AFE_PORT_I2S_SD0 0x1 57 #define AFE_PORT_I2S_SD1 0x2 58 #define AFE_PORT_I2S_SD2 0x3 59 #define AFE_PORT_I2S_SD3 0x4 60 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 61 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 62 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 63 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 64 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 65 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 66 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 67 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 68 #define AFE_PORT_I2S_QUAD01 0x5 69 #define AFE_PORT_I2S_QUAD23 0x6 70 #define AFE_PORT_I2S_6CHS 0x7 71 #define AFE_PORT_I2S_8CHS 0x8 72 #define AFE_PORT_I2S_MONO 0x0 73 #define AFE_PORT_I2S_STEREO 0x1 74 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 75 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 76 #define AFE_LINEAR_PCM_DATA 0x0 77 78 #define AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 0x1 79 80 /* Port IDs */ 81 #define AFE_API_VERSION_HDMI_CONFIG 0x1 82 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 83 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 84 85 /* USB AFE port */ 86 #define AFE_PORT_ID_USB_RX 0x7000 87 88 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 89 /* Clock set API version */ 90 #define AFE_API_VERSION_CLOCK_SET 1 91 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 92 #define AFE_MODULE_CLOCK_SET 0x0001028F 93 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 94 95 /* SLIMbus Rx port on channel 0. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 97 /* SLIMbus Tx port on channel 0. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 99 /* SLIMbus Rx port on channel 1. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 101 /* SLIMbus Tx port on channel 1. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 103 /* SLIMbus Rx port on channel 2. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 105 /* SLIMbus Tx port on channel 2. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 107 /* SLIMbus Rx port on channel 3. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 109 /* SLIMbus Tx port on channel 3. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 111 /* SLIMbus Rx port on channel 4. */ 112 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 113 /* SLIMbus Tx port on channel 4. */ 114 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 115 /* SLIMbus Rx port on channel 5. */ 116 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 117 /* SLIMbus Tx port on channel 5. */ 118 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 119 /* SLIMbus Rx port on channel 6. */ 120 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 121 /* SLIMbus Tx port on channel 6. */ 122 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 123 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 124 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 125 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 126 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 127 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 128 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 129 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 130 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 131 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 132 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 133 134 /* Start of the range of port IDs for TDM devices. */ 135 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 136 137 /* End of the range of port IDs for TDM devices. */ 138 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 139 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 140 141 /* Size of the range of port IDs for TDM ports. */ 142 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 143 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 144 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 145 146 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 147 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 148 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 149 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 150 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 151 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 152 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 153 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 154 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 155 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 156 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 157 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 158 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 159 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 160 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 161 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 162 163 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 164 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 165 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 166 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 167 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 168 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 169 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 170 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 171 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 172 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 173 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 174 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 175 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 176 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 177 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 178 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 179 180 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 181 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 182 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 183 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 184 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 185 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 186 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 187 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 188 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 189 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 190 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 191 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 192 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 193 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 194 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 195 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 196 197 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 198 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 199 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 200 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 201 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 202 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 203 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 204 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 205 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 206 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 207 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 208 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 209 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 210 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 211 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 212 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 213 214 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 215 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 216 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 217 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 218 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 219 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 220 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 221 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 222 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 223 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 224 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 225 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 226 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 227 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 228 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 229 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 230 231 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 232 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 233 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 234 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 235 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 236 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 237 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 238 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 239 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 240 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 241 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 242 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 243 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 244 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 245 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 246 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 247 248 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 249 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 250 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 251 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 252 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 253 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 254 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 255 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 256 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 257 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 258 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 259 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 260 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 261 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 262 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 263 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 264 265 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 266 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 267 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 268 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 269 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 270 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 271 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 272 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 273 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 274 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 275 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 276 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 277 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 278 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 279 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 280 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 281 282 #define AFE_PORT_ID_QUINARY_TDM_RX \ 283 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 284 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 285 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 286 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 287 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 288 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 289 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 290 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 291 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 292 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 293 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 294 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 295 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 296 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 297 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 298 299 #define AFE_PORT_ID_QUINARY_TDM_TX \ 300 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 301 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 302 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 303 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 304 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 305 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 306 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 307 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 308 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 309 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 310 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 311 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 312 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 313 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 314 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 315 316 /* AFE WSA Codec DMA Rx port 0 */ 317 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 318 /* AFE WSA Codec DMA Tx port 0 */ 319 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 320 /* AFE WSA Codec DMA Rx port 1 */ 321 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 322 /* AFE WSA Codec DMA Tx port 1 */ 323 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 324 /* AFE WSA Codec DMA Tx port 2 */ 325 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 326 /* AFE VA Codec DMA Tx port 0 */ 327 #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 328 /* AFE VA Codec DMA Tx port 1 */ 329 #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 330 /* AFE VA Codec DMA Tx port 2 */ 331 #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 332 /* AFE Rx Codec DMA Rx port 0 */ 333 #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 334 /* AFE Tx Codec DMA Tx port 0 */ 335 #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 336 /* AFE Rx Codec DMA Rx port 1 */ 337 #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 338 /* AFE Tx Codec DMA Tx port 1 */ 339 #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 340 /* AFE Rx Codec DMA Rx port 2 */ 341 #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 342 /* AFE Tx Codec DMA Tx port 2 */ 343 #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 344 /* AFE Rx Codec DMA Rx port 3 */ 345 #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 346 /* AFE Tx Codec DMA Tx port 3 */ 347 #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 348 /* AFE Rx Codec DMA Rx port 4 */ 349 #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 350 /* AFE Tx Codec DMA Tx port 4 */ 351 #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 352 /* AFE Rx Codec DMA Rx port 5 */ 353 #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A 354 /* AFE Tx Codec DMA Tx port 5 */ 355 #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B 356 /* AFE Rx Codec DMA Rx port 6 */ 357 #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C 358 /* AFE Rx Codec DMA Rx port 7 */ 359 #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E 360 361 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 362 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 363 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 364 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 365 #define AFE_API_VERSION_TDM_CONFIG 1 366 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 367 #define AFE_API_VERSION_CODEC_DMA_CONFIG 1 368 369 #define TIMEOUT_MS 3000 370 #define AFE_CMD_RESP_AVAIL 0 371 #define AFE_CMD_RESP_NONE 1 372 #define AFE_CLK_TOKEN 1024 373 374 struct q6afe { 375 struct apr_device *apr; 376 struct device *dev; 377 struct q6core_svc_api_info ainfo; 378 struct mutex lock; 379 struct aprv2_ibasic_rsp_result_t result; 380 wait_queue_head_t wait; 381 struct list_head port_list; 382 spinlock_t port_list_lock; 383 }; 384 385 struct afe_port_cmd_device_start { 386 u16 port_id; 387 u16 reserved; 388 } __packed; 389 390 struct afe_port_cmd_device_stop { 391 u16 port_id; 392 u16 reserved; 393 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 394 } __packed; 395 396 struct afe_port_param_data_v2 { 397 u32 module_id; 398 u32 param_id; 399 u16 param_size; 400 u16 reserved; 401 } __packed; 402 403 struct afe_svc_cmd_set_param { 404 uint32_t payload_size; 405 uint32_t payload_address_lsw; 406 uint32_t payload_address_msw; 407 uint32_t mem_map_handle; 408 } __packed; 409 410 struct afe_port_cmd_set_param_v2 { 411 u16 port_id; 412 u16 payload_size; 413 u32 payload_address_lsw; 414 u32 payload_address_msw; 415 u32 mem_map_handle; 416 } __packed; 417 418 struct afe_param_id_hdmi_multi_chan_audio_cfg { 419 u32 hdmi_cfg_minor_version; 420 u16 datatype; 421 u16 channel_allocation; 422 u32 sample_rate; 423 u16 bit_width; 424 u16 reserved; 425 } __packed; 426 427 struct afe_param_id_slimbus_cfg { 428 u32 sb_cfg_minor_version; 429 /* Minor version used for tracking the version of the SLIMBUS 430 * configuration interface. 431 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 432 */ 433 434 u16 slimbus_dev_id; 435 /* SLIMbus hardware device ID, which is required to handle 436 * multiple SLIMbus hardware blocks. 437 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 438 */ 439 u16 bit_width; 440 /* Bit width of the sample. 441 * Supported values: 16, 24 442 */ 443 u16 data_format; 444 /* Data format supported by the SLIMbus hardware. The default is 445 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 446 * hardware does not perform any format conversions before the data 447 * transfer. 448 */ 449 u16 num_channels; 450 /* Number of channels. 451 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 452 */ 453 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 454 /* Mapping of shared channel IDs (128 to 255) to which the 455 * master port is to be connected. 456 * Shared_channel_mapping[i] represents the shared channel assigned 457 * for audio channel i in multichannel audio data. 458 */ 459 u32 sample_rate; 460 /* Sampling rate of the port. 461 * Supported values: 462 * - #AFE_PORT_SAMPLE_RATE_8K 463 * - #AFE_PORT_SAMPLE_RATE_16K 464 * - #AFE_PORT_SAMPLE_RATE_48K 465 * - #AFE_PORT_SAMPLE_RATE_96K 466 * - #AFE_PORT_SAMPLE_RATE_192K 467 */ 468 } __packed; 469 470 struct afe_clk_cfg { 471 u32 i2s_cfg_minor_version; 472 u32 clk_val1; 473 u32 clk_val2; 474 u16 clk_src; 475 u16 clk_root; 476 u16 clk_set_mode; 477 u16 reserved; 478 } __packed; 479 480 struct afe_digital_clk_cfg { 481 u32 i2s_cfg_minor_version; 482 u32 clk_val; 483 u16 clk_root; 484 u16 reserved; 485 } __packed; 486 487 struct afe_param_id_i2s_cfg { 488 u32 i2s_cfg_minor_version; 489 u16 bit_width; 490 u16 channel_mode; 491 u16 mono_stereo; 492 u16 ws_src; 493 u32 sample_rate; 494 u16 data_format; 495 u16 reserved; 496 } __packed; 497 498 struct afe_param_id_tdm_cfg { 499 u32 tdm_cfg_minor_version; 500 u32 num_channels; 501 u32 sample_rate; 502 u32 bit_width; 503 u16 data_format; 504 u16 sync_mode; 505 u16 sync_src; 506 u16 nslots_per_frame; 507 u16 ctrl_data_out_enable; 508 u16 ctrl_invert_sync_pulse; 509 u16 ctrl_sync_data_delay; 510 u16 slot_width; 511 u32 slot_mask; 512 } __packed; 513 514 struct afe_param_id_cdc_dma_cfg { 515 u32 cdc_dma_cfg_minor_version; 516 u32 sample_rate; 517 u16 bit_width; 518 u16 data_format; 519 u16 num_channels; 520 u16 active_channels_mask; 521 } __packed; 522 523 struct afe_param_id_usb_cfg { 524 /* Minor version used for tracking USB audio device configuration. 525 * Supported values: AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 526 */ 527 u32 cfg_minor_version; 528 /* Sampling rate of the port. 529 * Supported values: 530 * - AFE_PORT_SAMPLE_RATE_8K 531 * - AFE_PORT_SAMPLE_RATE_11025 532 * - AFE_PORT_SAMPLE_RATE_12K 533 * - AFE_PORT_SAMPLE_RATE_16K 534 * - AFE_PORT_SAMPLE_RATE_22050 535 * - AFE_PORT_SAMPLE_RATE_24K 536 * - AFE_PORT_SAMPLE_RATE_32K 537 * - AFE_PORT_SAMPLE_RATE_44P1K 538 * - AFE_PORT_SAMPLE_RATE_48K 539 * - AFE_PORT_SAMPLE_RATE_96K 540 * - AFE_PORT_SAMPLE_RATE_192K 541 */ 542 u32 sample_rate; 543 /* Bit width of the sample. 544 * Supported values: 16, 24 545 */ 546 u16 bit_width; 547 /* Number of channels. 548 * Supported values: 1 and 2 549 */ 550 u16 num_channels; 551 /* Data format supported by the USB. The supported value is 552 * 0 (#AFE_USB_AUDIO_DATA_FORMAT_LINEAR_PCM). 553 */ 554 u16 data_format; 555 /* this field must be 0 */ 556 u16 reserved; 557 /* device token of actual end USB audio device */ 558 u32 dev_token; 559 /* endianness of this interface */ 560 u32 endian; 561 /* service interval */ 562 u32 service_interval; 563 } __packed; 564 565 /** 566 * struct afe_param_id_usb_audio_dev_params 567 * @cfg_minor_version: Minor version used for tracking USB audio device 568 * configuration. 569 * Supported values: 570 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 571 * @dev_token: device token of actual end USB audio device 572 **/ 573 struct afe_param_id_usb_audio_dev_params { 574 u32 cfg_minor_version; 575 u32 dev_token; 576 } __packed; 577 578 /** 579 * struct afe_param_id_usb_audio_dev_lpcm_fmt 580 * @cfg_minor_version: Minor version used for tracking USB audio device 581 * configuration. 582 * Supported values: 583 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 584 * @endian: endianness of this interface 585 **/ 586 struct afe_param_id_usb_audio_dev_lpcm_fmt { 587 u32 cfg_minor_version; 588 u32 endian; 589 } __packed; 590 591 #define AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL 0x000102B7 592 593 /** 594 * struct afe_param_id_usb_audio_svc_interval 595 * @cfg_minor_version: Minor version used for tracking USB audio device 596 * configuration. 597 * Supported values: 598 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 599 * @svc_interval: service interval 600 **/ 601 struct afe_param_id_usb_audio_svc_interval { 602 u32 cfg_minor_version; 603 u32 svc_interval; 604 } __packed; 605 606 union afe_port_config { 607 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 608 struct afe_param_id_slimbus_cfg slim_cfg; 609 struct afe_param_id_i2s_cfg i2s_cfg; 610 struct afe_param_id_tdm_cfg tdm_cfg; 611 struct afe_param_id_cdc_dma_cfg dma_cfg; 612 struct afe_param_id_usb_cfg usb_cfg; 613 } __packed; 614 615 616 struct afe_clk_set { 617 uint32_t clk_set_minor_version; 618 uint32_t clk_id; 619 uint32_t clk_freq_in_hz; 620 uint16_t clk_attri; 621 uint16_t clk_root; 622 uint32_t enable; 623 }; 624 625 struct afe_param_id_slot_mapping_cfg { 626 u32 minor_version; 627 u16 num_channels; 628 u16 bitwidth; 629 u32 data_align_type; 630 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 631 } __packed; 632 633 struct q6afe_port { 634 wait_queue_head_t wait; 635 union afe_port_config port_cfg; 636 struct afe_param_id_slot_mapping_cfg *scfg; 637 struct aprv2_ibasic_rsp_result_t result; 638 int token; 639 int id; 640 int cfg_type; 641 struct q6afe *afe; 642 struct kref refcount; 643 struct list_head node; 644 }; 645 646 struct afe_cmd_remote_lpass_core_hw_vote_request { 647 uint32_t hw_block_id; 648 char client_name[8]; 649 } __packed; 650 651 struct afe_cmd_remote_lpass_core_hw_devote_request { 652 uint32_t hw_block_id; 653 uint32_t client_handle; 654 } __packed; 655 656 657 658 struct afe_port_map { 659 int port_id; 660 int token; 661 int is_rx; 662 int is_dig_pcm; 663 }; 664 665 /* 666 * Mapping between Virtual Port IDs to DSP AFE Port ID 667 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 668 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 669 */ 670 671 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 672 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 673 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 674 SLIMBUS_0_RX, 1, 1}, 675 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 676 SLIMBUS_1_RX, 1, 1}, 677 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 678 SLIMBUS_2_RX, 1, 1}, 679 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 680 SLIMBUS_3_RX, 1, 1}, 681 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 682 SLIMBUS_4_RX, 1, 1}, 683 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 684 SLIMBUS_5_RX, 1, 1}, 685 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 686 SLIMBUS_6_RX, 1, 1}, 687 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 688 SLIMBUS_0_TX, 0, 1}, 689 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 690 SLIMBUS_1_TX, 0, 1}, 691 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 692 SLIMBUS_2_TX, 0, 1}, 693 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 694 SLIMBUS_3_TX, 0, 1}, 695 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 696 SLIMBUS_4_TX, 0, 1}, 697 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 698 SLIMBUS_5_TX, 0, 1}, 699 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 700 SLIMBUS_6_TX, 0, 1}, 701 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 702 PRIMARY_MI2S_RX, 1, 1}, 703 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 704 PRIMARY_MI2S_RX, 0, 1}, 705 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 706 SECONDARY_MI2S_RX, 1, 1}, 707 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 708 SECONDARY_MI2S_TX, 0, 1}, 709 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 710 TERTIARY_MI2S_RX, 1, 1}, 711 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 712 TERTIARY_MI2S_TX, 0, 1}, 713 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 714 QUATERNARY_MI2S_RX, 1, 1}, 715 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 716 QUATERNARY_MI2S_TX, 0, 1}, 717 [QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, 718 QUINARY_MI2S_RX, 1, 1}, 719 [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, 720 QUINARY_MI2S_TX, 0, 1}, 721 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 722 PRIMARY_TDM_RX_0, 1, 1}, 723 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 724 PRIMARY_TDM_TX_0, 0, 1}, 725 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 726 PRIMARY_TDM_RX_1, 1, 1}, 727 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 728 PRIMARY_TDM_TX_1, 0, 1}, 729 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 730 PRIMARY_TDM_RX_2, 1, 1}, 731 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 732 PRIMARY_TDM_TX_2, 0, 1}, 733 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 734 PRIMARY_TDM_RX_3, 1, 1}, 735 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 736 PRIMARY_TDM_TX_3, 0, 1}, 737 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 738 PRIMARY_TDM_RX_4, 1, 1}, 739 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 740 PRIMARY_TDM_TX_4, 0, 1}, 741 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 742 PRIMARY_TDM_RX_5, 1, 1}, 743 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 744 PRIMARY_TDM_TX_5, 0, 1}, 745 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 746 PRIMARY_TDM_RX_6, 1, 1}, 747 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 748 PRIMARY_TDM_TX_6, 0, 1}, 749 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 750 PRIMARY_TDM_RX_7, 1, 1}, 751 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 752 PRIMARY_TDM_TX_7, 0, 1}, 753 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 754 SECONDARY_TDM_RX_0, 1, 1}, 755 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 756 SECONDARY_TDM_TX_0, 0, 1}, 757 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 758 SECONDARY_TDM_RX_1, 1, 1}, 759 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 760 SECONDARY_TDM_TX_1, 0, 1}, 761 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 762 SECONDARY_TDM_RX_2, 1, 1}, 763 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 764 SECONDARY_TDM_TX_2, 0, 1}, 765 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 766 SECONDARY_TDM_RX_3, 1, 1}, 767 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 768 SECONDARY_TDM_TX_3, 0, 1}, 769 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 770 SECONDARY_TDM_RX_4, 1, 1}, 771 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 772 SECONDARY_TDM_TX_4, 0, 1}, 773 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 774 SECONDARY_TDM_RX_5, 1, 1}, 775 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 776 SECONDARY_TDM_TX_5, 0, 1}, 777 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 778 SECONDARY_TDM_RX_6, 1, 1}, 779 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 780 SECONDARY_TDM_TX_6, 0, 1}, 781 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 782 SECONDARY_TDM_RX_7, 1, 1}, 783 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 784 SECONDARY_TDM_TX_7, 0, 1}, 785 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 786 TERTIARY_TDM_RX_0, 1, 1}, 787 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 788 TERTIARY_TDM_TX_0, 0, 1}, 789 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 790 TERTIARY_TDM_RX_1, 1, 1}, 791 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 792 TERTIARY_TDM_TX_1, 0, 1}, 793 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 794 TERTIARY_TDM_RX_2, 1, 1}, 795 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 796 TERTIARY_TDM_TX_2, 0, 1}, 797 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 798 TERTIARY_TDM_RX_3, 1, 1}, 799 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 800 TERTIARY_TDM_TX_3, 0, 1}, 801 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 802 TERTIARY_TDM_RX_4, 1, 1}, 803 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 804 TERTIARY_TDM_TX_4, 0, 1}, 805 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 806 TERTIARY_TDM_RX_5, 1, 1}, 807 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 808 TERTIARY_TDM_TX_5, 0, 1}, 809 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 810 TERTIARY_TDM_RX_6, 1, 1}, 811 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 812 TERTIARY_TDM_TX_6, 0, 1}, 813 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 814 TERTIARY_TDM_RX_7, 1, 1}, 815 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 816 TERTIARY_TDM_TX_7, 0, 1}, 817 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 818 QUATERNARY_TDM_RX_0, 1, 1}, 819 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 820 QUATERNARY_TDM_TX_0, 0, 1}, 821 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 822 QUATERNARY_TDM_RX_1, 1, 1}, 823 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 824 QUATERNARY_TDM_TX_1, 0, 1}, 825 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 826 QUATERNARY_TDM_RX_2, 1, 1}, 827 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 828 QUATERNARY_TDM_TX_2, 0, 1}, 829 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 830 QUATERNARY_TDM_RX_3, 1, 1}, 831 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 832 QUATERNARY_TDM_TX_3, 0, 1}, 833 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 834 QUATERNARY_TDM_RX_4, 1, 1}, 835 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 836 QUATERNARY_TDM_TX_4, 0, 1}, 837 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 838 QUATERNARY_TDM_RX_5, 1, 1}, 839 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 840 QUATERNARY_TDM_TX_5, 0, 1}, 841 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 842 QUATERNARY_TDM_RX_6, 1, 1}, 843 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 844 QUATERNARY_TDM_TX_6, 0, 1}, 845 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 846 QUATERNARY_TDM_RX_7, 1, 1}, 847 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 848 QUATERNARY_TDM_TX_7, 0, 1}, 849 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 850 QUINARY_TDM_RX_0, 1, 1}, 851 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 852 QUINARY_TDM_TX_0, 0, 1}, 853 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 854 QUINARY_TDM_RX_1, 1, 1}, 855 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 856 QUINARY_TDM_TX_1, 0, 1}, 857 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 858 QUINARY_TDM_RX_2, 1, 1}, 859 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 860 QUINARY_TDM_TX_2, 0, 1}, 861 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 862 QUINARY_TDM_RX_3, 1, 1}, 863 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 864 QUINARY_TDM_TX_3, 0, 1}, 865 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 866 QUINARY_TDM_RX_4, 1, 1}, 867 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 868 QUINARY_TDM_TX_4, 0, 1}, 869 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 870 QUINARY_TDM_RX_5, 1, 1}, 871 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 872 QUINARY_TDM_TX_5, 0, 1}, 873 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 874 QUINARY_TDM_RX_6, 1, 1}, 875 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 876 QUINARY_TDM_TX_6, 0, 1}, 877 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 878 QUINARY_TDM_RX_7, 1, 1}, 879 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 880 QUINARY_TDM_TX_7, 0, 1}, 881 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 882 DISPLAY_PORT_RX, 1, 1}, 883 [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, 884 WSA_CODEC_DMA_RX_0, 1, 1}, 885 [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, 886 WSA_CODEC_DMA_TX_0, 0, 1}, 887 [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, 888 WSA_CODEC_DMA_RX_1, 1, 1}, 889 [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, 890 WSA_CODEC_DMA_TX_1, 0, 1}, 891 [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, 892 WSA_CODEC_DMA_TX_2, 0, 1}, 893 [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, 894 VA_CODEC_DMA_TX_0, 0, 1}, 895 [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, 896 VA_CODEC_DMA_TX_1, 0, 1}, 897 [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, 898 VA_CODEC_DMA_TX_2, 0, 1}, 899 [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, 900 RX_CODEC_DMA_RX_0, 1, 1}, 901 [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, 902 TX_CODEC_DMA_TX_0, 0, 1}, 903 [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, 904 RX_CODEC_DMA_RX_1, 1, 1}, 905 [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, 906 TX_CODEC_DMA_TX_1, 0, 1}, 907 [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, 908 RX_CODEC_DMA_RX_2, 1, 1}, 909 [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, 910 TX_CODEC_DMA_TX_2, 0, 1}, 911 [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, 912 RX_CODEC_DMA_RX_3, 1, 1}, 913 [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, 914 TX_CODEC_DMA_TX_3, 0, 1}, 915 [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, 916 RX_CODEC_DMA_RX_4, 1, 1}, 917 [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, 918 TX_CODEC_DMA_TX_4, 0, 1}, 919 [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, 920 RX_CODEC_DMA_RX_5, 1, 1}, 921 [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, 922 TX_CODEC_DMA_TX_5, 0, 1}, 923 [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, 924 RX_CODEC_DMA_RX_6, 1, 1}, 925 [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, 926 RX_CODEC_DMA_RX_7, 1, 1}, 927 [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, 928 }; 929 930 static void q6afe_port_free(struct kref *ref) 931 { 932 struct q6afe_port *port; 933 struct q6afe *afe; 934 unsigned long flags; 935 936 port = container_of(ref, struct q6afe_port, refcount); 937 afe = port->afe; 938 spin_lock_irqsave(&afe->port_list_lock, flags); 939 list_del(&port->node); 940 spin_unlock_irqrestore(&afe->port_list_lock, flags); 941 kfree(port->scfg); 942 kfree(port); 943 } 944 945 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 946 { 947 struct q6afe_port *p; 948 struct q6afe_port *ret = NULL; 949 unsigned long flags; 950 951 spin_lock_irqsave(&afe->port_list_lock, flags); 952 list_for_each_entry(p, &afe->port_list, node) 953 if (p->token == token) { 954 ret = p; 955 kref_get(&p->refcount); 956 break; 957 } 958 959 spin_unlock_irqrestore(&afe->port_list_lock, flags); 960 return ret; 961 } 962 963 static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) 964 { 965 struct q6afe *afe = dev_get_drvdata(&adev->dev); 966 struct aprv2_ibasic_rsp_result_t *res; 967 struct apr_hdr *hdr = &data->hdr; 968 struct q6afe_port *port; 969 970 if (!data->payload_size) 971 return 0; 972 973 res = data->payload; 974 switch (hdr->opcode) { 975 case APR_BASIC_RSP_RESULT: { 976 if (res->status) { 977 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 978 res->opcode, res->status); 979 } 980 switch (res->opcode) { 981 case AFE_PORT_CMD_SET_PARAM_V2: 982 case AFE_PORT_CMD_DEVICE_STOP: 983 case AFE_PORT_CMD_DEVICE_START: 984 case AFE_SVC_CMD_SET_PARAM: 985 port = q6afe_find_port(afe, hdr->token); 986 if (port) { 987 port->result = *res; 988 wake_up(&port->wait); 989 kref_put(&port->refcount, q6afe_port_free); 990 } else if (hdr->token == AFE_CLK_TOKEN) { 991 afe->result = *res; 992 wake_up(&afe->wait); 993 } 994 break; 995 default: 996 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 997 break; 998 } 999 } 1000 break; 1001 case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: 1002 afe->result.opcode = hdr->opcode; 1003 afe->result.status = res->status; 1004 wake_up(&afe->wait); 1005 break; 1006 default: 1007 break; 1008 } 1009 1010 return 0; 1011 } 1012 1013 /** 1014 * q6afe_get_port_id() - Get port id from a given port index 1015 * 1016 * @index: port index 1017 * 1018 * Return: Will be an negative on error or valid port_id on success 1019 */ 1020 int q6afe_get_port_id(int index) 1021 { 1022 if (index < 0 || index >= AFE_PORT_MAX) 1023 return -EINVAL; 1024 1025 return port_maps[index].port_id; 1026 } 1027 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 1028 1029 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 1030 struct q6afe_port *port, uint32_t rsp_opcode) 1031 { 1032 wait_queue_head_t *wait; 1033 struct aprv2_ibasic_rsp_result_t *result; 1034 int ret; 1035 1036 mutex_lock(&afe->lock); 1037 if (port) { 1038 wait = &port->wait; 1039 result = &port->result; 1040 } else { 1041 result = &afe->result; 1042 wait = &afe->wait; 1043 } 1044 1045 result->opcode = 0; 1046 result->status = 0; 1047 1048 ret = apr_send_pkt(afe->apr, pkt); 1049 if (ret < 0) { 1050 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 1051 ret = -EINVAL; 1052 goto err; 1053 } 1054 1055 ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), 1056 msecs_to_jiffies(TIMEOUT_MS)); 1057 if (!ret) { 1058 ret = -ETIMEDOUT; 1059 } else if (result->status > 0) { 1060 dev_err(afe->dev, "DSP returned error[%x]\n", 1061 result->status); 1062 ret = -EINVAL; 1063 } else { 1064 ret = 0; 1065 } 1066 1067 err: 1068 mutex_unlock(&afe->lock); 1069 1070 return ret; 1071 } 1072 1073 static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, 1074 void *data, int param_id, int module_id, int psize, 1075 int token) 1076 { 1077 struct afe_svc_cmd_set_param *param; 1078 struct afe_port_param_data_v2 *pdata; 1079 struct apr_pkt *pkt; 1080 int ret, pkt_size; 1081 void *p, *pl; 1082 1083 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1084 p = kzalloc(pkt_size, GFP_KERNEL); 1085 if (!p) 1086 return -ENOMEM; 1087 1088 pkt = p; 1089 param = p + APR_HDR_SIZE; 1090 pdata = p + APR_HDR_SIZE + sizeof(*param); 1091 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1092 memcpy(pl, data, psize); 1093 1094 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1095 APR_HDR_LEN(APR_HDR_SIZE), 1096 APR_PKT_VER); 1097 pkt->hdr.pkt_size = pkt_size; 1098 pkt->hdr.src_port = 0; 1099 pkt->hdr.dest_port = 0; 1100 pkt->hdr.token = token; 1101 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 1102 1103 param->payload_size = sizeof(*pdata) + psize; 1104 param->payload_address_lsw = 0x00; 1105 param->payload_address_msw = 0x00; 1106 param->mem_map_handle = 0x00; 1107 pdata->module_id = module_id; 1108 pdata->param_id = param_id; 1109 pdata->param_size = psize; 1110 1111 ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); 1112 if (ret) 1113 dev_err(afe->dev, "AFE set params failed %d\n", ret); 1114 1115 kfree(pkt); 1116 return ret; 1117 } 1118 1119 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 1120 int param_id, int module_id, int psize) 1121 { 1122 return q6afe_set_param(port->afe, port, data, param_id, module_id, 1123 psize, port->token); 1124 } 1125 1126 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 1127 int param_id, int module_id, int psize) 1128 { 1129 struct afe_port_cmd_set_param_v2 *param; 1130 struct afe_port_param_data_v2 *pdata; 1131 struct q6afe *afe = port->afe; 1132 struct apr_pkt *pkt; 1133 u16 port_id = port->id; 1134 int ret, pkt_size; 1135 void *p, *pl; 1136 1137 pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1138 p = kzalloc(pkt_size, GFP_KERNEL); 1139 if (!p) 1140 return -ENOMEM; 1141 1142 pkt = p; 1143 param = p + APR_HDR_SIZE; 1144 pdata = p + APR_HDR_SIZE + sizeof(*param); 1145 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1146 memcpy(pl, data, psize); 1147 1148 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1149 APR_HDR_LEN(APR_HDR_SIZE), 1150 APR_PKT_VER); 1151 pkt->hdr.pkt_size = pkt_size; 1152 pkt->hdr.src_port = 0; 1153 pkt->hdr.dest_port = 0; 1154 pkt->hdr.token = port->token; 1155 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 1156 1157 param->port_id = port_id; 1158 param->payload_size = sizeof(*pdata) + psize; 1159 param->payload_address_lsw = 0x00; 1160 param->payload_address_msw = 0x00; 1161 param->mem_map_handle = 0x00; 1162 pdata->module_id = module_id; 1163 pdata->param_id = param_id; 1164 pdata->param_size = psize; 1165 1166 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); 1167 if (ret) 1168 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1169 port_id, ret); 1170 1171 kfree(pkt); 1172 return ret; 1173 } 1174 1175 static int q6afe_port_set_lpass_clock(struct q6afe_port *port, 1176 struct afe_clk_cfg *cfg) 1177 { 1178 return q6afe_port_set_param_v2(port, cfg, 1179 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 1180 AFE_MODULE_AUDIO_DEV_INTERFACE, 1181 sizeof(*cfg)); 1182 } 1183 1184 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 1185 struct afe_clk_set *cfg) 1186 { 1187 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 1188 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 1189 } 1190 1191 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 1192 struct afe_digital_clk_cfg *cfg) 1193 { 1194 return q6afe_port_set_param_v2(port, cfg, 1195 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 1196 AFE_MODULE_AUDIO_DEV_INTERFACE, 1197 sizeof(*cfg)); 1198 } 1199 1200 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 1201 int clk_root, unsigned int freq) 1202 { 1203 struct q6afe *afe = dev_get_drvdata(dev->parent); 1204 struct afe_clk_set cset = {0,}; 1205 1206 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1207 cset.clk_id = clk_id; 1208 cset.clk_freq_in_hz = freq; 1209 cset.clk_attri = attri; 1210 cset.clk_root = clk_root; 1211 cset.enable = !!freq; 1212 1213 return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, 1214 AFE_MODULE_CLOCK_SET, sizeof(cset), 1215 AFE_CLK_TOKEN); 1216 } 1217 EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); 1218 1219 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 1220 int clk_src, int clk_root, 1221 unsigned int freq, int dir) 1222 { 1223 struct afe_clk_cfg ccfg = {0,}; 1224 struct afe_clk_set cset = {0,}; 1225 struct afe_digital_clk_cfg dcfg = {0,}; 1226 int ret; 1227 1228 switch (clk_id) { 1229 case LPAIF_DIG_CLK: 1230 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1231 dcfg.clk_val = freq; 1232 dcfg.clk_root = clk_root; 1233 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 1234 break; 1235 case LPAIF_BIT_CLK: 1236 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1237 ccfg.clk_val1 = freq; 1238 ccfg.clk_src = clk_src; 1239 ccfg.clk_root = clk_root; 1240 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 1241 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1242 break; 1243 1244 case LPAIF_OSR_CLK: 1245 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1246 ccfg.clk_val2 = freq; 1247 ccfg.clk_src = clk_src; 1248 ccfg.clk_root = clk_root; 1249 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1250 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1251 break; 1252 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1253 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1254 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1255 case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: 1256 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1257 cset.clk_id = clk_id; 1258 cset.clk_freq_in_hz = freq; 1259 cset.clk_attri = clk_src; 1260 cset.clk_root = clk_root; 1261 cset.enable = !!freq; 1262 ret = q6afe_set_lpass_clock_v2(port, &cset); 1263 break; 1264 default: 1265 ret = -EINVAL; 1266 break; 1267 } 1268 1269 return ret; 1270 } 1271 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1272 1273 /** 1274 * q6afe_port_stop() - Stop a afe port 1275 * 1276 * @port: Instance of port to stop 1277 * 1278 * Return: Will be an negative on packet size on success. 1279 */ 1280 int q6afe_port_stop(struct q6afe_port *port) 1281 { 1282 struct afe_port_cmd_device_stop *stop; 1283 struct q6afe *afe = port->afe; 1284 struct apr_pkt *pkt; 1285 int port_id = port->id; 1286 int ret = 0; 1287 int index, pkt_size; 1288 void *p; 1289 1290 index = port->token; 1291 if (index < 0 || index >= AFE_PORT_MAX) { 1292 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1293 return -EINVAL; 1294 } 1295 1296 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1297 p = kzalloc(pkt_size, GFP_KERNEL); 1298 if (!p) 1299 return -ENOMEM; 1300 1301 pkt = p; 1302 stop = p + APR_HDR_SIZE; 1303 1304 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1305 APR_HDR_LEN(APR_HDR_SIZE), 1306 APR_PKT_VER); 1307 pkt->hdr.pkt_size = pkt_size; 1308 pkt->hdr.src_port = 0; 1309 pkt->hdr.dest_port = 0; 1310 pkt->hdr.token = index; 1311 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1312 stop->port_id = port_id; 1313 stop->reserved = 0; 1314 1315 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); 1316 if (ret) 1317 dev_err(afe->dev, "AFE close failed %d\n", ret); 1318 1319 kfree(pkt); 1320 return ret; 1321 } 1322 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1323 1324 /** 1325 * q6afe_slim_port_prepare() - Prepare slim afe port. 1326 * 1327 * @port: Instance of afe port 1328 * @cfg: SLIM configuration for the afe port 1329 * 1330 */ 1331 void q6afe_slim_port_prepare(struct q6afe_port *port, 1332 struct q6afe_slim_cfg *cfg) 1333 { 1334 union afe_port_config *pcfg = &port->port_cfg; 1335 1336 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1337 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1338 pcfg->slim_cfg.bit_width = cfg->bit_width; 1339 pcfg->slim_cfg.num_channels = cfg->num_channels; 1340 pcfg->slim_cfg.data_format = cfg->data_format; 1341 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1342 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1343 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1344 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1345 1346 } 1347 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1348 1349 /** 1350 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1351 * 1352 * @port: Instance of afe port 1353 * @cfg: TDM configuration for the afe port 1354 * 1355 */ 1356 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1357 struct q6afe_tdm_cfg *cfg) 1358 { 1359 union afe_port_config *pcfg = &port->port_cfg; 1360 1361 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1362 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1363 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1364 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1365 pcfg->tdm_cfg.data_format = cfg->data_format; 1366 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1367 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1368 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1369 1370 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1371 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1372 port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL); 1373 if (!port->scfg) 1374 return; 1375 1376 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1377 port->scfg->num_channels = cfg->num_channels; 1378 port->scfg->bitwidth = cfg->bit_width; 1379 port->scfg->data_align_type = cfg->data_align_type; 1380 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1381 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1382 } 1383 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1384 1385 /** 1386 * afe_port_send_usb_dev_param() - Send USB dev token 1387 * 1388 * @port: Instance of afe port 1389 * @cardidx: USB SND card index to reference 1390 * @pcmidx: USB SND PCM device index to reference 1391 * 1392 * The USB dev token carries information about which USB SND card instance and 1393 * PCM device to execute the offload on. This information is carried through 1394 * to the stream enable QMI request, which is handled by the offload class 1395 * driver. The information is parsed to determine which USB device to query 1396 * the required resources for. 1397 */ 1398 int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx) 1399 { 1400 struct afe_param_id_usb_audio_dev_params usb_dev; 1401 int ret; 1402 1403 memset(&usb_dev, 0, sizeof(usb_dev)); 1404 1405 usb_dev.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1406 usb_dev.dev_token = (cardidx << 16) | (pcmidx << 8); 1407 ret = q6afe_port_set_param_v2(port, &usb_dev, 1408 AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS, 1409 AFE_MODULE_AUDIO_DEV_INTERFACE, 1410 sizeof(usb_dev)); 1411 if (ret) 1412 dev_err(port->afe->dev, "%s: AFE device param cmd failed %d\n", 1413 __func__, ret); 1414 1415 return ret; 1416 } 1417 EXPORT_SYMBOL_GPL(afe_port_send_usb_dev_param); 1418 1419 static int afe_port_send_usb_params(struct q6afe_port *port, struct q6afe_usb_cfg *cfg) 1420 { 1421 union afe_port_config *pcfg = &port->port_cfg; 1422 struct afe_param_id_usb_audio_dev_lpcm_fmt lpcm_fmt; 1423 struct afe_param_id_usb_audio_svc_interval svc_int; 1424 int ret; 1425 1426 if (!pcfg) { 1427 dev_err(port->afe->dev, "%s: Error, no configuration data\n", __func__); 1428 return -EINVAL; 1429 } 1430 1431 memset(&lpcm_fmt, 0, sizeof(lpcm_fmt)); 1432 memset(&svc_int, 0, sizeof(svc_int)); 1433 1434 lpcm_fmt.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1435 lpcm_fmt.endian = pcfg->usb_cfg.endian; 1436 ret = q6afe_port_set_param_v2(port, &lpcm_fmt, 1437 AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT, 1438 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(lpcm_fmt)); 1439 if (ret) { 1440 dev_err(port->afe->dev, "%s: AFE device param cmd LPCM_FMT failed %d\n", 1441 __func__, ret); 1442 return ret; 1443 } 1444 1445 svc_int.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1446 svc_int.svc_interval = pcfg->usb_cfg.service_interval; 1447 ret = q6afe_port_set_param_v2(port, &svc_int, 1448 AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL, 1449 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(svc_int)); 1450 if (ret) 1451 dev_err(port->afe->dev, "%s: AFE device param cmd svc_interval failed %d\n", 1452 __func__, ret); 1453 1454 return ret; 1455 } 1456 1457 /** 1458 * q6afe_usb_port_prepare() - Prepare usb afe port. 1459 * 1460 * @port: Instance of afe port 1461 * @cfg: USB configuration for the afe port 1462 * 1463 */ 1464 void q6afe_usb_port_prepare(struct q6afe_port *port, 1465 struct q6afe_usb_cfg *cfg) 1466 { 1467 union afe_port_config *pcfg = &port->port_cfg; 1468 1469 pcfg->usb_cfg.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1470 pcfg->usb_cfg.sample_rate = cfg->sample_rate; 1471 pcfg->usb_cfg.num_channels = cfg->num_channels; 1472 pcfg->usb_cfg.bit_width = cfg->bit_width; 1473 1474 afe_port_send_usb_params(port, cfg); 1475 } 1476 EXPORT_SYMBOL_GPL(q6afe_usb_port_prepare); 1477 1478 /** 1479 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1480 * 1481 * @port: Instance of afe port 1482 * @cfg: HDMI configuration for the afe port 1483 * 1484 */ 1485 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1486 struct q6afe_hdmi_cfg *cfg) 1487 { 1488 union afe_port_config *pcfg = &port->port_cfg; 1489 1490 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1491 AFE_API_VERSION_HDMI_CONFIG; 1492 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1493 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1494 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1495 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1496 } 1497 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1498 1499 /** 1500 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1501 * 1502 * @port: Instance of afe port 1503 * @cfg: I2S configuration for the afe port 1504 * Return: Will be an negative on error and zero on success. 1505 */ 1506 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1507 { 1508 union afe_port_config *pcfg = &port->port_cfg; 1509 struct device *dev = port->afe->dev; 1510 int num_sd_lines; 1511 1512 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1513 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1514 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1515 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1516 1517 switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1518 case SND_SOC_DAIFMT_BP_FP: 1519 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1520 break; 1521 case SND_SOC_DAIFMT_BC_FC: 1522 /* CPU is slave */ 1523 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1524 break; 1525 default: 1526 break; 1527 } 1528 1529 num_sd_lines = hweight_long(cfg->sd_line_mask); 1530 1531 switch (num_sd_lines) { 1532 case 0: 1533 dev_err(dev, "no line is assigned\n"); 1534 return -EINVAL; 1535 case 1: 1536 switch (cfg->sd_line_mask) { 1537 case AFE_PORT_I2S_SD0_MASK: 1538 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1539 break; 1540 case AFE_PORT_I2S_SD1_MASK: 1541 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1542 break; 1543 case AFE_PORT_I2S_SD2_MASK: 1544 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1545 break; 1546 case AFE_PORT_I2S_SD3_MASK: 1547 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1548 break; 1549 default: 1550 dev_err(dev, "Invalid SD lines\n"); 1551 return -EINVAL; 1552 } 1553 break; 1554 case 2: 1555 switch (cfg->sd_line_mask) { 1556 case AFE_PORT_I2S_SD0_1_MASK: 1557 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1558 break; 1559 case AFE_PORT_I2S_SD2_3_MASK: 1560 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1561 break; 1562 default: 1563 dev_err(dev, "Invalid SD lines\n"); 1564 return -EINVAL; 1565 } 1566 break; 1567 case 3: 1568 switch (cfg->sd_line_mask) { 1569 case AFE_PORT_I2S_SD0_1_2_MASK: 1570 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1571 break; 1572 default: 1573 dev_err(dev, "Invalid SD lines\n"); 1574 return -EINVAL; 1575 } 1576 break; 1577 case 4: 1578 switch (cfg->sd_line_mask) { 1579 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1580 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1581 1582 break; 1583 default: 1584 dev_err(dev, "Invalid SD lines\n"); 1585 return -EINVAL; 1586 } 1587 break; 1588 default: 1589 dev_err(dev, "Invalid SD lines\n"); 1590 return -EINVAL; 1591 } 1592 1593 switch (cfg->num_channels) { 1594 case 1: 1595 case 2: 1596 switch (pcfg->i2s_cfg.channel_mode) { 1597 case AFE_PORT_I2S_QUAD01: 1598 case AFE_PORT_I2S_6CHS: 1599 case AFE_PORT_I2S_8CHS: 1600 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1601 break; 1602 case AFE_PORT_I2S_QUAD23: 1603 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1604 break; 1605 } 1606 1607 if (cfg->num_channels == 2) 1608 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1609 else 1610 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1611 1612 break; 1613 case 3: 1614 case 4: 1615 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1616 dev_err(dev, "Invalid Channel mode\n"); 1617 return -EINVAL; 1618 } 1619 break; 1620 case 5: 1621 case 6: 1622 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1623 dev_err(dev, "Invalid Channel mode\n"); 1624 return -EINVAL; 1625 } 1626 break; 1627 case 7: 1628 case 8: 1629 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1630 dev_err(dev, "Invalid Channel mode\n"); 1631 return -EINVAL; 1632 } 1633 break; 1634 default: 1635 break; 1636 } 1637 1638 return 0; 1639 } 1640 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1641 1642 /** 1643 * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. 1644 * 1645 * @port: Instance of afe port 1646 * @cfg: DMA configuration for the afe port 1647 * 1648 */ 1649 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 1650 struct q6afe_cdc_dma_cfg *cfg) 1651 { 1652 union afe_port_config *pcfg = &port->port_cfg; 1653 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; 1654 1655 dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; 1656 dma_cfg->sample_rate = cfg->sample_rate; 1657 dma_cfg->bit_width = cfg->bit_width; 1658 dma_cfg->data_format = cfg->data_format; 1659 dma_cfg->num_channels = cfg->num_channels; 1660 if (!cfg->active_channels_mask) 1661 dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; 1662 } 1663 EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); 1664 /** 1665 * q6afe_port_start() - Start a afe port 1666 * 1667 * @port: Instance of port to start 1668 * 1669 * Return: Will be an negative on packet size on success. 1670 */ 1671 int q6afe_port_start(struct q6afe_port *port) 1672 { 1673 struct afe_port_cmd_device_start *start; 1674 struct q6afe *afe = port->afe; 1675 int port_id = port->id; 1676 int ret, param_id = port->cfg_type; 1677 struct apr_pkt *pkt; 1678 int pkt_size; 1679 void *p; 1680 1681 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1682 AFE_MODULE_AUDIO_DEV_INTERFACE, 1683 sizeof(port->port_cfg)); 1684 if (ret) { 1685 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1686 port_id, ret); 1687 return ret; 1688 } 1689 1690 if (port->scfg) { 1691 ret = q6afe_port_set_param_v2(port, port->scfg, 1692 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1693 AFE_MODULE_TDM, sizeof(*port->scfg)); 1694 if (ret) { 1695 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1696 port_id, ret); 1697 return ret; 1698 } 1699 } 1700 1701 pkt_size = APR_HDR_SIZE + sizeof(*start); 1702 p = kzalloc(pkt_size, GFP_KERNEL); 1703 if (!p) 1704 return -ENOMEM; 1705 1706 pkt = p; 1707 start = p + APR_HDR_SIZE; 1708 1709 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1710 APR_HDR_LEN(APR_HDR_SIZE), 1711 APR_PKT_VER); 1712 pkt->hdr.pkt_size = pkt_size; 1713 pkt->hdr.src_port = 0; 1714 pkt->hdr.dest_port = 0; 1715 pkt->hdr.token = port->token; 1716 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1717 1718 start->port_id = port_id; 1719 1720 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); 1721 if (ret) 1722 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1723 port_id, ret); 1724 1725 kfree(pkt); 1726 return ret; 1727 } 1728 EXPORT_SYMBOL_GPL(q6afe_port_start); 1729 1730 /** 1731 * q6afe_port_get_from_id() - Get port instance from a port id 1732 * 1733 * @dev: Pointer to afe child device. 1734 * @id: port id 1735 * 1736 * Return: Will be an error pointer on error or a valid afe port 1737 * on success. 1738 */ 1739 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1740 { 1741 int port_id; 1742 struct q6afe *afe = dev_get_drvdata(dev->parent); 1743 struct q6afe_port *port; 1744 unsigned long flags; 1745 int cfg_type; 1746 1747 if (id < 0 || id >= AFE_PORT_MAX) { 1748 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1749 return ERR_PTR(-EINVAL); 1750 } 1751 1752 /* if port is multiple times bind/unbind before callback finishes */ 1753 port = q6afe_find_port(afe, id); 1754 if (port) { 1755 dev_err(dev, "AFE Port already open\n"); 1756 return port; 1757 } 1758 1759 port_id = port_maps[id].port_id; 1760 1761 switch (port_id) { 1762 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1763 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1764 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1765 break; 1766 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1767 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1768 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1769 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1770 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1771 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1772 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1773 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1774 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1775 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1776 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1777 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1778 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1779 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1780 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1781 break; 1782 1783 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1784 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1785 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1786 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1787 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1788 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1789 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1790 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1791 case AFE_PORT_ID_QUINARY_MI2S_RX: 1792 case AFE_PORT_ID_QUINARY_MI2S_TX: 1793 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1794 break; 1795 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1796 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1797 break; 1798 case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: 1799 cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; 1800 break; 1801 case AFE_PORT_ID_USB_RX: 1802 cfg_type = AFE_PARAM_ID_USB_AUDIO_CONFIG; 1803 break; 1804 default: 1805 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1806 return ERR_PTR(-EINVAL); 1807 } 1808 1809 port = kzalloc(sizeof(*port), GFP_KERNEL); 1810 if (!port) 1811 return ERR_PTR(-ENOMEM); 1812 1813 init_waitqueue_head(&port->wait); 1814 1815 port->token = id; 1816 port->id = port_id; 1817 port->afe = afe; 1818 port->cfg_type = cfg_type; 1819 kref_init(&port->refcount); 1820 1821 spin_lock_irqsave(&afe->port_list_lock, flags); 1822 list_add_tail(&port->node, &afe->port_list); 1823 spin_unlock_irqrestore(&afe->port_list_lock, flags); 1824 1825 return port; 1826 1827 } 1828 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1829 1830 /** 1831 * q6afe_port_put() - Release port reference 1832 * 1833 * @port: Instance of port to put 1834 */ 1835 void q6afe_port_put(struct q6afe_port *port) 1836 { 1837 kref_put(&port->refcount, q6afe_port_free); 1838 } 1839 EXPORT_SYMBOL_GPL(q6afe_port_put); 1840 1841 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1842 uint32_t client_handle) 1843 { 1844 struct q6afe *afe = dev_get_drvdata(dev->parent); 1845 struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; 1846 struct apr_pkt *pkt; 1847 int ret = 0; 1848 int pkt_size; 1849 void *p; 1850 1851 pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1852 p = kzalloc(pkt_size, GFP_KERNEL); 1853 if (!p) 1854 return -ENOMEM; 1855 1856 pkt = p; 1857 vote_cfg = p + APR_HDR_SIZE; 1858 1859 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1860 APR_HDR_LEN(APR_HDR_SIZE), 1861 APR_PKT_VER); 1862 pkt->hdr.pkt_size = pkt_size; 1863 pkt->hdr.src_port = 0; 1864 pkt->hdr.dest_port = 0; 1865 pkt->hdr.token = hw_block_id; 1866 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; 1867 vote_cfg->hw_block_id = hw_block_id; 1868 vote_cfg->client_handle = client_handle; 1869 1870 ret = apr_send_pkt(afe->apr, pkt); 1871 if (ret < 0) 1872 dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); 1873 1874 kfree(pkt); 1875 return ret; 1876 } 1877 EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); 1878 1879 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1880 const char *client_name, uint32_t *client_handle) 1881 { 1882 struct q6afe *afe = dev_get_drvdata(dev->parent); 1883 struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; 1884 struct apr_pkt *pkt; 1885 int ret = 0; 1886 int pkt_size; 1887 void *p; 1888 1889 pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1890 p = kzalloc(pkt_size, GFP_KERNEL); 1891 if (!p) 1892 return -ENOMEM; 1893 1894 pkt = p; 1895 vote_cfg = p + APR_HDR_SIZE; 1896 1897 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1898 APR_HDR_LEN(APR_HDR_SIZE), 1899 APR_PKT_VER); 1900 pkt->hdr.pkt_size = pkt_size; 1901 pkt->hdr.src_port = 0; 1902 pkt->hdr.dest_port = 0; 1903 pkt->hdr.token = hw_block_id; 1904 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; 1905 vote_cfg->hw_block_id = hw_block_id; 1906 strscpy(vote_cfg->client_name, client_name, 1907 sizeof(vote_cfg->client_name)); 1908 1909 ret = afe_apr_send_pkt(afe, pkt, NULL, 1910 AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); 1911 if (ret) 1912 dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); 1913 1914 1915 kfree(pkt); 1916 return ret; 1917 } 1918 EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); 1919 1920 static int q6afe_probe(struct apr_device *adev) 1921 { 1922 struct q6afe *afe; 1923 struct device *dev = &adev->dev; 1924 1925 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1926 if (!afe) 1927 return -ENOMEM; 1928 1929 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1930 afe->apr = adev; 1931 mutex_init(&afe->lock); 1932 init_waitqueue_head(&afe->wait); 1933 afe->dev = dev; 1934 INIT_LIST_HEAD(&afe->port_list); 1935 spin_lock_init(&afe->port_list_lock); 1936 1937 dev_set_drvdata(dev, afe); 1938 1939 return devm_of_platform_populate(dev); 1940 } 1941 1942 #ifdef CONFIG_OF 1943 static const struct of_device_id q6afe_device_id[] = { 1944 { .compatible = "qcom,q6afe" }, 1945 {}, 1946 }; 1947 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1948 #endif 1949 1950 static struct apr_driver qcom_q6afe_driver = { 1951 .probe = q6afe_probe, 1952 .callback = q6afe_callback, 1953 .driver = { 1954 .name = "qcom-q6afe", 1955 .of_match_table = of_match_ptr(q6afe_device_id), 1956 1957 }, 1958 }; 1959 1960 module_apr_driver(qcom_q6afe_driver); 1961 MODULE_DESCRIPTION("Q6 Audio Front End"); 1962 MODULE_LICENSE("GPL v2"); 1963