1 /* 2 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * lpass-platform.c -- ALSA SoC platform driver for QTi LPASS 14 */ 15 16 #include <linux/dma-mapping.h> 17 #include <linux/export.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <sound/pcm_params.h> 22 #include <linux/regmap.h> 23 #include <sound/soc.h> 24 #include "lpass-lpaif-reg.h" 25 #include "lpass.h" 26 27 struct lpass_pcm_data { 28 int rdma_ch; 29 int wrdma_ch; 30 int i2s_port; 31 }; 32 33 #define LPASS_PLATFORM_BUFFER_SIZE (16 * 1024) 34 #define LPASS_PLATFORM_PERIODS 2 35 36 static struct snd_pcm_hardware lpass_platform_pcm_hardware = { 37 .info = SNDRV_PCM_INFO_MMAP | 38 SNDRV_PCM_INFO_MMAP_VALID | 39 SNDRV_PCM_INFO_INTERLEAVED | 40 SNDRV_PCM_INFO_PAUSE | 41 SNDRV_PCM_INFO_RESUME, 42 .formats = SNDRV_PCM_FMTBIT_S16 | 43 SNDRV_PCM_FMTBIT_S24 | 44 SNDRV_PCM_FMTBIT_S32, 45 .rates = SNDRV_PCM_RATE_8000_192000, 46 .rate_min = 8000, 47 .rate_max = 192000, 48 .channels_min = 1, 49 .channels_max = 8, 50 .buffer_bytes_max = LPASS_PLATFORM_BUFFER_SIZE, 51 .period_bytes_max = LPASS_PLATFORM_BUFFER_SIZE / 52 LPASS_PLATFORM_PERIODS, 53 .period_bytes_min = LPASS_PLATFORM_BUFFER_SIZE / 54 LPASS_PLATFORM_PERIODS, 55 .periods_min = LPASS_PLATFORM_PERIODS, 56 .periods_max = LPASS_PLATFORM_PERIODS, 57 .fifo_size = 0, 58 }; 59 60 static int lpass_platform_pcmops_open(struct snd_pcm_substream *substream) 61 { 62 struct snd_pcm_runtime *runtime = substream->runtime; 63 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 64 struct snd_soc_dai *cpu_dai = soc_runtime->cpu_dai; 65 struct lpass_data *drvdata = 66 snd_soc_platform_get_drvdata(soc_runtime->platform); 67 struct lpass_variant *v = drvdata->variant; 68 int ret, dma_ch, dir = substream->stream; 69 struct lpass_pcm_data *data; 70 71 data = devm_kzalloc(soc_runtime->dev, sizeof(*data), GFP_KERNEL); 72 if (!data) 73 return -ENOMEM; 74 75 data->i2s_port = cpu_dai->driver->id; 76 runtime->private_data = data; 77 78 if (v->alloc_dma_channel) 79 dma_ch = v->alloc_dma_channel(drvdata, dir); 80 if (dma_ch < 0) 81 return dma_ch; 82 83 drvdata->substream[dma_ch] = substream; 84 85 ret = regmap_write(drvdata->lpaif_map, 86 LPAIF_DMACTL_REG(v, dma_ch, dir), 0); 87 if (ret) { 88 dev_err(soc_runtime->dev, 89 "%s() error writing to rdmactl reg: %d\n", 90 __func__, ret); 91 return ret; 92 } 93 94 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 95 data->rdma_ch = dma_ch; 96 else 97 data->wrdma_ch = dma_ch; 98 99 snd_soc_set_runtime_hwparams(substream, &lpass_platform_pcm_hardware); 100 101 runtime->dma_bytes = lpass_platform_pcm_hardware.buffer_bytes_max; 102 103 ret = snd_pcm_hw_constraint_integer(runtime, 104 SNDRV_PCM_HW_PARAM_PERIODS); 105 if (ret < 0) { 106 dev_err(soc_runtime->dev, "%s() setting constraints failed: %d\n", 107 __func__, ret); 108 return -EINVAL; 109 } 110 111 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer); 112 113 return 0; 114 } 115 116 static int lpass_platform_pcmops_close(struct snd_pcm_substream *substream) 117 { 118 struct snd_pcm_runtime *runtime = substream->runtime; 119 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 120 struct lpass_data *drvdata = 121 snd_soc_platform_get_drvdata(soc_runtime->platform); 122 struct lpass_variant *v = drvdata->variant; 123 struct lpass_pcm_data *data; 124 int dma_ch, dir = substream->stream; 125 126 data = runtime->private_data; 127 v = drvdata->variant; 128 129 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 130 dma_ch = data->rdma_ch; 131 else 132 dma_ch = data->wrdma_ch; 133 134 drvdata->substream[dma_ch] = NULL; 135 136 if (v->free_dma_channel) 137 v->free_dma_channel(drvdata, dma_ch); 138 139 return 0; 140 } 141 142 static int lpass_platform_pcmops_hw_params(struct snd_pcm_substream *substream, 143 struct snd_pcm_hw_params *params) 144 { 145 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 146 struct lpass_data *drvdata = 147 snd_soc_platform_get_drvdata(soc_runtime->platform); 148 struct snd_pcm_runtime *rt = substream->runtime; 149 struct lpass_pcm_data *pcm_data = rt->private_data; 150 struct lpass_variant *v = drvdata->variant; 151 snd_pcm_format_t format = params_format(params); 152 unsigned int channels = params_channels(params); 153 unsigned int regval; 154 int ch, dir = substream->stream; 155 int bitwidth; 156 int ret, dma_port = pcm_data->i2s_port + v->dmactl_audif_start; 157 158 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 159 ch = pcm_data->rdma_ch; 160 else 161 ch = pcm_data->wrdma_ch; 162 163 bitwidth = snd_pcm_format_width(format); 164 if (bitwidth < 0) { 165 dev_err(soc_runtime->dev, "%s() invalid bit width given: %d\n", 166 __func__, bitwidth); 167 return bitwidth; 168 } 169 170 regval = LPAIF_DMACTL_BURSTEN_INCR4 | 171 LPAIF_DMACTL_AUDINTF(dma_port) | 172 LPAIF_DMACTL_FIFOWM_8; 173 174 switch (bitwidth) { 175 case 16: 176 switch (channels) { 177 case 1: 178 case 2: 179 regval |= LPAIF_DMACTL_WPSCNT_ONE; 180 break; 181 case 4: 182 regval |= LPAIF_DMACTL_WPSCNT_TWO; 183 break; 184 case 6: 185 regval |= LPAIF_DMACTL_WPSCNT_THREE; 186 break; 187 case 8: 188 regval |= LPAIF_DMACTL_WPSCNT_FOUR; 189 break; 190 default: 191 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", 192 __func__, bitwidth, channels); 193 return -EINVAL; 194 } 195 break; 196 case 24: 197 case 32: 198 switch (channels) { 199 case 1: 200 regval |= LPAIF_DMACTL_WPSCNT_ONE; 201 break; 202 case 2: 203 regval |= LPAIF_DMACTL_WPSCNT_TWO; 204 break; 205 case 4: 206 regval |= LPAIF_DMACTL_WPSCNT_FOUR; 207 break; 208 case 6: 209 regval |= LPAIF_DMACTL_WPSCNT_SIX; 210 break; 211 case 8: 212 regval |= LPAIF_DMACTL_WPSCNT_EIGHT; 213 break; 214 default: 215 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", 216 __func__, bitwidth, channels); 217 return -EINVAL; 218 } 219 break; 220 default: 221 dev_err(soc_runtime->dev, "%s() invalid PCM config given: bw=%d, ch=%u\n", 222 __func__, bitwidth, channels); 223 return -EINVAL; 224 } 225 226 ret = regmap_write(drvdata->lpaif_map, 227 LPAIF_DMACTL_REG(v, ch, dir), regval); 228 if (ret) { 229 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 230 __func__, ret); 231 return ret; 232 } 233 234 return 0; 235 } 236 237 static int lpass_platform_pcmops_hw_free(struct snd_pcm_substream *substream) 238 { 239 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 240 struct lpass_data *drvdata = 241 snd_soc_platform_get_drvdata(soc_runtime->platform); 242 struct snd_pcm_runtime *rt = substream->runtime; 243 struct lpass_pcm_data *pcm_data = rt->private_data; 244 struct lpass_variant *v = drvdata->variant; 245 unsigned int reg; 246 int ret; 247 248 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 249 reg = LPAIF_RDMACTL_REG(v, pcm_data->rdma_ch); 250 else 251 reg = LPAIF_WRDMACTL_REG(v, pcm_data->wrdma_ch); 252 253 ret = regmap_write(drvdata->lpaif_map, reg, 0); 254 if (ret) 255 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 256 __func__, ret); 257 258 return ret; 259 } 260 261 static int lpass_platform_pcmops_prepare(struct snd_pcm_substream *substream) 262 { 263 struct snd_pcm_runtime *runtime = substream->runtime; 264 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 265 struct lpass_data *drvdata = 266 snd_soc_platform_get_drvdata(soc_runtime->platform); 267 struct snd_pcm_runtime *rt = substream->runtime; 268 struct lpass_pcm_data *pcm_data = rt->private_data; 269 struct lpass_variant *v = drvdata->variant; 270 int ret, ch, dir = substream->stream; 271 272 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 273 ch = pcm_data->rdma_ch; 274 else 275 ch = pcm_data->wrdma_ch; 276 277 ret = regmap_write(drvdata->lpaif_map, 278 LPAIF_DMABASE_REG(v, ch, dir), 279 runtime->dma_addr); 280 if (ret) { 281 dev_err(soc_runtime->dev, "%s() error writing to rdmabase reg: %d\n", 282 __func__, ret); 283 return ret; 284 } 285 286 ret = regmap_write(drvdata->lpaif_map, 287 LPAIF_DMABUFF_REG(v, ch, dir), 288 (snd_pcm_lib_buffer_bytes(substream) >> 2) - 1); 289 if (ret) { 290 dev_err(soc_runtime->dev, "%s() error writing to rdmabuff reg: %d\n", 291 __func__, ret); 292 return ret; 293 } 294 295 ret = regmap_write(drvdata->lpaif_map, 296 LPAIF_DMAPER_REG(v, ch, dir), 297 (snd_pcm_lib_period_bytes(substream) >> 2) - 1); 298 if (ret) { 299 dev_err(soc_runtime->dev, "%s() error writing to rdmaper reg: %d\n", 300 __func__, ret); 301 return ret; 302 } 303 304 ret = regmap_update_bits(drvdata->lpaif_map, 305 LPAIF_DMACTL_REG(v, ch, dir), 306 LPAIF_DMACTL_ENABLE_MASK, LPAIF_DMACTL_ENABLE_ON); 307 if (ret) { 308 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 309 __func__, ret); 310 return ret; 311 } 312 313 return 0; 314 } 315 316 static int lpass_platform_pcmops_trigger(struct snd_pcm_substream *substream, 317 int cmd) 318 { 319 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 320 struct lpass_data *drvdata = 321 snd_soc_platform_get_drvdata(soc_runtime->platform); 322 struct snd_pcm_runtime *rt = substream->runtime; 323 struct lpass_pcm_data *pcm_data = rt->private_data; 324 struct lpass_variant *v = drvdata->variant; 325 int ret, ch, dir = substream->stream; 326 327 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 328 ch = pcm_data->rdma_ch; 329 else 330 ch = pcm_data->wrdma_ch; 331 332 switch (cmd) { 333 case SNDRV_PCM_TRIGGER_START: 334 case SNDRV_PCM_TRIGGER_RESUME: 335 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 336 /* clear status before enabling interrupts */ 337 ret = regmap_write(drvdata->lpaif_map, 338 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST), 339 LPAIF_IRQ_ALL(ch)); 340 if (ret) { 341 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", 342 __func__, ret); 343 return ret; 344 } 345 346 ret = regmap_update_bits(drvdata->lpaif_map, 347 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 348 LPAIF_IRQ_ALL(ch), 349 LPAIF_IRQ_ALL(ch)); 350 if (ret) { 351 dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n", 352 __func__, ret); 353 return ret; 354 } 355 356 ret = regmap_update_bits(drvdata->lpaif_map, 357 LPAIF_DMACTL_REG(v, ch, dir), 358 LPAIF_DMACTL_ENABLE_MASK, 359 LPAIF_DMACTL_ENABLE_ON); 360 if (ret) { 361 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 362 __func__, ret); 363 return ret; 364 } 365 break; 366 case SNDRV_PCM_TRIGGER_STOP: 367 case SNDRV_PCM_TRIGGER_SUSPEND: 368 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 369 ret = regmap_update_bits(drvdata->lpaif_map, 370 LPAIF_DMACTL_REG(v, ch, dir), 371 LPAIF_DMACTL_ENABLE_MASK, 372 LPAIF_DMACTL_ENABLE_OFF); 373 if (ret) { 374 dev_err(soc_runtime->dev, "%s() error writing to rdmactl reg: %d\n", 375 __func__, ret); 376 return ret; 377 } 378 379 ret = regmap_update_bits(drvdata->lpaif_map, 380 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 381 LPAIF_IRQ_ALL(ch), 0); 382 if (ret) { 383 dev_err(soc_runtime->dev, "%s() error writing to irqen reg: %d\n", 384 __func__, ret); 385 return ret; 386 } 387 break; 388 } 389 390 return 0; 391 } 392 393 static snd_pcm_uframes_t lpass_platform_pcmops_pointer( 394 struct snd_pcm_substream *substream) 395 { 396 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 397 struct lpass_data *drvdata = 398 snd_soc_platform_get_drvdata(soc_runtime->platform); 399 struct snd_pcm_runtime *rt = substream->runtime; 400 struct lpass_pcm_data *pcm_data = rt->private_data; 401 struct lpass_variant *v = drvdata->variant; 402 unsigned int base_addr, curr_addr; 403 int ret, ch, dir = substream->stream; 404 405 if (dir == SNDRV_PCM_STREAM_PLAYBACK) 406 ch = pcm_data->rdma_ch; 407 else 408 ch = pcm_data->wrdma_ch; 409 410 ret = regmap_read(drvdata->lpaif_map, 411 LPAIF_DMABASE_REG(v, ch, dir), &base_addr); 412 if (ret) { 413 dev_err(soc_runtime->dev, "%s() error reading from rdmabase reg: %d\n", 414 __func__, ret); 415 return ret; 416 } 417 418 ret = regmap_read(drvdata->lpaif_map, 419 LPAIF_DMACURR_REG(v, ch, dir), &curr_addr); 420 if (ret) { 421 dev_err(soc_runtime->dev, "%s() error reading from rdmacurr reg: %d\n", 422 __func__, ret); 423 return ret; 424 } 425 426 return bytes_to_frames(substream->runtime, curr_addr - base_addr); 427 } 428 429 static int lpass_platform_pcmops_mmap(struct snd_pcm_substream *substream, 430 struct vm_area_struct *vma) 431 { 432 struct snd_pcm_runtime *runtime = substream->runtime; 433 434 return dma_mmap_coherent(substream->pcm->card->dev, vma, 435 runtime->dma_area, runtime->dma_addr, 436 runtime->dma_bytes); 437 } 438 439 static const struct snd_pcm_ops lpass_platform_pcm_ops = { 440 .open = lpass_platform_pcmops_open, 441 .close = lpass_platform_pcmops_close, 442 .ioctl = snd_pcm_lib_ioctl, 443 .hw_params = lpass_platform_pcmops_hw_params, 444 .hw_free = lpass_platform_pcmops_hw_free, 445 .prepare = lpass_platform_pcmops_prepare, 446 .trigger = lpass_platform_pcmops_trigger, 447 .pointer = lpass_platform_pcmops_pointer, 448 .mmap = lpass_platform_pcmops_mmap, 449 }; 450 451 static irqreturn_t lpass_dma_interrupt_handler( 452 struct snd_pcm_substream *substream, 453 struct lpass_data *drvdata, 454 int chan, u32 interrupts) 455 { 456 struct snd_soc_pcm_runtime *soc_runtime = substream->private_data; 457 struct lpass_variant *v = drvdata->variant; 458 irqreturn_t ret = IRQ_NONE; 459 int rv; 460 461 if (interrupts & LPAIF_IRQ_PER(chan)) { 462 rv = regmap_write(drvdata->lpaif_map, 463 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST), 464 LPAIF_IRQ_PER(chan)); 465 if (rv) { 466 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", 467 __func__, rv); 468 return IRQ_NONE; 469 } 470 snd_pcm_period_elapsed(substream); 471 ret = IRQ_HANDLED; 472 } 473 474 if (interrupts & LPAIF_IRQ_XRUN(chan)) { 475 rv = regmap_write(drvdata->lpaif_map, 476 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST), 477 LPAIF_IRQ_XRUN(chan)); 478 if (rv) { 479 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", 480 __func__, rv); 481 return IRQ_NONE; 482 } 483 dev_warn(soc_runtime->dev, "%s() xrun warning\n", __func__); 484 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN); 485 ret = IRQ_HANDLED; 486 } 487 488 if (interrupts & LPAIF_IRQ_ERR(chan)) { 489 rv = regmap_write(drvdata->lpaif_map, 490 LPAIF_IRQCLEAR_REG(v, LPAIF_IRQ_PORT_HOST), 491 LPAIF_IRQ_ERR(chan)); 492 if (rv) { 493 dev_err(soc_runtime->dev, "%s() error writing to irqclear reg: %d\n", 494 __func__, rv); 495 return IRQ_NONE; 496 } 497 dev_err(soc_runtime->dev, "%s() bus access error\n", __func__); 498 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED); 499 ret = IRQ_HANDLED; 500 } 501 502 return ret; 503 } 504 505 static irqreturn_t lpass_platform_lpaif_irq(int irq, void *data) 506 { 507 struct lpass_data *drvdata = data; 508 struct lpass_variant *v = drvdata->variant; 509 unsigned int irqs; 510 int rv, chan; 511 512 rv = regmap_read(drvdata->lpaif_map, 513 LPAIF_IRQSTAT_REG(v, LPAIF_IRQ_PORT_HOST), &irqs); 514 if (rv) { 515 pr_err("%s() error reading from irqstat reg: %d\n", 516 __func__, rv); 517 return IRQ_NONE; 518 } 519 520 /* Handle per channel interrupts */ 521 for (chan = 0; chan < LPASS_MAX_DMA_CHANNELS; chan++) { 522 if (irqs & LPAIF_IRQ_ALL(chan) && drvdata->substream[chan]) { 523 rv = lpass_dma_interrupt_handler( 524 drvdata->substream[chan], 525 drvdata, chan, irqs); 526 if (rv != IRQ_HANDLED) 527 return rv; 528 } 529 } 530 531 return IRQ_HANDLED; 532 } 533 534 static int lpass_platform_pcm_new(struct snd_soc_pcm_runtime *soc_runtime) 535 { 536 struct snd_pcm *pcm = soc_runtime->pcm; 537 struct snd_pcm_substream *psubstream, *csubstream; 538 int ret = -EINVAL; 539 size_t size = lpass_platform_pcm_hardware.buffer_bytes_max; 540 541 psubstream = pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; 542 if (psubstream) { 543 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 544 soc_runtime->platform->dev, 545 size, &psubstream->dma_buffer); 546 if (ret) { 547 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n"); 548 return ret; 549 } 550 } 551 552 csubstream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; 553 if (csubstream) { 554 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, 555 soc_runtime->platform->dev, 556 size, &csubstream->dma_buffer); 557 if (ret) { 558 dev_err(soc_runtime->dev, "Cannot allocate buffer(s)\n"); 559 if (psubstream) 560 snd_dma_free_pages(&psubstream->dma_buffer); 561 return ret; 562 } 563 564 } 565 566 return 0; 567 } 568 569 static void lpass_platform_pcm_free(struct snd_pcm *pcm) 570 { 571 struct snd_pcm_substream *substream; 572 int i; 573 574 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) { 575 substream = pcm->streams[i].substream; 576 if (substream) { 577 snd_dma_free_pages(&substream->dma_buffer); 578 substream->dma_buffer.area = NULL; 579 substream->dma_buffer.addr = 0; 580 } 581 } 582 } 583 584 static struct snd_soc_platform_driver lpass_platform_driver = { 585 .pcm_new = lpass_platform_pcm_new, 586 .pcm_free = lpass_platform_pcm_free, 587 .ops = &lpass_platform_pcm_ops, 588 }; 589 590 int asoc_qcom_lpass_platform_register(struct platform_device *pdev) 591 { 592 struct lpass_data *drvdata = platform_get_drvdata(pdev); 593 struct lpass_variant *v = drvdata->variant; 594 int ret; 595 596 drvdata->lpaif_irq = platform_get_irq_byname(pdev, "lpass-irq-lpaif"); 597 if (drvdata->lpaif_irq < 0) { 598 dev_err(&pdev->dev, "%s() error getting irq handle: %d\n", 599 __func__, drvdata->lpaif_irq); 600 return -ENODEV; 601 } 602 603 /* ensure audio hardware is disabled */ 604 ret = regmap_write(drvdata->lpaif_map, 605 LPAIF_IRQEN_REG(v, LPAIF_IRQ_PORT_HOST), 0); 606 if (ret) { 607 dev_err(&pdev->dev, "%s() error writing to irqen reg: %d\n", 608 __func__, ret); 609 return ret; 610 } 611 612 ret = devm_request_irq(&pdev->dev, drvdata->lpaif_irq, 613 lpass_platform_lpaif_irq, IRQF_TRIGGER_RISING, 614 "lpass-irq-lpaif", drvdata); 615 if (ret) { 616 dev_err(&pdev->dev, "%s() irq request failed: %d\n", 617 __func__, ret); 618 return ret; 619 } 620 621 622 return devm_snd_soc_register_platform(&pdev->dev, 623 &lpass_platform_driver); 624 } 625 EXPORT_SYMBOL_GPL(asoc_qcom_lpass_platform_register); 626 627 MODULE_DESCRIPTION("QTi LPASS Platform Driver"); 628 MODULE_LICENSE("GPL v2"); 629