1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2010-2011,2013-2015 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __LPASS_LPAIF_REG_H__ 7 #define __LPASS_LPAIF_REG_H__ 8 9 /* LPAIF I2S */ 10 11 #define LPAIF_I2SCTL_REG_ADDR(v, addr, port) \ 12 (v->i2sctrl_reg_base + (addr) + v->i2sctrl_reg_stride * (port)) 13 14 #define LPAIF_I2SCTL_REG(v, port) LPAIF_I2SCTL_REG_ADDR(v, 0x0, (port)) 15 16 #define LPAIF_I2SCTL_LOOPBACK_DISABLE 0 17 #define LPAIF_I2SCTL_LOOPBACK_ENABLE 1 18 19 #define LPAIF_I2SCTL_SPKEN_DISABLE 0 20 #define LPAIF_I2SCTL_SPKEN_ENABLE 1 21 22 #define LPAIF_I2SCTL_MODE_NONE 0 23 #define LPAIF_I2SCTL_MODE_SD0 1 24 #define LPAIF_I2SCTL_MODE_SD1 2 25 #define LPAIF_I2SCTL_MODE_SD2 3 26 #define LPAIF_I2SCTL_MODE_SD3 4 27 #define LPAIF_I2SCTL_MODE_QUAD01 5 28 #define LPAIF_I2SCTL_MODE_QUAD23 6 29 #define LPAIF_I2SCTL_MODE_6CH 7 30 #define LPAIF_I2SCTL_MODE_8CH 8 31 #define LPAIF_I2SCTL_MODE_10CH 9 32 #define LPAIF_I2SCTL_MODE_12CH 10 33 #define LPAIF_I2SCTL_MODE_14CH 11 34 #define LPAIF_I2SCTL_MODE_16CH 12 35 #define LPAIF_I2SCTL_MODE_SD4 13 36 #define LPAIF_I2SCTL_MODE_SD5 14 37 #define LPAIF_I2SCTL_MODE_SD6 15 38 #define LPAIF_I2SCTL_MODE_SD7 16 39 #define LPAIF_I2SCTL_MODE_QUAD45 17 40 #define LPAIF_I2SCTL_MODE_QUAD47 18 41 #define LPAIF_I2SCTL_MODE_8CH_2 19 42 43 #define LPAIF_I2SCTL_SPKMODE(mode) mode 44 45 #define LPAIF_I2SCTL_SPKMONO_STEREO 0 46 #define LPAIF_I2SCTL_SPKMONO_MONO 1 47 48 #define LPAIF_I2SCTL_MICEN_DISABLE 0 49 #define LPAIF_I2SCTL_MICEN_ENABLE 1 50 51 #define LPAIF_I2SCTL_MICMODE(mode) mode 52 53 #define LPAIF_I2SCTL_MICMONO_STEREO 0 54 #define LPAIF_I2SCTL_MICMONO_MONO 1 55 56 #define LPAIF_I2SCTL_WSSRC_INTERNAL 0 57 #define LPAIF_I2SCTL_WSSRC_EXTERNAL 1 58 59 #define LPAIF_I2SCTL_BITWIDTH_16 0 60 #define LPAIF_I2SCTL_BITWIDTH_24 1 61 #define LPAIF_I2SCTL_BITWIDTH_32 2 62 63 #define LPAIF_I2SCTL_RESET_STATE 0x003C0004 64 #define LPAIF_DMACTL_RESET_STATE 0x00200000 65 66 67 /* LPAIF IRQ */ 68 #define LPAIF_IRQ_REG_ADDR(v, addr, port) \ 69 (v->irq_reg_base + (addr) + v->irq_reg_stride * (port)) 70 71 #define LPAIF_IRQ_PORT_HOST 0 72 73 #define LPAIF_IRQEN_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x0, (port)) 74 #define LPAIF_IRQSTAT_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0x4, (port)) 75 #define LPAIF_IRQCLEAR_REG(v, port) LPAIF_IRQ_REG_ADDR(v, 0xC, (port)) 76 77 78 #define LPASS_HDMITX_APP_IRQ_REG_ADDR(v, addr) \ 79 ((v->hdmi_irq_reg_base) + (addr)) 80 81 #define LPASS_HDMITX_APP_IRQEN_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x4) 82 #define LPASS_HDMITX_APP_IRQSTAT_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0x8) 83 #define LPASS_HDMITX_APP_IRQCLEAR_REG(v) LPASS_HDMITX_APP_IRQ_REG_ADDR(v, 0xC) 84 85 #define LPAIF_IRQ_BITSTRIDE 3 86 87 #define LPAIF_IRQ_PER(chan) (1 << (LPAIF_IRQ_BITSTRIDE * (chan))) 88 #define LPAIF_IRQ_XRUN(chan) (2 << (LPAIF_IRQ_BITSTRIDE * (chan))) 89 #define LPAIF_IRQ_ERR(chan) (4 << (LPAIF_IRQ_BITSTRIDE * (chan))) 90 91 #define LPAIF_IRQ_ALL(chan) (7 << (LPAIF_IRQ_BITSTRIDE * (chan))) 92 #define LPAIF_IRQ_HDMI_REQ_ON_PRELOAD(chan) (1 << (14 + chan)) 93 #define LPAIF_IRQ_HDMI_SDEEP_AUD_DIS(chan) (1 << (24 + chan)) 94 #define LPAIF_IRQ_HDMI_METADONE BIT(23) 95 96 /* LPAIF DMA */ 97 #define LPAIF_HDMI_RDMA_REG_ADDR(v, addr, chan) \ 98 (v->hdmi_rdma_reg_base + (addr) + v->hdmi_rdma_reg_stride * (chan)) 99 100 #define LPAIF_HDMI_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) 101 102 #define LPAIF_HDMI_RDMACTL_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x00, (chan)) 103 #define LPAIF_HDMI_RDMABASE_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x04, (chan)) 104 #define LPAIF_HDMI_RDMABUFF_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x08, (chan)) 105 #define LPAIF_HDMI_RDMACURR_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x0C, (chan)) 106 #define LPAIF_HDMI_RDMAPER_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x10, (chan)) 107 #define LPAIF_HDMI_RDMAPERCNT_REG(v, chan) LPAIF_HDMI_RDMA_REG_ADDR(v, 0x14, (chan)) 108 109 #define LPAIF_RDMA_REG_ADDR(v, addr, chan) \ 110 (v->rdma_reg_base + (addr) + v->rdma_reg_stride * (chan)) 111 112 #define LPAIF_RDMACTL_AUDINTF(id) (id << LPAIF_RDMACTL_AUDINTF_SHIFT) 113 114 #define LPAIF_RDMACTL_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x00, (chan)) 115 #define LPAIF_RDMABASE_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x04, (chan)) 116 #define LPAIF_RDMABUFF_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x08, (chan)) 117 #define LPAIF_RDMACURR_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x0C, (chan)) 118 #define LPAIF_RDMAPER_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x10, (chan)) 119 #define LPAIF_RDMAPERCNT_REG(v, chan) LPAIF_RDMA_REG_ADDR(v, 0x14, (chan)) 120 121 #define LPAIF_WRDMA_REG_ADDR(v, addr, chan) \ 122 (v->wrdma_reg_base + (addr) + \ 123 v->wrdma_reg_stride * (chan - v->wrdma_channel_start)) 124 125 #define LPAIF_WRDMACTL_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x00, (chan)) 126 #define LPAIF_WRDMABASE_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x04, (chan)) 127 #define LPAIF_WRDMABUFF_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x08, (chan)) 128 #define LPAIF_WRDMACURR_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x0C, (chan)) 129 #define LPAIF_WRDMAPER_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x10, (chan)) 130 #define LPAIF_WRDMAPERCNT_REG(v, chan) LPAIF_WRDMA_REG_ADDR(v, 0x14, (chan)) 131 132 #define LPAIF_INTFDMA_REG(v, chan, reg, dai_id) \ 133 ((dai_id == LPASS_DP_RX) ? \ 134 LPAIF_HDMI_RDMA##reg##_REG(v, chan) : \ 135 LPAIF_RDMA##reg##_REG(v, chan)) 136 137 #define __LPAIF_DMA_REG(v, chan, dir, reg, dai_id) \ 138 ((dir == SNDRV_PCM_STREAM_PLAYBACK) ? \ 139 (LPAIF_INTFDMA_REG(v, chan, reg, dai_id)) : \ 140 LPAIF_WRDMA##reg##_REG(v, chan)) 141 142 #define LPAIF_DMACTL_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CTL, dai_id) 143 #define LPAIF_DMABASE_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BASE, dai_id) 144 #define LPAIF_DMABUFF_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, BUFF, dai_id) 145 #define LPAIF_DMACURR_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, CURR, dai_id) 146 #define LPAIF_DMAPER_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PER, dai_id) 147 #define LPAIF_DMAPERCNT_REG(v, chan, dir, dai_id) __LPAIF_DMA_REG(v, chan, dir, PERCNT, dai_id) 148 149 #define LPAIF_DMACTL_BURSTEN_SINGLE 0 150 #define LPAIF_DMACTL_BURSTEN_INCR4 1 151 152 #define LPAIF_DMACTL_WPSCNT_ONE 0 153 #define LPAIF_DMACTL_WPSCNT_TWO 1 154 #define LPAIF_DMACTL_WPSCNT_THREE 2 155 #define LPAIF_DMACTL_WPSCNT_FOUR 3 156 #define LPAIF_DMACTL_WPSCNT_SIX 5 157 #define LPAIF_DMACTL_WPSCNT_EIGHT 7 158 #define LPAIF_DMACTL_WPSCNT_TEN 9 159 #define LPAIF_DMACTL_WPSCNT_TWELVE 11 160 #define LPAIF_DMACTL_WPSCNT_FOURTEEN 13 161 #define LPAIF_DMACTL_WPSCNT_SIXTEEN 15 162 163 #define LPAIF_DMACTL_AUDINTF(id) id 164 165 #define LPAIF_DMACTL_FIFOWM_1 0 166 #define LPAIF_DMACTL_FIFOWM_2 1 167 #define LPAIF_DMACTL_FIFOWM_3 2 168 #define LPAIF_DMACTL_FIFOWM_4 3 169 #define LPAIF_DMACTL_FIFOWM_5 4 170 #define LPAIF_DMACTL_FIFOWM_6 5 171 #define LPAIF_DMACTL_FIFOWM_7 6 172 #define LPAIF_DMACTL_FIFOWM_8 7 173 #define LPAIF_DMACTL_FIFOWM_9 8 174 #define LPAIF_DMACTL_FIFOWM_10 9 175 #define LPAIF_DMACTL_FIFOWM_11 10 176 #define LPAIF_DMACTL_FIFOWM_12 11 177 #define LPAIF_DMACTL_FIFOWM_13 12 178 #define LPAIF_DMACTL_FIFOWM_14 13 179 #define LPAIF_DMACTL_FIFOWM_15 14 180 #define LPAIF_DMACTL_FIFOWM_16 15 181 #define LPAIF_DMACTL_FIFOWM_17 16 182 #define LPAIF_DMACTL_FIFOWM_18 17 183 #define LPAIF_DMACTL_FIFOWM_19 18 184 #define LPAIF_DMACTL_FIFOWM_20 19 185 #define LPAIF_DMACTL_FIFOWM_21 20 186 #define LPAIF_DMACTL_FIFOWM_22 21 187 #define LPAIF_DMACTL_FIFOWM_23 22 188 #define LPAIF_DMACTL_FIFOWM_24 23 189 #define LPAIF_DMACTL_FIFOWM_25 24 190 #define LPAIF_DMACTL_FIFOWM_26 25 191 #define LPAIF_DMACTL_FIFOWM_27 26 192 #define LPAIF_DMACTL_FIFOWM_28 27 193 #define LPAIF_DMACTL_FIFOWM_29 28 194 #define LPAIF_DMACTL_FIFOWM_30 29 195 #define LPAIF_DMACTL_FIFOWM_31 30 196 #define LPAIF_DMACTL_FIFOWM_32 31 197 198 #define LPAIF_DMACTL_ENABLE_OFF 0 199 #define LPAIF_DMACTL_ENABLE_ON 1 200 201 #define LPAIF_DMACTL_DYNCLK_OFF 0 202 #define LPAIF_DMACTL_DYNCLK_ON 1 203 204 #endif /* __LPASS_LPAIF_REG_H__ */ 205