1 /* 2 * pxa-ssp.c -- ALSA Soc Audio Layer 3 * 4 * Copyright 2005,2008 Wolfson Microelectronics PLC. 5 * Author: Liam Girdwood 6 * Mark Brown <broonie@opensource.wolfsonmicro.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by the 10 * Free Software Foundation; either version 2 of the License, or (at your 11 * option) any later version. 12 * 13 * TODO: 14 * o Test network mode for > 16bit sample size 15 */ 16 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 23 #include <asm/irq.h> 24 25 #include <sound/core.h> 26 #include <sound/pcm.h> 27 #include <sound/initval.h> 28 #include <sound/pcm_params.h> 29 #include <sound/soc.h> 30 #include <sound/pxa2xx-lib.h> 31 32 #include <mach/hardware.h> 33 #include <mach/dma.h> 34 #include <mach/regs-ssp.h> 35 #include <mach/audio.h> 36 #include <mach/ssp.h> 37 38 #include "pxa2xx-pcm.h" 39 #include "pxa-ssp.h" 40 41 /* 42 * SSP audio private data 43 */ 44 struct ssp_priv { 45 struct ssp_dev dev; 46 unsigned int sysclk; 47 int dai_fmt; 48 #ifdef CONFIG_PM 49 struct ssp_state state; 50 #endif 51 }; 52 53 static void dump_registers(struct ssp_device *ssp) 54 { 55 dev_dbg(&ssp->pdev->dev, "SSCR0 0x%08x SSCR1 0x%08x SSTO 0x%08x\n", 56 ssp_read_reg(ssp, SSCR0), ssp_read_reg(ssp, SSCR1), 57 ssp_read_reg(ssp, SSTO)); 58 59 dev_dbg(&ssp->pdev->dev, "SSPSP 0x%08x SSSR 0x%08x SSACD 0x%08x\n", 60 ssp_read_reg(ssp, SSPSP), ssp_read_reg(ssp, SSSR), 61 ssp_read_reg(ssp, SSACD)); 62 } 63 64 struct pxa2xx_pcm_dma_data { 65 struct pxa2xx_pcm_dma_params params; 66 char name[20]; 67 }; 68 69 static struct pxa2xx_pcm_dma_params * 70 ssp_get_dma_params(struct ssp_device *ssp, int width4, int out) 71 { 72 struct pxa2xx_pcm_dma_data *dma; 73 74 dma = kzalloc(sizeof(struct pxa2xx_pcm_dma_data), GFP_KERNEL); 75 if (dma == NULL) 76 return NULL; 77 78 snprintf(dma->name, 20, "SSP%d PCM %s %s", ssp->port_id, 79 width4 ? "32-bit" : "16-bit", out ? "out" : "in"); 80 81 dma->params.name = dma->name; 82 dma->params.drcmr = &DRCMR(out ? ssp->drcmr_tx : ssp->drcmr_rx); 83 dma->params.dcmd = (out ? (DCMD_INCSRCADDR | DCMD_FLOWTRG) : 84 (DCMD_INCTRGADDR | DCMD_FLOWSRC)) | 85 (width4 ? DCMD_WIDTH4 : DCMD_WIDTH2) | DCMD_BURST16; 86 dma->params.dev_addr = ssp->phys_base + SSDR; 87 88 return &dma->params; 89 } 90 91 static int pxa_ssp_startup(struct snd_pcm_substream *substream, 92 struct snd_soc_dai *dai) 93 { 94 struct snd_soc_pcm_runtime *rtd = substream->private_data; 95 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 96 struct ssp_priv *priv = cpu_dai->private_data; 97 int ret = 0; 98 99 if (!cpu_dai->active) { 100 priv->dev.port = cpu_dai->id + 1; 101 priv->dev.irq = NO_IRQ; 102 clk_enable(priv->dev.ssp->clk); 103 ssp_disable(&priv->dev); 104 } 105 106 if (cpu_dai->dma_data) { 107 kfree(cpu_dai->dma_data); 108 cpu_dai->dma_data = NULL; 109 } 110 return ret; 111 } 112 113 static void pxa_ssp_shutdown(struct snd_pcm_substream *substream, 114 struct snd_soc_dai *dai) 115 { 116 struct snd_soc_pcm_runtime *rtd = substream->private_data; 117 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 118 struct ssp_priv *priv = cpu_dai->private_data; 119 120 if (!cpu_dai->active) { 121 ssp_disable(&priv->dev); 122 clk_disable(priv->dev.ssp->clk); 123 } 124 125 if (cpu_dai->dma_data) { 126 kfree(cpu_dai->dma_data); 127 cpu_dai->dma_data = NULL; 128 } 129 } 130 131 #ifdef CONFIG_PM 132 133 static int pxa_ssp_suspend(struct snd_soc_dai *cpu_dai) 134 { 135 struct ssp_priv *priv = cpu_dai->private_data; 136 137 if (!cpu_dai->active) 138 return 0; 139 140 ssp_save_state(&priv->dev, &priv->state); 141 clk_disable(priv->dev.ssp->clk); 142 return 0; 143 } 144 145 static int pxa_ssp_resume(struct snd_soc_dai *cpu_dai) 146 { 147 struct ssp_priv *priv = cpu_dai->private_data; 148 149 if (!cpu_dai->active) 150 return 0; 151 152 clk_enable(priv->dev.ssp->clk); 153 ssp_restore_state(&priv->dev, &priv->state); 154 ssp_enable(&priv->dev); 155 156 return 0; 157 } 158 159 #else 160 #define pxa_ssp_suspend NULL 161 #define pxa_ssp_resume NULL 162 #endif 163 164 /** 165 * ssp_set_clkdiv - set SSP clock divider 166 * @div: serial clock rate divider 167 */ 168 static void ssp_set_scr(struct ssp_device *ssp, u32 div) 169 { 170 u32 sscr0 = ssp_read_reg(ssp, SSCR0); 171 172 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) { 173 sscr0 &= ~0x0000ff00; 174 sscr0 |= ((div - 2)/2) << 8; /* 2..512 */ 175 } else { 176 sscr0 &= ~0x000fff00; 177 sscr0 |= (div - 1) << 8; /* 1..4096 */ 178 } 179 ssp_write_reg(ssp, SSCR0, sscr0); 180 } 181 182 /** 183 * ssp_get_clkdiv - get SSP clock divider 184 */ 185 static u32 ssp_get_scr(struct ssp_device *ssp) 186 { 187 u32 sscr0 = ssp_read_reg(ssp, SSCR0); 188 u32 div; 189 190 if (cpu_is_pxa25x() && ssp->type == PXA25x_SSP) 191 div = ((sscr0 >> 8) & 0xff) * 2 + 2; 192 else 193 div = ((sscr0 >> 8) & 0xfff) + 1; 194 return div; 195 } 196 197 /* 198 * Set the SSP ports SYSCLK. 199 */ 200 static int pxa_ssp_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 201 int clk_id, unsigned int freq, int dir) 202 { 203 struct ssp_priv *priv = cpu_dai->private_data; 204 struct ssp_device *ssp = priv->dev.ssp; 205 int val; 206 207 u32 sscr0 = ssp_read_reg(ssp, SSCR0) & 208 ~(SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); 209 210 dev_dbg(&ssp->pdev->dev, 211 "pxa_ssp_set_dai_sysclk id: %d, clk_id %d, freq %u\n", 212 cpu_dai->id, clk_id, freq); 213 214 switch (clk_id) { 215 case PXA_SSP_CLK_NET_PLL: 216 sscr0 |= SSCR0_MOD; 217 break; 218 case PXA_SSP_CLK_PLL: 219 /* Internal PLL is fixed */ 220 if (cpu_is_pxa25x()) 221 priv->sysclk = 1843200; 222 else 223 priv->sysclk = 13000000; 224 break; 225 case PXA_SSP_CLK_EXT: 226 priv->sysclk = freq; 227 sscr0 |= SSCR0_ECS; 228 break; 229 case PXA_SSP_CLK_NET: 230 priv->sysclk = freq; 231 sscr0 |= SSCR0_NCS | SSCR0_MOD; 232 break; 233 case PXA_SSP_CLK_AUDIO: 234 priv->sysclk = 0; 235 ssp_set_scr(ssp, 1); 236 sscr0 |= SSCR0_ACS; 237 break; 238 default: 239 return -ENODEV; 240 } 241 242 /* The SSP clock must be disabled when changing SSP clock mode 243 * on PXA2xx. On PXA3xx it must be enabled when doing so. */ 244 if (!cpu_is_pxa3xx()) 245 clk_disable(priv->dev.ssp->clk); 246 val = ssp_read_reg(ssp, SSCR0) | sscr0; 247 ssp_write_reg(ssp, SSCR0, val); 248 if (!cpu_is_pxa3xx()) 249 clk_enable(priv->dev.ssp->clk); 250 251 return 0; 252 } 253 254 /* 255 * Set the SSP clock dividers. 256 */ 257 static int pxa_ssp_set_dai_clkdiv(struct snd_soc_dai *cpu_dai, 258 int div_id, int div) 259 { 260 struct ssp_priv *priv = cpu_dai->private_data; 261 struct ssp_device *ssp = priv->dev.ssp; 262 int val; 263 264 switch (div_id) { 265 case PXA_SSP_AUDIO_DIV_ACDS: 266 val = (ssp_read_reg(ssp, SSACD) & ~0x7) | SSACD_ACDS(div); 267 ssp_write_reg(ssp, SSACD, val); 268 break; 269 case PXA_SSP_AUDIO_DIV_SCDB: 270 val = ssp_read_reg(ssp, SSACD); 271 val &= ~SSACD_SCDB; 272 #if defined(CONFIG_PXA3xx) 273 if (cpu_is_pxa3xx()) 274 val &= ~SSACD_SCDX8; 275 #endif 276 switch (div) { 277 case PXA_SSP_CLK_SCDB_1: 278 val |= SSACD_SCDB; 279 break; 280 case PXA_SSP_CLK_SCDB_4: 281 break; 282 #if defined(CONFIG_PXA3xx) 283 case PXA_SSP_CLK_SCDB_8: 284 if (cpu_is_pxa3xx()) 285 val |= SSACD_SCDX8; 286 else 287 return -EINVAL; 288 break; 289 #endif 290 default: 291 return -EINVAL; 292 } 293 ssp_write_reg(ssp, SSACD, val); 294 break; 295 case PXA_SSP_DIV_SCR: 296 ssp_set_scr(ssp, div); 297 break; 298 default: 299 return -ENODEV; 300 } 301 302 return 0; 303 } 304 305 /* 306 * Configure the PLL frequency pxa27x and (afaik - pxa320 only) 307 */ 308 static int pxa_ssp_set_dai_pll(struct snd_soc_dai *cpu_dai, 309 int pll_id, unsigned int freq_in, unsigned int freq_out) 310 { 311 struct ssp_priv *priv = cpu_dai->private_data; 312 struct ssp_device *ssp = priv->dev.ssp; 313 u32 ssacd = ssp_read_reg(ssp, SSACD) & ~0x70; 314 315 #if defined(CONFIG_PXA3xx) 316 if (cpu_is_pxa3xx()) 317 ssp_write_reg(ssp, SSACDD, 0); 318 #endif 319 320 switch (freq_out) { 321 case 5622000: 322 break; 323 case 11345000: 324 ssacd |= (0x1 << 4); 325 break; 326 case 12235000: 327 ssacd |= (0x2 << 4); 328 break; 329 case 14857000: 330 ssacd |= (0x3 << 4); 331 break; 332 case 32842000: 333 ssacd |= (0x4 << 4); 334 break; 335 case 48000000: 336 ssacd |= (0x5 << 4); 337 break; 338 case 0: 339 /* Disable */ 340 break; 341 342 default: 343 #ifdef CONFIG_PXA3xx 344 /* PXA3xx has a clock ditherer which can be used to generate 345 * a wider range of frequencies - calculate a value for it. 346 */ 347 if (cpu_is_pxa3xx()) { 348 u32 val; 349 u64 tmp = 19968; 350 tmp *= 1000000; 351 do_div(tmp, freq_out); 352 val = tmp; 353 354 val = (val << 16) | 64; 355 ssp_write_reg(ssp, SSACDD, val); 356 357 ssacd |= (0x6 << 4); 358 359 dev_dbg(&ssp->pdev->dev, 360 "Using SSACDD %x to supply %uHz\n", 361 val, freq_out); 362 break; 363 } 364 #endif 365 366 return -EINVAL; 367 } 368 369 ssp_write_reg(ssp, SSACD, ssacd); 370 371 return 0; 372 } 373 374 /* 375 * Set the active slots in TDM/Network mode 376 */ 377 static int pxa_ssp_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, 378 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width) 379 { 380 struct ssp_priv *priv = cpu_dai->private_data; 381 struct ssp_device *ssp = priv->dev.ssp; 382 u32 sscr0; 383 384 sscr0 = ssp_read_reg(ssp, SSCR0); 385 sscr0 &= ~(SSCR0_MOD | SSCR0_SlotsPerFrm(8) | SSCR0_EDSS | SSCR0_DSS); 386 387 /* set slot width */ 388 if (slot_width > 16) 389 sscr0 |= SSCR0_EDSS | SSCR0_DataSize(slot_width - 16); 390 else 391 sscr0 |= SSCR0_DataSize(slot_width); 392 393 if (slots > 1) { 394 /* enable network mode */ 395 sscr0 |= SSCR0_MOD; 396 397 /* set number of active slots */ 398 sscr0 |= SSCR0_SlotsPerFrm(slots); 399 400 /* set active slot mask */ 401 ssp_write_reg(ssp, SSTSA, tx_mask); 402 ssp_write_reg(ssp, SSRSA, rx_mask); 403 } 404 ssp_write_reg(ssp, SSCR0, sscr0); 405 406 return 0; 407 } 408 409 /* 410 * Tristate the SSP DAI lines 411 */ 412 static int pxa_ssp_set_dai_tristate(struct snd_soc_dai *cpu_dai, 413 int tristate) 414 { 415 struct ssp_priv *priv = cpu_dai->private_data; 416 struct ssp_device *ssp = priv->dev.ssp; 417 u32 sscr1; 418 419 sscr1 = ssp_read_reg(ssp, SSCR1); 420 if (tristate) 421 sscr1 &= ~SSCR1_TTE; 422 else 423 sscr1 |= SSCR1_TTE; 424 ssp_write_reg(ssp, SSCR1, sscr1); 425 426 return 0; 427 } 428 429 /* 430 * Set up the SSP DAI format. 431 * The SSP Port must be inactive before calling this function as the 432 * physical interface format is changed. 433 */ 434 static int pxa_ssp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 435 unsigned int fmt) 436 { 437 struct ssp_priv *priv = cpu_dai->private_data; 438 struct ssp_device *ssp = priv->dev.ssp; 439 u32 sscr0; 440 u32 sscr1; 441 u32 sspsp; 442 443 /* check if we need to change anything at all */ 444 if (priv->dai_fmt == fmt) 445 return 0; 446 447 /* we can only change the settings if the port is not in use */ 448 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) { 449 dev_err(&ssp->pdev->dev, 450 "can't change hardware dai format: stream is in use"); 451 return -EINVAL; 452 } 453 454 /* reset port settings */ 455 sscr0 = ssp_read_reg(ssp, SSCR0) & 456 (SSCR0_ECS | SSCR0_NCS | SSCR0_MOD | SSCR0_ACS); 457 sscr1 = SSCR1_RxTresh(8) | SSCR1_TxTresh(7); 458 sspsp = 0; 459 460 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 461 case SND_SOC_DAIFMT_CBM_CFM: 462 sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR; 463 break; 464 case SND_SOC_DAIFMT_CBM_CFS: 465 sscr1 |= SSCR1_SCLKDIR; 466 break; 467 case SND_SOC_DAIFMT_CBS_CFS: 468 break; 469 default: 470 return -EINVAL; 471 } 472 473 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 474 case SND_SOC_DAIFMT_NB_NF: 475 sspsp |= SSPSP_SFRMP; 476 break; 477 case SND_SOC_DAIFMT_NB_IF: 478 break; 479 case SND_SOC_DAIFMT_IB_IF: 480 sspsp |= SSPSP_SCMODE(2); 481 break; 482 case SND_SOC_DAIFMT_IB_NF: 483 sspsp |= SSPSP_SCMODE(2) | SSPSP_SFRMP; 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 490 case SND_SOC_DAIFMT_I2S: 491 sscr0 |= SSCR0_PSP; 492 sscr1 |= SSCR1_RWOT | SSCR1_TRAIL; 493 /* See hw_params() */ 494 break; 495 496 case SND_SOC_DAIFMT_DSP_A: 497 sspsp |= SSPSP_FSRT; 498 case SND_SOC_DAIFMT_DSP_B: 499 sscr0 |= SSCR0_MOD | SSCR0_PSP; 500 sscr1 |= SSCR1_TRAIL | SSCR1_RWOT; 501 break; 502 503 default: 504 return -EINVAL; 505 } 506 507 ssp_write_reg(ssp, SSCR0, sscr0); 508 ssp_write_reg(ssp, SSCR1, sscr1); 509 ssp_write_reg(ssp, SSPSP, sspsp); 510 511 dump_registers(ssp); 512 513 /* Since we are configuring the timings for the format by hand 514 * we have to defer some things until hw_params() where we 515 * know parameters like the sample size. 516 */ 517 priv->dai_fmt = fmt; 518 519 return 0; 520 } 521 522 /* 523 * Set the SSP audio DMA parameters and sample size. 524 * Can be called multiple times by oss emulation. 525 */ 526 static int pxa_ssp_hw_params(struct snd_pcm_substream *substream, 527 struct snd_pcm_hw_params *params, 528 struct snd_soc_dai *dai) 529 { 530 struct snd_soc_pcm_runtime *rtd = substream->private_data; 531 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 532 struct ssp_priv *priv = cpu_dai->private_data; 533 struct ssp_device *ssp = priv->dev.ssp; 534 int chn = params_channels(params); 535 u32 sscr0; 536 u32 sspsp; 537 int width = snd_pcm_format_physical_width(params_format(params)); 538 int ttsa = ssp_read_reg(ssp, SSTSA) & 0xf; 539 540 /* generate correct DMA params */ 541 if (cpu_dai->dma_data) 542 kfree(cpu_dai->dma_data); 543 544 /* Network mode with one active slot (ttsa == 1) can be used 545 * to force 16-bit frame width on the wire (for S16_LE), even 546 * with two channels. Use 16-bit DMA transfers for this case. 547 */ 548 cpu_dai->dma_data = ssp_get_dma_params(ssp, 549 ((chn == 2) && (ttsa != 1)) || (width == 32), 550 substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 551 552 /* we can only change the settings if the port is not in use */ 553 if (ssp_read_reg(ssp, SSCR0) & SSCR0_SSE) 554 return 0; 555 556 /* clear selected SSP bits */ 557 sscr0 = ssp_read_reg(ssp, SSCR0) & ~(SSCR0_DSS | SSCR0_EDSS); 558 ssp_write_reg(ssp, SSCR0, sscr0); 559 560 /* bit size */ 561 sscr0 = ssp_read_reg(ssp, SSCR0); 562 switch (params_format(params)) { 563 case SNDRV_PCM_FORMAT_S16_LE: 564 #ifdef CONFIG_PXA3xx 565 if (cpu_is_pxa3xx()) 566 sscr0 |= SSCR0_FPCKE; 567 #endif 568 sscr0 |= SSCR0_DataSize(16); 569 break; 570 case SNDRV_PCM_FORMAT_S24_LE: 571 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(8)); 572 break; 573 case SNDRV_PCM_FORMAT_S32_LE: 574 sscr0 |= (SSCR0_EDSS | SSCR0_DataSize(16)); 575 break; 576 } 577 ssp_write_reg(ssp, SSCR0, sscr0); 578 579 switch (priv->dai_fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 580 case SND_SOC_DAIFMT_I2S: 581 sspsp = ssp_read_reg(ssp, SSPSP); 582 583 if ((ssp_get_scr(ssp) == 4) && (width == 16)) { 584 /* This is a special case where the bitclk is 64fs 585 * and we're not dealing with 2*32 bits of audio 586 * samples. 587 * 588 * The SSP values used for that are all found out by 589 * trying and failing a lot; some of the registers 590 * needed for that mode are only available on PXA3xx. 591 */ 592 593 #ifdef CONFIG_PXA3xx 594 if (!cpu_is_pxa3xx()) 595 return -EINVAL; 596 597 sspsp |= SSPSP_SFRMWDTH(width * 2); 598 sspsp |= SSPSP_SFRMDLY(width * 4); 599 sspsp |= SSPSP_EDMYSTOP(3); 600 sspsp |= SSPSP_DMYSTOP(3); 601 sspsp |= SSPSP_DMYSTRT(1); 602 #else 603 return -EINVAL; 604 #endif 605 } else { 606 /* The frame width is the width the LRCLK is 607 * asserted for; the delay is expressed in 608 * half cycle units. We need the extra cycle 609 * because the data starts clocking out one BCLK 610 * after LRCLK changes polarity. 611 */ 612 sspsp |= SSPSP_SFRMWDTH(width + 1); 613 sspsp |= SSPSP_SFRMDLY((width + 1) * 2); 614 sspsp |= SSPSP_DMYSTRT(1); 615 } 616 617 ssp_write_reg(ssp, SSPSP, sspsp); 618 break; 619 default: 620 break; 621 } 622 623 /* When we use a network mode, we always require TDM slots 624 * - complain loudly and fail if they've not been set up yet. 625 */ 626 if ((sscr0 & SSCR0_MOD) && !ttsa) { 627 dev_err(&ssp->pdev->dev, "No TDM timeslot configured\n"); 628 return -EINVAL; 629 } 630 631 dump_registers(ssp); 632 633 return 0; 634 } 635 636 static int pxa_ssp_trigger(struct snd_pcm_substream *substream, int cmd, 637 struct snd_soc_dai *dai) 638 { 639 struct snd_soc_pcm_runtime *rtd = substream->private_data; 640 struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; 641 int ret = 0; 642 struct ssp_priv *priv = cpu_dai->private_data; 643 struct ssp_device *ssp = priv->dev.ssp; 644 int val; 645 646 switch (cmd) { 647 case SNDRV_PCM_TRIGGER_RESUME: 648 ssp_enable(&priv->dev); 649 break; 650 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 651 val = ssp_read_reg(ssp, SSCR1); 652 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 653 val |= SSCR1_TSRE; 654 else 655 val |= SSCR1_RSRE; 656 ssp_write_reg(ssp, SSCR1, val); 657 val = ssp_read_reg(ssp, SSSR); 658 ssp_write_reg(ssp, SSSR, val); 659 break; 660 case SNDRV_PCM_TRIGGER_START: 661 val = ssp_read_reg(ssp, SSCR1); 662 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 663 val |= SSCR1_TSRE; 664 else 665 val |= SSCR1_RSRE; 666 ssp_write_reg(ssp, SSCR1, val); 667 ssp_enable(&priv->dev); 668 break; 669 case SNDRV_PCM_TRIGGER_STOP: 670 val = ssp_read_reg(ssp, SSCR1); 671 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 672 val &= ~SSCR1_TSRE; 673 else 674 val &= ~SSCR1_RSRE; 675 ssp_write_reg(ssp, SSCR1, val); 676 break; 677 case SNDRV_PCM_TRIGGER_SUSPEND: 678 ssp_disable(&priv->dev); 679 break; 680 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 681 val = ssp_read_reg(ssp, SSCR1); 682 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 683 val &= ~SSCR1_TSRE; 684 else 685 val &= ~SSCR1_RSRE; 686 ssp_write_reg(ssp, SSCR1, val); 687 break; 688 689 default: 690 ret = -EINVAL; 691 } 692 693 dump_registers(ssp); 694 695 return ret; 696 } 697 698 static int pxa_ssp_probe(struct platform_device *pdev, 699 struct snd_soc_dai *dai) 700 { 701 struct ssp_priv *priv; 702 int ret; 703 704 priv = kzalloc(sizeof(struct ssp_priv), GFP_KERNEL); 705 if (!priv) 706 return -ENOMEM; 707 708 priv->dev.ssp = ssp_request(dai->id + 1, "SoC audio"); 709 if (priv->dev.ssp == NULL) { 710 ret = -ENODEV; 711 goto err_priv; 712 } 713 714 priv->dai_fmt = (unsigned int) -1; 715 dai->private_data = priv; 716 717 return 0; 718 719 err_priv: 720 kfree(priv); 721 return ret; 722 } 723 724 static void pxa_ssp_remove(struct platform_device *pdev, 725 struct snd_soc_dai *dai) 726 { 727 struct ssp_priv *priv = dai->private_data; 728 ssp_free(priv->dev.ssp); 729 } 730 731 #define PXA_SSP_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\ 732 SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \ 733 SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 | \ 734 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000) 735 736 #define PXA_SSP_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 737 SNDRV_PCM_FMTBIT_S24_LE | \ 738 SNDRV_PCM_FMTBIT_S32_LE) 739 740 static struct snd_soc_dai_ops pxa_ssp_dai_ops = { 741 .startup = pxa_ssp_startup, 742 .shutdown = pxa_ssp_shutdown, 743 .trigger = pxa_ssp_trigger, 744 .hw_params = pxa_ssp_hw_params, 745 .set_sysclk = pxa_ssp_set_dai_sysclk, 746 .set_clkdiv = pxa_ssp_set_dai_clkdiv, 747 .set_pll = pxa_ssp_set_dai_pll, 748 .set_fmt = pxa_ssp_set_dai_fmt, 749 .set_tdm_slot = pxa_ssp_set_dai_tdm_slot, 750 .set_tristate = pxa_ssp_set_dai_tristate, 751 }; 752 753 struct snd_soc_dai pxa_ssp_dai[] = { 754 { 755 .name = "pxa2xx-ssp1", 756 .id = 0, 757 .probe = pxa_ssp_probe, 758 .remove = pxa_ssp_remove, 759 .suspend = pxa_ssp_suspend, 760 .resume = pxa_ssp_resume, 761 .playback = { 762 .channels_min = 1, 763 .channels_max = 2, 764 .rates = PXA_SSP_RATES, 765 .formats = PXA_SSP_FORMATS, 766 }, 767 .capture = { 768 .channels_min = 1, 769 .channels_max = 2, 770 .rates = PXA_SSP_RATES, 771 .formats = PXA_SSP_FORMATS, 772 }, 773 .ops = &pxa_ssp_dai_ops, 774 }, 775 { .name = "pxa2xx-ssp2", 776 .id = 1, 777 .probe = pxa_ssp_probe, 778 .remove = pxa_ssp_remove, 779 .suspend = pxa_ssp_suspend, 780 .resume = pxa_ssp_resume, 781 .playback = { 782 .channels_min = 1, 783 .channels_max = 2, 784 .rates = PXA_SSP_RATES, 785 .formats = PXA_SSP_FORMATS, 786 }, 787 .capture = { 788 .channels_min = 1, 789 .channels_max = 2, 790 .rates = PXA_SSP_RATES, 791 .formats = PXA_SSP_FORMATS, 792 }, 793 .ops = &pxa_ssp_dai_ops, 794 }, 795 { 796 .name = "pxa2xx-ssp3", 797 .id = 2, 798 .probe = pxa_ssp_probe, 799 .remove = pxa_ssp_remove, 800 .suspend = pxa_ssp_suspend, 801 .resume = pxa_ssp_resume, 802 .playback = { 803 .channels_min = 1, 804 .channels_max = 2, 805 .rates = PXA_SSP_RATES, 806 .formats = PXA_SSP_FORMATS, 807 }, 808 .capture = { 809 .channels_min = 1, 810 .channels_max = 2, 811 .rates = PXA_SSP_RATES, 812 .formats = PXA_SSP_FORMATS, 813 }, 814 .ops = &pxa_ssp_dai_ops, 815 }, 816 { 817 .name = "pxa2xx-ssp4", 818 .id = 3, 819 .probe = pxa_ssp_probe, 820 .remove = pxa_ssp_remove, 821 .suspend = pxa_ssp_suspend, 822 .resume = pxa_ssp_resume, 823 .playback = { 824 .channels_min = 1, 825 .channels_max = 2, 826 .rates = PXA_SSP_RATES, 827 .formats = PXA_SSP_FORMATS, 828 }, 829 .capture = { 830 .channels_min = 1, 831 .channels_max = 2, 832 .rates = PXA_SSP_RATES, 833 .formats = PXA_SSP_FORMATS, 834 }, 835 .ops = &pxa_ssp_dai_ops, 836 }, 837 }; 838 EXPORT_SYMBOL_GPL(pxa_ssp_dai); 839 840 static int __init pxa_ssp_init(void) 841 { 842 return snd_soc_register_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai)); 843 } 844 module_init(pxa_ssp_init); 845 846 static void __exit pxa_ssp_exit(void) 847 { 848 snd_soc_unregister_dais(pxa_ssp_dai, ARRAY_SIZE(pxa_ssp_dai)); 849 } 850 module_exit(pxa_ssp_exit); 851 852 /* Module information */ 853 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>"); 854 MODULE_DESCRIPTION("PXA SSP/PCM SoC Interface"); 855 MODULE_LICENSE("GPL"); 856