1 /* 2 * linux/sound/soc/pxa/mmp-sspa.h 3 * 4 * Copyright (C) 2011 Marvell International Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 */ 21 #ifndef _MMP_SSPA_H 22 #define _MMP_SSPA_H 23 24 /* 25 * SSPA Registers 26 */ 27 #define SSPA_RXD (0x00) 28 #define SSPA_RXID (0x04) 29 #define SSPA_RXCTL (0x08) 30 #define SSPA_RXSP (0x0c) 31 #define SSPA_RXFIFO_UL (0x10) 32 #define SSPA_RXINT_MASK (0x14) 33 #define SSPA_RXC (0x18) 34 #define SSPA_RXFIFO_NOFS (0x1c) 35 #define SSPA_RXFIFO_SIZE (0x20) 36 37 #define SSPA_TXD (0x80) 38 #define SSPA_TXID (0x84) 39 #define SSPA_TXCTL (0x88) 40 #define SSPA_TXSP (0x8c) 41 #define SSPA_TXFIFO_LL (0x90) 42 #define SSPA_TXINT_MASK (0x94) 43 #define SSPA_TXC (0x98) 44 #define SSPA_TXFIFO_NOFS (0x9c) 45 #define SSPA_TXFIFO_SIZE (0xa0) 46 47 /* SSPA Control Register */ 48 #define SSPA_CTL_XPH (1 << 31) /* Read Phase */ 49 #define SSPA_CTL_XFIG (1 << 15) /* Transmit Zeros when FIFO Empty */ 50 #define SSPA_CTL_JST (1 << 3) /* Audio Sample Justification */ 51 #define SSPA_CTL_XFRLEN2_MASK (7 << 24) 52 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ 53 #define SSPA_CTL_XWDLEN2_MASK (7 << 21) 54 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ 55 #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Tansmit Data Delay */ 56 #define SSPA_CTL_XSSZ2_MASK (7 << 16) 57 #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ 58 #define SSPA_CTL_XFRLEN1_MASK (7 << 8) 59 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ 60 #define SSPA_CTL_XWDLEN1_MASK (7 << 5) 61 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ 62 #define SSPA_CTL_XSSZ1_MASK (7 << 0) 63 #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ 64 65 #define SSPA_CTL_8_BITS (0x0) /* Sample Size */ 66 #define SSPA_CTL_12_BITS (0x1) 67 #define SSPA_CTL_16_BITS (0x2) 68 #define SSPA_CTL_20_BITS (0x3) 69 #define SSPA_CTL_24_BITS (0x4) 70 #define SSPA_CTL_32_BITS (0x5) 71 72 /* SSPA Serial Port Register */ 73 #define SSPA_SP_WEN (1 << 31) /* Write Configuration Enable */ 74 #define SSPA_SP_MSL (1 << 18) /* Master Slave Configuration */ 75 #define SSPA_SP_CLKP (1 << 17) /* CLKP Polarity Clock Edge Select */ 76 #define SSPA_SP_FSP (1 << 16) /* FSP Polarity Clock Edge Select */ 77 #define SSPA_SP_FFLUSH (1 << 2) /* FIFO Flush */ 78 #define SSPA_SP_S_RST (1 << 1) /* Active High Reset Signal */ 79 #define SSPA_SP_S_EN (1 << 0) /* Serial Clock Domain Enable */ 80 #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ 81 #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ 82 83 /* sspa clock sources */ 84 #define MMP_SSPA_CLK_PLL 0 85 #define MMP_SSPA_CLK_VCXO 1 86 #define MMP_SSPA_CLK_AUDIO 3 87 88 /* sspa pll id */ 89 #define MMP_SYSCLK 0 90 #define MMP_SSPA_CLK 1 91 92 #endif /* _MMP_SSPA_H */ 93