1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/clk-provider.h> 28 #include <linux/delay.h> 29 #include <linux/time.h> 30 #include <sound/core.h> 31 #include <sound/pcm.h> 32 #include <sound/pcm_params.h> 33 #include <sound/soc.h> 34 35 #include "mxs-saif.h" 36 37 #define MXS_SET_ADDR 0x4 38 #define MXS_CLR_ADDR 0x8 39 40 static struct mxs_saif *mxs_saif[2]; 41 42 /* 43 * SAIF is a little different with other normal SOC DAIs on clock using. 44 * 45 * For MXS, two SAIF modules are instantiated on-chip. 46 * Each SAIF has a set of clock pins and can be operating in master 47 * mode simultaneously if they are connected to different off-chip codecs. 48 * Also, one of the two SAIFs can master or drive the clock pins while the 49 * other SAIF, in slave mode, receives clocking from the master SAIF. 50 * This also means that both SAIFs must operate at the same sample rate. 51 * 52 * We abstract this as each saif has a master, the master could be 53 * itself or other saifs. In the generic saif driver, saif does not need 54 * to know the different clkmux. Saif only needs to know who is its master 55 * and operating its master to generate the proper clock rate for it. 56 * The master id is provided in mach-specific layer according to different 57 * clkmux setting. 58 */ 59 60 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 61 int clk_id, unsigned int freq, int dir) 62 { 63 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 64 65 switch (clk_id) { 66 case MXS_SAIF_MCLK: 67 saif->mclk = freq; 68 break; 69 default: 70 return -EINVAL; 71 } 72 return 0; 73 } 74 75 /* 76 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 77 * is provided by other SAIF, we provide a interface here to get its master 78 * from its master_id. 79 * Note that the master could be itself. 80 */ 81 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 82 { 83 return mxs_saif[saif->master_id]; 84 } 85 86 /* 87 * Set SAIF clock and MCLK 88 */ 89 static int mxs_saif_set_clk(struct mxs_saif *saif, 90 unsigned int mclk, 91 unsigned int rate) 92 { 93 u32 scr; 94 int ret; 95 struct mxs_saif *master_saif; 96 97 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 98 99 /* Set master saif to generate proper clock */ 100 master_saif = mxs_saif_get_master(saif); 101 if (!master_saif) 102 return -EINVAL; 103 104 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 105 106 /* Checking if can playback and capture simutaneously */ 107 if (master_saif->ongoing && rate != master_saif->cur_rate) { 108 dev_err(saif->dev, 109 "can not change clock, master saif%d(rate %d) is ongoing\n", 110 master_saif->id, master_saif->cur_rate); 111 return -EINVAL; 112 } 113 114 scr = __raw_readl(master_saif->base + SAIF_CTRL); 115 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 116 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 117 118 /* 119 * Set SAIF clock 120 * 121 * The SAIF clock should be either 384*fs or 512*fs. 122 * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 123 * For 32x mclk, set saif clk as 512*fs. 124 * For 48x mclk, set saif clk as 384*fs. 125 * 126 * If MCLK is not used, we just set saif clk to 512*fs. 127 */ 128 clk_prepare_enable(master_saif->clk); 129 130 if (master_saif->mclk_in_use) { 131 if (mclk % 32 == 0) { 132 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 133 ret = clk_set_rate(master_saif->clk, 512 * rate); 134 } else if (mclk % 48 == 0) { 135 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 136 ret = clk_set_rate(master_saif->clk, 384 * rate); 137 } else { 138 /* SAIF MCLK should be either 32x or 48x */ 139 clk_disable_unprepare(master_saif->clk); 140 return -EINVAL; 141 } 142 } else { 143 ret = clk_set_rate(master_saif->clk, 512 * rate); 144 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 145 } 146 147 clk_disable_unprepare(master_saif->clk); 148 149 if (ret) 150 return ret; 151 152 master_saif->cur_rate = rate; 153 154 if (!master_saif->mclk_in_use) { 155 __raw_writel(scr, master_saif->base + SAIF_CTRL); 156 return 0; 157 } 158 159 /* 160 * Program the over-sample rate for MCLK output 161 * 162 * The available MCLK range is 32x, 48x... 512x. The rate 163 * could be from 8kHz to 192kH. 164 */ 165 switch (mclk / rate) { 166 case 32: 167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 168 break; 169 case 64: 170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 171 break; 172 case 128: 173 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 174 break; 175 case 256: 176 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 177 break; 178 case 512: 179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 180 break; 181 case 48: 182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 183 break; 184 case 96: 185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 186 break; 187 case 192: 188 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 189 break; 190 case 384: 191 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 __raw_writel(scr, master_saif->base + SAIF_CTRL); 198 199 return 0; 200 } 201 202 /* 203 * Put and disable MCLK. 204 */ 205 int mxs_saif_put_mclk(unsigned int saif_id) 206 { 207 struct mxs_saif *saif = mxs_saif[saif_id]; 208 u32 stat; 209 210 if (!saif) 211 return -EINVAL; 212 213 stat = __raw_readl(saif->base + SAIF_STAT); 214 if (stat & BM_SAIF_STAT_BUSY) { 215 dev_err(saif->dev, "error: busy\n"); 216 return -EBUSY; 217 } 218 219 clk_disable_unprepare(saif->clk); 220 221 /* disable MCLK output */ 222 __raw_writel(BM_SAIF_CTRL_CLKGATE, 223 saif->base + SAIF_CTRL + MXS_SET_ADDR); 224 __raw_writel(BM_SAIF_CTRL_RUN, 225 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 226 227 saif->mclk_in_use = 0; 228 return 0; 229 } 230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 231 232 /* 233 * Get MCLK and set clock rate, then enable it 234 * 235 * This interface is used for codecs who are using MCLK provided 236 * by saif. 237 */ 238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 239 unsigned int rate) 240 { 241 struct mxs_saif *saif = mxs_saif[saif_id]; 242 u32 stat; 243 int ret; 244 struct mxs_saif *master_saif; 245 246 if (!saif) 247 return -EINVAL; 248 249 /* Clear Reset */ 250 __raw_writel(BM_SAIF_CTRL_SFTRST, 251 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 252 253 /* FIXME: need clear clk gate for register r/w */ 254 __raw_writel(BM_SAIF_CTRL_CLKGATE, 255 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 256 257 master_saif = mxs_saif_get_master(saif); 258 if (saif != master_saif) { 259 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 260 return -EINVAL; 261 } 262 263 stat = __raw_readl(saif->base + SAIF_STAT); 264 if (stat & BM_SAIF_STAT_BUSY) { 265 dev_err(saif->dev, "error: busy\n"); 266 return -EBUSY; 267 } 268 269 saif->mclk_in_use = 1; 270 ret = mxs_saif_set_clk(saif, mclk, rate); 271 if (ret) 272 return ret; 273 274 ret = clk_prepare_enable(saif->clk); 275 if (ret) 276 return ret; 277 278 /* enable MCLK output */ 279 __raw_writel(BM_SAIF_CTRL_RUN, 280 saif->base + SAIF_CTRL + MXS_SET_ADDR); 281 282 return 0; 283 } 284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 285 286 /* 287 * SAIF DAI format configuration. 288 * Should only be called when port is inactive. 289 */ 290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 291 { 292 u32 scr, stat; 293 u32 scr0; 294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 295 296 stat = __raw_readl(saif->base + SAIF_STAT); 297 if (stat & BM_SAIF_STAT_BUSY) { 298 dev_err(cpu_dai->dev, "error: busy\n"); 299 return -EBUSY; 300 } 301 302 scr0 = __raw_readl(saif->base + SAIF_CTRL); 303 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 304 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 305 scr = 0; 306 307 /* DAI mode */ 308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 309 case SND_SOC_DAIFMT_I2S: 310 /* data frame low 1clk before data */ 311 scr |= BM_SAIF_CTRL_DELAY; 312 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 313 break; 314 case SND_SOC_DAIFMT_LEFT_J: 315 /* data frame high with data */ 316 scr &= ~BM_SAIF_CTRL_DELAY; 317 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 318 scr &= ~BM_SAIF_CTRL_JUSTIFY; 319 break; 320 default: 321 return -EINVAL; 322 } 323 324 /* DAI clock inversion */ 325 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 326 case SND_SOC_DAIFMT_IB_IF: 327 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 328 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 329 break; 330 case SND_SOC_DAIFMT_IB_NF: 331 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 333 break; 334 case SND_SOC_DAIFMT_NB_IF: 335 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 336 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 337 break; 338 case SND_SOC_DAIFMT_NB_NF: 339 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 340 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 341 break; 342 } 343 344 /* 345 * Note: We simply just support master mode since SAIF TX can only 346 * work as master. 347 * Here the master is relative to codec side. 348 * Saif internally could be slave when working on EXTMASTER mode. 349 * We just hide this to machine driver. 350 */ 351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 352 case SND_SOC_DAIFMT_CBS_CFS: 353 if (saif->id == saif->master_id) 354 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 355 else 356 scr |= BM_SAIF_CTRL_SLAVE_MODE; 357 358 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 359 break; 360 default: 361 return -EINVAL; 362 } 363 364 return 0; 365 } 366 367 static int mxs_saif_startup(struct snd_pcm_substream *substream, 368 struct snd_soc_dai *cpu_dai) 369 { 370 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 371 372 /* clear error status to 0 for each re-open */ 373 saif->fifo_underrun = 0; 374 saif->fifo_overrun = 0; 375 376 /* Clear Reset for normal operations */ 377 __raw_writel(BM_SAIF_CTRL_SFTRST, 378 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 379 380 /* clear clock gate */ 381 __raw_writel(BM_SAIF_CTRL_CLKGATE, 382 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 383 384 return 0; 385 } 386 387 /* 388 * Should only be called when port is inactive. 389 * although can be called multiple times by upper layers. 390 */ 391 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 392 struct snd_pcm_hw_params *params, 393 struct snd_soc_dai *cpu_dai) 394 { 395 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 396 struct mxs_saif *master_saif; 397 u32 scr, stat; 398 int ret; 399 400 master_saif = mxs_saif_get_master(saif); 401 if (!master_saif) 402 return -EINVAL; 403 404 /* mclk should already be set */ 405 if (!saif->mclk && saif->mclk_in_use) { 406 dev_err(cpu_dai->dev, "set mclk first\n"); 407 return -EINVAL; 408 } 409 410 stat = __raw_readl(saif->base + SAIF_STAT); 411 if (stat & BM_SAIF_STAT_BUSY) { 412 dev_err(cpu_dai->dev, "error: busy\n"); 413 return -EBUSY; 414 } 415 416 /* 417 * Set saif clk based on sample rate. 418 * If mclk is used, we also set mclk, if not, saif->mclk is 419 * default 0, means not used. 420 */ 421 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 422 if (ret) { 423 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 424 return ret; 425 } 426 427 /* prepare clk in hw_param, enable in trigger */ 428 clk_prepare(saif->clk); 429 if (saif != master_saif) { 430 /* 431 * Set an initial clock rate for the saif internal logic to work 432 * properly. This is important when working in EXTMASTER mode 433 * that uses the other saif's BITCLK&LRCLK but it still needs a 434 * basic clock which should be fast enough for the internal 435 * logic. 436 */ 437 clk_enable(saif->clk); 438 ret = clk_set_rate(saif->clk, 24000000); 439 clk_disable(saif->clk); 440 if (ret) 441 return ret; 442 443 clk_prepare(master_saif->clk); 444 } 445 446 scr = __raw_readl(saif->base + SAIF_CTRL); 447 448 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 449 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 450 switch (params_format(params)) { 451 case SNDRV_PCM_FORMAT_S16_LE: 452 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 453 break; 454 case SNDRV_PCM_FORMAT_S20_3LE: 455 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 456 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 457 break; 458 case SNDRV_PCM_FORMAT_S24_LE: 459 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 460 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 461 break; 462 default: 463 return -EINVAL; 464 } 465 466 /* Tx/Rx config */ 467 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 468 /* enable TX mode */ 469 scr &= ~BM_SAIF_CTRL_READ_MODE; 470 } else { 471 /* enable RX mode */ 472 scr |= BM_SAIF_CTRL_READ_MODE; 473 } 474 475 __raw_writel(scr, saif->base + SAIF_CTRL); 476 return 0; 477 } 478 479 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 480 struct snd_soc_dai *cpu_dai) 481 { 482 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 483 484 /* enable FIFO error irqs */ 485 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 486 saif->base + SAIF_CTRL + MXS_SET_ADDR); 487 488 return 0; 489 } 490 491 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 492 struct snd_soc_dai *cpu_dai) 493 { 494 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 495 struct mxs_saif *master_saif; 496 u32 delay; 497 int ret; 498 499 master_saif = mxs_saif_get_master(saif); 500 if (!master_saif) 501 return -EINVAL; 502 503 switch (cmd) { 504 case SNDRV_PCM_TRIGGER_START: 505 case SNDRV_PCM_TRIGGER_RESUME: 506 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 507 if (saif->state == MXS_SAIF_STATE_RUNNING) 508 return 0; 509 510 dev_dbg(cpu_dai->dev, "start\n"); 511 512 ret = clk_enable(master_saif->clk); 513 if (ret) { 514 dev_err(saif->dev, "Failed to enable master clock\n"); 515 return ret; 516 } 517 518 /* 519 * If the saif's master is not itself, we also need to enable 520 * itself clk for its internal basic logic to work. 521 */ 522 if (saif != master_saif) { 523 ret = clk_enable(saif->clk); 524 if (ret) { 525 dev_err(saif->dev, "Failed to enable master clock\n"); 526 clk_disable(master_saif->clk); 527 return ret; 528 } 529 530 __raw_writel(BM_SAIF_CTRL_RUN, 531 saif->base + SAIF_CTRL + MXS_SET_ADDR); 532 } 533 534 if (!master_saif->mclk_in_use) 535 __raw_writel(BM_SAIF_CTRL_RUN, 536 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 537 538 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 539 /* 540 * write data to saif data register to trigger 541 * the transfer. 542 * For 24-bit format the 32-bit FIFO register stores 543 * only one channel, so we need to write twice. 544 * This is also safe for the other non 24-bit formats. 545 */ 546 __raw_writel(0, saif->base + SAIF_DATA); 547 __raw_writel(0, saif->base + SAIF_DATA); 548 } else { 549 /* 550 * read data from saif data register to trigger 551 * the receive. 552 * For 24-bit format the 32-bit FIFO register stores 553 * only one channel, so we need to read twice. 554 * This is also safe for the other non 24-bit formats. 555 */ 556 __raw_readl(saif->base + SAIF_DATA); 557 __raw_readl(saif->base + SAIF_DATA); 558 } 559 560 master_saif->ongoing = 1; 561 saif->state = MXS_SAIF_STATE_RUNNING; 562 563 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 564 __raw_readl(saif->base + SAIF_CTRL), 565 __raw_readl(saif->base + SAIF_STAT)); 566 567 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 568 __raw_readl(master_saif->base + SAIF_CTRL), 569 __raw_readl(master_saif->base + SAIF_STAT)); 570 break; 571 case SNDRV_PCM_TRIGGER_SUSPEND: 572 case SNDRV_PCM_TRIGGER_STOP: 573 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 574 if (saif->state == MXS_SAIF_STATE_STOPPED) 575 return 0; 576 577 dev_dbg(cpu_dai->dev, "stop\n"); 578 579 /* wait a while for the current sample to complete */ 580 delay = USEC_PER_SEC / master_saif->cur_rate; 581 582 if (!master_saif->mclk_in_use) { 583 __raw_writel(BM_SAIF_CTRL_RUN, 584 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 585 udelay(delay); 586 } 587 clk_disable(master_saif->clk); 588 589 if (saif != master_saif) { 590 __raw_writel(BM_SAIF_CTRL_RUN, 591 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 592 udelay(delay); 593 clk_disable(saif->clk); 594 } 595 596 master_saif->ongoing = 0; 597 saif->state = MXS_SAIF_STATE_STOPPED; 598 599 break; 600 default: 601 return -EINVAL; 602 } 603 604 return 0; 605 } 606 607 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 608 #define MXS_SAIF_FORMATS \ 609 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 610 SNDRV_PCM_FMTBIT_S24_LE) 611 612 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 613 .startup = mxs_saif_startup, 614 .trigger = mxs_saif_trigger, 615 .prepare = mxs_saif_prepare, 616 .hw_params = mxs_saif_hw_params, 617 .set_sysclk = mxs_saif_set_dai_sysclk, 618 .set_fmt = mxs_saif_set_dai_fmt, 619 }; 620 621 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 622 { 623 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 624 625 snd_soc_dai_set_drvdata(dai, saif); 626 627 return 0; 628 } 629 630 static struct snd_soc_dai_driver mxs_saif_dai = { 631 .name = "mxs-saif", 632 .probe = mxs_saif_dai_probe, 633 .playback = { 634 .channels_min = 2, 635 .channels_max = 2, 636 .rates = MXS_SAIF_RATES, 637 .formats = MXS_SAIF_FORMATS, 638 }, 639 .capture = { 640 .channels_min = 2, 641 .channels_max = 2, 642 .rates = MXS_SAIF_RATES, 643 .formats = MXS_SAIF_FORMATS, 644 }, 645 .ops = &mxs_saif_dai_ops, 646 }; 647 648 static const struct snd_soc_component_driver mxs_saif_component = { 649 .name = "mxs-saif", 650 }; 651 652 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 653 { 654 struct mxs_saif *saif = dev_id; 655 unsigned int stat; 656 657 stat = __raw_readl(saif->base + SAIF_STAT); 658 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 659 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 660 return IRQ_NONE; 661 662 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 663 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 664 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 665 saif->base + SAIF_STAT + MXS_CLR_ADDR); 666 } 667 668 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 669 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 670 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 671 saif->base + SAIF_STAT + MXS_CLR_ADDR); 672 } 673 674 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 675 __raw_readl(saif->base + SAIF_CTRL), 676 __raw_readl(saif->base + SAIF_STAT)); 677 678 return IRQ_HANDLED; 679 } 680 681 static int mxs_saif_mclk_init(struct platform_device *pdev) 682 { 683 struct mxs_saif *saif = platform_get_drvdata(pdev); 684 struct device_node *np = pdev->dev.of_node; 685 struct clk *clk; 686 int ret; 687 688 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 689 __clk_get_name(saif->clk), 0, 690 saif->base + SAIF_CTRL, 691 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 692 0, NULL); 693 if (IS_ERR(clk)) { 694 ret = PTR_ERR(clk); 695 if (ret == -EEXIST) 696 return 0; 697 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 698 return PTR_ERR(clk); 699 } 700 701 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 702 if (ret) 703 return ret; 704 705 return 0; 706 } 707 708 static int mxs_saif_probe(struct platform_device *pdev) 709 { 710 struct device_node *np = pdev->dev.of_node; 711 struct resource *iores; 712 struct mxs_saif *saif; 713 int irq, ret = 0; 714 struct device_node *master; 715 716 if (!np) 717 return -EINVAL; 718 719 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 720 if (!saif) 721 return -ENOMEM; 722 723 ret = of_alias_get_id(np, "saif"); 724 if (ret < 0) 725 return ret; 726 else 727 saif->id = ret; 728 729 /* 730 * If there is no "fsl,saif-master" phandle, it's a saif 731 * master. Otherwise, it's a slave and its phandle points 732 * to the master. 733 */ 734 master = of_parse_phandle(np, "fsl,saif-master", 0); 735 if (!master) { 736 saif->master_id = saif->id; 737 } else { 738 ret = of_alias_get_id(master, "saif"); 739 if (ret < 0) 740 return ret; 741 else 742 saif->master_id = ret; 743 } 744 745 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 746 dev_err(&pdev->dev, "get wrong master id\n"); 747 return -EINVAL; 748 } 749 750 mxs_saif[saif->id] = saif; 751 752 saif->clk = devm_clk_get(&pdev->dev, NULL); 753 if (IS_ERR(saif->clk)) { 754 ret = PTR_ERR(saif->clk); 755 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 756 ret); 757 return ret; 758 } 759 760 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 761 762 saif->base = devm_ioremap_resource(&pdev->dev, iores); 763 if (IS_ERR(saif->base)) 764 return PTR_ERR(saif->base); 765 766 irq = platform_get_irq(pdev, 0); 767 if (irq < 0) { 768 ret = irq; 769 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 770 ret); 771 return ret; 772 } 773 774 saif->dev = &pdev->dev; 775 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 776 dev_name(&pdev->dev), saif); 777 if (ret) { 778 dev_err(&pdev->dev, "failed to request irq\n"); 779 return ret; 780 } 781 782 platform_set_drvdata(pdev, saif); 783 784 /* We only support saif0 being tx and clock master */ 785 if (saif->id == 0) { 786 ret = mxs_saif_mclk_init(pdev); 787 if (ret) 788 dev_warn(&pdev->dev, "failed to init clocks\n"); 789 } 790 791 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 792 &mxs_saif_dai, 1); 793 if (ret) { 794 dev_err(&pdev->dev, "register DAI failed\n"); 795 return ret; 796 } 797 798 ret = mxs_pcm_platform_register(&pdev->dev); 799 if (ret) { 800 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 801 return ret; 802 } 803 804 return 0; 805 } 806 807 static const struct of_device_id mxs_saif_dt_ids[] = { 808 { .compatible = "fsl,imx28-saif", }, 809 { /* sentinel */ } 810 }; 811 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 812 813 static struct platform_driver mxs_saif_driver = { 814 .probe = mxs_saif_probe, 815 816 .driver = { 817 .name = "mxs-saif", 818 .of_match_table = mxs_saif_dt_ids, 819 }, 820 }; 821 822 module_platform_driver(mxs_saif_driver); 823 824 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 825 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 826 MODULE_LICENSE("GPL"); 827 MODULE_ALIAS("platform:mxs-saif"); 828