xref: /linux/sound/soc/mxs/mxs-saif.c (revision b43ab901d671e3e3cad425ea5e9a3c74e266dcdd)
1 /*
2  * Copyright 2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License as published by
6  * the Free Software Foundation; either version 2 of the License, or
7  * (at your option) any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License along
15  * with this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17  */
18 
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/platform_device.h>
22 #include <linux/slab.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/clk.h>
25 #include <linux/delay.h>
26 #include <linux/time.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/saif.h>
32 #include <mach/dma.h>
33 #include <asm/mach-types.h>
34 #include <mach/hardware.h>
35 #include <mach/mxs.h>
36 
37 #include "mxs-saif.h"
38 
39 static struct mxs_saif *mxs_saif[2];
40 
41 /*
42  * SAIF is a little different with other normal SOC DAIs on clock using.
43  *
44  * For MXS, two SAIF modules are instantiated on-chip.
45  * Each SAIF has a set of clock pins and can be operating in master
46  * mode simultaneously if they are connected to different off-chip codecs.
47  * Also, one of the two SAIFs can master or drive the clock pins while the
48  * other SAIF, in slave mode, receives clocking from the master SAIF.
49  * This also means that both SAIFs must operate at the same sample rate.
50  *
51  * We abstract this as each saif has a master, the master could be
52  * himself or other saifs. In the generic saif driver, saif does not need
53  * to know the different clkmux. Saif only needs to know who is his master
54  * and operating his master to generate the proper clock rate for him.
55  * The master id is provided in mach-specific layer according to different
56  * clkmux setting.
57  */
58 
59 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
60 			int clk_id, unsigned int freq, int dir)
61 {
62 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
63 
64 	switch (clk_id) {
65 	case MXS_SAIF_MCLK:
66 		saif->mclk = freq;
67 		break;
68 	default:
69 		return -EINVAL;
70 	}
71 	return 0;
72 }
73 
74 /*
75  * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK
76  * is provided by other SAIF, we provide a interface here to get its master
77  * from its master_id.
78  * Note that the master could be himself.
79  */
80 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif)
81 {
82 	return mxs_saif[saif->master_id];
83 }
84 
85 /*
86  * Set SAIF clock and MCLK
87  */
88 static int mxs_saif_set_clk(struct mxs_saif *saif,
89 				  unsigned int mclk,
90 				  unsigned int rate)
91 {
92 	u32 scr;
93 	int ret;
94 	struct mxs_saif *master_saif;
95 
96 	dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate);
97 
98 	/* Set master saif to generate proper clock */
99 	master_saif = mxs_saif_get_master(saif);
100 	if (!master_saif)
101 		return -EINVAL;
102 
103 	dev_dbg(saif->dev, "master saif%d\n", master_saif->id);
104 
105 	/* Checking if can playback and capture simutaneously */
106 	if (master_saif->ongoing && rate != master_saif->cur_rate) {
107 		dev_err(saif->dev,
108 			"can not change clock, master saif%d(rate %d) is ongoing\n",
109 			master_saif->id, master_saif->cur_rate);
110 		return -EINVAL;
111 	}
112 
113 	scr = __raw_readl(master_saif->base + SAIF_CTRL);
114 	scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE;
115 	scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
116 
117 	/*
118 	 * Set SAIF clock
119 	 *
120 	 * The SAIF clock should be either 384*fs or 512*fs.
121 	 * If MCLK is used, the SAIF clk ratio need to match mclk ratio.
122 	 *  For 32x mclk, set saif clk as 512*fs.
123 	 *  For 48x mclk, set saif clk as 384*fs.
124 	 *
125 	 * If MCLK is not used, we just set saif clk to 512*fs.
126 	 */
127 	if (master_saif->mclk_in_use) {
128 		if (mclk % 32 == 0) {
129 			scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
130 			ret = clk_set_rate(master_saif->clk, 512 * rate);
131 		} else if (mclk % 48 == 0) {
132 			scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
133 			ret = clk_set_rate(master_saif->clk, 384 * rate);
134 		} else {
135 			/* SAIF MCLK should be either 32x or 48x */
136 			return -EINVAL;
137 		}
138 	} else {
139 		ret = clk_set_rate(master_saif->clk, 512 * rate);
140 		scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
141 	}
142 
143 	if (ret)
144 		return ret;
145 
146 	master_saif->cur_rate = rate;
147 
148 	if (!master_saif->mclk_in_use) {
149 		__raw_writel(scr, master_saif->base + SAIF_CTRL);
150 		return 0;
151 	}
152 
153 	/*
154 	 * Program the over-sample rate for MCLK output
155 	 *
156 	 * The available MCLK range is 32x, 48x... 512x. The rate
157 	 * could be from 8kHz to 192kH.
158 	 */
159 	switch (mclk / rate) {
160 	case 32:
161 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4);
162 		break;
163 	case 64:
164 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
165 		break;
166 	case 128:
167 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
168 		break;
169 	case 256:
170 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
171 		break;
172 	case 512:
173 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
174 		break;
175 	case 48:
176 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3);
177 		break;
178 	case 96:
179 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2);
180 		break;
181 	case 192:
182 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1);
183 		break;
184 	case 384:
185 		scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0);
186 		break;
187 	default:
188 		return -EINVAL;
189 	}
190 
191 	__raw_writel(scr, master_saif->base + SAIF_CTRL);
192 
193 	return 0;
194 }
195 
196 /*
197  * Put and disable MCLK.
198  */
199 int mxs_saif_put_mclk(unsigned int saif_id)
200 {
201 	struct mxs_saif *saif = mxs_saif[saif_id];
202 	u32 stat;
203 
204 	if (!saif)
205 		return -EINVAL;
206 
207 	stat = __raw_readl(saif->base + SAIF_STAT);
208 	if (stat & BM_SAIF_STAT_BUSY) {
209 		dev_err(saif->dev, "error: busy\n");
210 		return -EBUSY;
211 	}
212 
213 	clk_disable_unprepare(saif->clk);
214 
215 	/* disable MCLK output */
216 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
217 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
218 	__raw_writel(BM_SAIF_CTRL_RUN,
219 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
220 
221 	saif->mclk_in_use = 0;
222 	return 0;
223 }
224 
225 /*
226  * Get MCLK and set clock rate, then enable it
227  *
228  * This interface is used for codecs who are using MCLK provided
229  * by saif.
230  */
231 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
232 					unsigned int rate)
233 {
234 	struct mxs_saif *saif = mxs_saif[saif_id];
235 	u32 stat;
236 	int ret;
237 	struct mxs_saif *master_saif;
238 
239 	if (!saif)
240 		return -EINVAL;
241 
242 	/* Clear Reset */
243 	__raw_writel(BM_SAIF_CTRL_SFTRST,
244 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
245 
246 	/* FIXME: need clear clk gate for register r/w */
247 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
248 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
249 
250 	master_saif = mxs_saif_get_master(saif);
251 	if (saif != master_saif) {
252 		dev_err(saif->dev, "can not get mclk from a non-master saif\n");
253 		return -EINVAL;
254 	}
255 
256 	stat = __raw_readl(saif->base + SAIF_STAT);
257 	if (stat & BM_SAIF_STAT_BUSY) {
258 		dev_err(saif->dev, "error: busy\n");
259 		return -EBUSY;
260 	}
261 
262 	saif->mclk_in_use = 1;
263 	ret = mxs_saif_set_clk(saif, mclk, rate);
264 	if (ret)
265 		return ret;
266 
267 	ret = clk_prepare_enable(saif->clk);
268 	if (ret)
269 		return ret;
270 
271 	/* enable MCLK output */
272 	__raw_writel(BM_SAIF_CTRL_RUN,
273 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
274 
275 	return 0;
276 }
277 
278 /*
279  * SAIF DAI format configuration.
280  * Should only be called when port is inactive.
281  */
282 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
283 {
284 	u32 scr, stat;
285 	u32 scr0;
286 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
287 
288 	stat = __raw_readl(saif->base + SAIF_STAT);
289 	if (stat & BM_SAIF_STAT_BUSY) {
290 		dev_err(cpu_dai->dev, "error: busy\n");
291 		return -EBUSY;
292 	}
293 
294 	scr0 = __raw_readl(saif->base + SAIF_CTRL);
295 	scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \
296 		& ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY;
297 	scr = 0;
298 
299 	/* DAI mode */
300 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
301 	case SND_SOC_DAIFMT_I2S:
302 		/* data frame low 1clk before data */
303 		scr |= BM_SAIF_CTRL_DELAY;
304 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
305 		break;
306 	case SND_SOC_DAIFMT_LEFT_J:
307 		/* data frame high with data */
308 		scr &= ~BM_SAIF_CTRL_DELAY;
309 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
310 		scr &= ~BM_SAIF_CTRL_JUSTIFY;
311 		break;
312 	default:
313 		return -EINVAL;
314 	}
315 
316 	/* DAI clock inversion */
317 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
318 	case SND_SOC_DAIFMT_IB_IF:
319 		scr |= BM_SAIF_CTRL_BITCLK_EDGE;
320 		scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
321 		break;
322 	case SND_SOC_DAIFMT_IB_NF:
323 		scr |= BM_SAIF_CTRL_BITCLK_EDGE;
324 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
325 		break;
326 	case SND_SOC_DAIFMT_NB_IF:
327 		scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
328 		scr |= BM_SAIF_CTRL_LRCLK_POLARITY;
329 		break;
330 	case SND_SOC_DAIFMT_NB_NF:
331 		scr &= ~BM_SAIF_CTRL_BITCLK_EDGE;
332 		scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY;
333 		break;
334 	}
335 
336 	/*
337 	 * Note: We simply just support master mode since SAIF TX can only
338 	 * work as master.
339 	 * Here the master is relative to codec side.
340 	 * Saif internally could be slave when working on EXTMASTER mode.
341 	 * We just hide this to machine driver.
342 	 */
343 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
344 	case SND_SOC_DAIFMT_CBS_CFS:
345 		if (saif->id == saif->master_id)
346 			scr &= ~BM_SAIF_CTRL_SLAVE_MODE;
347 		else
348 			scr |= BM_SAIF_CTRL_SLAVE_MODE;
349 
350 		__raw_writel(scr | scr0, saif->base + SAIF_CTRL);
351 		break;
352 	default:
353 		return -EINVAL;
354 	}
355 
356 	return 0;
357 }
358 
359 static int mxs_saif_startup(struct snd_pcm_substream *substream,
360 			   struct snd_soc_dai *cpu_dai)
361 {
362 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
363 	snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param);
364 
365 	/* clear error status to 0 for each re-open */
366 	saif->fifo_underrun = 0;
367 	saif->fifo_overrun = 0;
368 
369 	/* Clear Reset for normal operations */
370 	__raw_writel(BM_SAIF_CTRL_SFTRST,
371 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
372 
373 	/* clear clock gate */
374 	__raw_writel(BM_SAIF_CTRL_CLKGATE,
375 		saif->base + SAIF_CTRL + MXS_CLR_ADDR);
376 
377 	return 0;
378 }
379 
380 /*
381  * Should only be called when port is inactive.
382  * although can be called multiple times by upper layers.
383  */
384 static int mxs_saif_hw_params(struct snd_pcm_substream *substream,
385 			     struct snd_pcm_hw_params *params,
386 			     struct snd_soc_dai *cpu_dai)
387 {
388 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
389 	u32 scr, stat;
390 	int ret;
391 
392 	/* mclk should already be set */
393 	if (!saif->mclk && saif->mclk_in_use) {
394 		dev_err(cpu_dai->dev, "set mclk first\n");
395 		return -EINVAL;
396 	}
397 
398 	stat = __raw_readl(saif->base + SAIF_STAT);
399 	if (stat & BM_SAIF_STAT_BUSY) {
400 		dev_err(cpu_dai->dev, "error: busy\n");
401 		return -EBUSY;
402 	}
403 
404 	/*
405 	 * Set saif clk based on sample rate.
406 	 * If mclk is used, we also set mclk, if not, saif->mclk is
407 	 * default 0, means not used.
408 	 */
409 	ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params));
410 	if (ret) {
411 		dev_err(cpu_dai->dev, "unable to get proper clk\n");
412 		return ret;
413 	}
414 
415 	scr = __raw_readl(saif->base + SAIF_CTRL);
416 
417 	scr &= ~BM_SAIF_CTRL_WORD_LENGTH;
418 	scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
419 	switch (params_format(params)) {
420 	case SNDRV_PCM_FORMAT_S16_LE:
421 		scr |= BF_SAIF_CTRL_WORD_LENGTH(0);
422 		break;
423 	case SNDRV_PCM_FORMAT_S20_3LE:
424 		scr |= BF_SAIF_CTRL_WORD_LENGTH(4);
425 		scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
426 		break;
427 	case SNDRV_PCM_FORMAT_S24_LE:
428 		scr |= BF_SAIF_CTRL_WORD_LENGTH(8);
429 		scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE;
430 		break;
431 	default:
432 		return -EINVAL;
433 	}
434 
435 	/* Tx/Rx config */
436 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
437 		/* enable TX mode */
438 		scr &= ~BM_SAIF_CTRL_READ_MODE;
439 	} else {
440 		/* enable RX mode */
441 		scr |= BM_SAIF_CTRL_READ_MODE;
442 	}
443 
444 	__raw_writel(scr, saif->base + SAIF_CTRL);
445 	return 0;
446 }
447 
448 static int mxs_saif_prepare(struct snd_pcm_substream *substream,
449 			   struct snd_soc_dai *cpu_dai)
450 {
451 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
452 
453 	/* enable FIFO error irqs */
454 	__raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN,
455 		saif->base + SAIF_CTRL + MXS_SET_ADDR);
456 
457 	return 0;
458 }
459 
460 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd,
461 				struct snd_soc_dai *cpu_dai)
462 {
463 	struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai);
464 	struct mxs_saif *master_saif;
465 	u32 delay;
466 
467 	master_saif = mxs_saif_get_master(saif);
468 	if (!master_saif)
469 		return -EINVAL;
470 
471 	switch (cmd) {
472 	case SNDRV_PCM_TRIGGER_START:
473 	case SNDRV_PCM_TRIGGER_RESUME:
474 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
475 		dev_dbg(cpu_dai->dev, "start\n");
476 
477 		clk_enable(master_saif->clk);
478 		if (!master_saif->mclk_in_use)
479 			__raw_writel(BM_SAIF_CTRL_RUN,
480 				master_saif->base + SAIF_CTRL + MXS_SET_ADDR);
481 
482 		/*
483 		 * If the saif's master is not himself, we also need to enable
484 		 * itself clk for its internal basic logic to work.
485 		 */
486 		if (saif != master_saif) {
487 			clk_enable(saif->clk);
488 			__raw_writel(BM_SAIF_CTRL_RUN,
489 				saif->base + SAIF_CTRL + MXS_SET_ADDR);
490 		}
491 
492 		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
493 			/*
494 			 * write a data to saif data register to trigger
495 			 * the transfer
496 			 */
497 			__raw_writel(0, saif->base + SAIF_DATA);
498 		} else {
499 			/*
500 			 * read a data from saif data register to trigger
501 			 * the receive
502 			 */
503 			__raw_readl(saif->base + SAIF_DATA);
504 		}
505 
506 		master_saif->ongoing = 1;
507 
508 		dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n",
509 			__raw_readl(saif->base + SAIF_CTRL),
510 			__raw_readl(saif->base + SAIF_STAT));
511 
512 		dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n",
513 			__raw_readl(master_saif->base + SAIF_CTRL),
514 			__raw_readl(master_saif->base + SAIF_STAT));
515 		break;
516 	case SNDRV_PCM_TRIGGER_SUSPEND:
517 	case SNDRV_PCM_TRIGGER_STOP:
518 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
519 		dev_dbg(cpu_dai->dev, "stop\n");
520 
521 		/* wait a while for the current sample to complete */
522 		delay = USEC_PER_SEC / master_saif->cur_rate;
523 
524 		if (!master_saif->mclk_in_use) {
525 			__raw_writel(BM_SAIF_CTRL_RUN,
526 				master_saif->base + SAIF_CTRL + MXS_CLR_ADDR);
527 			udelay(delay);
528 		}
529 		clk_disable(master_saif->clk);
530 
531 		if (saif != master_saif) {
532 			__raw_writel(BM_SAIF_CTRL_RUN,
533 				saif->base + SAIF_CTRL + MXS_CLR_ADDR);
534 			udelay(delay);
535 			clk_disable(saif->clk);
536 		}
537 
538 		master_saif->ongoing = 0;
539 
540 		break;
541 	default:
542 		return -EINVAL;
543 	}
544 
545 	return 0;
546 }
547 
548 #define MXS_SAIF_RATES		SNDRV_PCM_RATE_8000_192000
549 #define MXS_SAIF_FORMATS \
550 	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
551 	SNDRV_PCM_FMTBIT_S24_LE)
552 
553 static const struct snd_soc_dai_ops mxs_saif_dai_ops = {
554 	.startup = mxs_saif_startup,
555 	.trigger = mxs_saif_trigger,
556 	.prepare = mxs_saif_prepare,
557 	.hw_params = mxs_saif_hw_params,
558 	.set_sysclk = mxs_saif_set_dai_sysclk,
559 	.set_fmt = mxs_saif_set_dai_fmt,
560 };
561 
562 static int mxs_saif_dai_probe(struct snd_soc_dai *dai)
563 {
564 	struct mxs_saif *saif = dev_get_drvdata(dai->dev);
565 
566 	snd_soc_dai_set_drvdata(dai, saif);
567 
568 	return 0;
569 }
570 
571 static struct snd_soc_dai_driver mxs_saif_dai = {
572 	.name = "mxs-saif",
573 	.probe = mxs_saif_dai_probe,
574 	.playback = {
575 		.channels_min = 2,
576 		.channels_max = 2,
577 		.rates = MXS_SAIF_RATES,
578 		.formats = MXS_SAIF_FORMATS,
579 	},
580 	.capture = {
581 		.channels_min = 2,
582 		.channels_max = 2,
583 		.rates = MXS_SAIF_RATES,
584 		.formats = MXS_SAIF_FORMATS,
585 	},
586 	.ops = &mxs_saif_dai_ops,
587 };
588 
589 static irqreturn_t mxs_saif_irq(int irq, void *dev_id)
590 {
591 	struct mxs_saif *saif = dev_id;
592 	unsigned int stat;
593 
594 	stat = __raw_readl(saif->base + SAIF_STAT);
595 	if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ |
596 			BM_SAIF_STAT_FIFO_OVERFLOW_IRQ)))
597 		return IRQ_NONE;
598 
599 	if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) {
600 		dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun);
601 		__raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ,
602 				saif->base + SAIF_STAT + MXS_CLR_ADDR);
603 	}
604 
605 	if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) {
606 		dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun);
607 		__raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ,
608 				saif->base + SAIF_STAT + MXS_CLR_ADDR);
609 	}
610 
611 	dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n",
612 	       __raw_readl(saif->base + SAIF_CTRL),
613 	       __raw_readl(saif->base + SAIF_STAT));
614 
615 	return IRQ_HANDLED;
616 }
617 
618 static int mxs_saif_probe(struct platform_device *pdev)
619 {
620 	struct resource *iores, *dmares;
621 	struct mxs_saif *saif;
622 	struct mxs_saif_platform_data *pdata;
623 	int ret = 0;
624 
625 	if (pdev->id >= ARRAY_SIZE(mxs_saif))
626 		return -EINVAL;
627 
628 	saif = kzalloc(sizeof(*saif), GFP_KERNEL);
629 	if (!saif)
630 		return -ENOMEM;
631 
632 	mxs_saif[pdev->id] = saif;
633 	saif->id = pdev->id;
634 
635 	pdata = pdev->dev.platform_data;
636 	if (pdata && !pdata->master_mode) {
637 		saif->master_id = pdata->master_id;
638 		if (saif->master_id < 0 ||
639 			saif->master_id >= ARRAY_SIZE(mxs_saif) ||
640 			saif->master_id == saif->id) {
641 			dev_err(&pdev->dev, "get wrong master id\n");
642 			return -EINVAL;
643 		}
644 	} else {
645 		saif->master_id = saif->id;
646 	}
647 
648 	saif->clk = clk_get(&pdev->dev, NULL);
649 	if (IS_ERR(saif->clk)) {
650 		ret = PTR_ERR(saif->clk);
651 		dev_err(&pdev->dev, "Cannot get the clock: %d\n",
652 			ret);
653 		goto failed_clk;
654 	}
655 
656 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
657 	if (!iores) {
658 		ret = -ENODEV;
659 		dev_err(&pdev->dev, "failed to get io resource: %d\n",
660 			ret);
661 		goto failed_get_resource;
662 	}
663 
664 	if (!request_mem_region(iores->start, resource_size(iores),
665 				"mxs-saif")) {
666 		dev_err(&pdev->dev, "request_mem_region failed\n");
667 		ret = -EBUSY;
668 		goto failed_get_resource;
669 	}
670 
671 	saif->base = ioremap(iores->start, resource_size(iores));
672 	if (!saif->base) {
673 		dev_err(&pdev->dev, "ioremap failed\n");
674 		ret = -ENODEV;
675 		goto failed_ioremap;
676 	}
677 
678 	dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
679 	if (!dmares) {
680 		ret = -ENODEV;
681 		dev_err(&pdev->dev, "failed to get dma resource: %d\n",
682 			ret);
683 		goto failed_ioremap;
684 	}
685 	saif->dma_param.chan_num = dmares->start;
686 
687 	saif->irq = platform_get_irq(pdev, 0);
688 	if (saif->irq < 0) {
689 		ret = saif->irq;
690 		dev_err(&pdev->dev, "failed to get irq resource: %d\n",
691 			ret);
692 		goto failed_get_irq1;
693 	}
694 
695 	saif->dev = &pdev->dev;
696 	ret = request_irq(saif->irq, mxs_saif_irq, 0, "mxs-saif", saif);
697 	if (ret) {
698 		dev_err(&pdev->dev, "failed to request irq\n");
699 		goto failed_get_irq1;
700 	}
701 
702 	saif->dma_param.chan_irq = platform_get_irq(pdev, 1);
703 	if (saif->dma_param.chan_irq < 0) {
704 		ret = saif->dma_param.chan_irq;
705 		dev_err(&pdev->dev, "failed to get dma irq resource: %d\n",
706 			ret);
707 		goto failed_get_irq2;
708 	}
709 
710 	platform_set_drvdata(pdev, saif);
711 
712 	ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai);
713 	if (ret) {
714 		dev_err(&pdev->dev, "register DAI failed\n");
715 		goto failed_register;
716 	}
717 
718 	saif->soc_platform_pdev = platform_device_alloc(
719 					"mxs-pcm-audio", pdev->id);
720 	if (!saif->soc_platform_pdev) {
721 		ret = -ENOMEM;
722 		goto failed_pdev_alloc;
723 	}
724 
725 	platform_set_drvdata(saif->soc_platform_pdev, saif);
726 	ret = platform_device_add(saif->soc_platform_pdev);
727 	if (ret) {
728 		dev_err(&pdev->dev, "failed to add soc platform device\n");
729 		goto failed_pdev_add;
730 	}
731 
732 	return 0;
733 
734 failed_pdev_add:
735 	platform_device_put(saif->soc_platform_pdev);
736 failed_pdev_alloc:
737 	snd_soc_unregister_dai(&pdev->dev);
738 failed_register:
739 failed_get_irq2:
740 	free_irq(saif->irq, saif);
741 failed_get_irq1:
742 	iounmap(saif->base);
743 failed_ioremap:
744 	release_mem_region(iores->start, resource_size(iores));
745 failed_get_resource:
746 	clk_put(saif->clk);
747 failed_clk:
748 	kfree(saif);
749 
750 	return ret;
751 }
752 
753 static int __devexit mxs_saif_remove(struct platform_device *pdev)
754 {
755 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
756 	struct mxs_saif *saif = platform_get_drvdata(pdev);
757 
758 	platform_device_unregister(saif->soc_platform_pdev);
759 
760 	snd_soc_unregister_dai(&pdev->dev);
761 
762 	iounmap(saif->base);
763 	release_mem_region(res->start, resource_size(res));
764 	free_irq(saif->irq, saif);
765 
766 	clk_put(saif->clk);
767 	kfree(saif);
768 
769 	return 0;
770 }
771 
772 static struct platform_driver mxs_saif_driver = {
773 	.probe = mxs_saif_probe,
774 	.remove = __devexit_p(mxs_saif_remove),
775 
776 	.driver = {
777 		.name = "mxs-saif",
778 		.owner = THIS_MODULE,
779 	},
780 };
781 
782 module_platform_driver(mxs_saif_driver);
783 
784 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
785 MODULE_DESCRIPTION("MXS ASoC SAIF driver");
786 MODULE_LICENSE("GPL");
787