1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2011 Freescale Semiconductor, Inc. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/init.h> 8 #include <linux/of.h> 9 #include <linux/of_device.h> 10 #include <linux/platform_device.h> 11 #include <linux/slab.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 15 #include <linux/delay.h> 16 #include <linux/io.h> 17 #include <linux/time.h> 18 #include <sound/core.h> 19 #include <sound/pcm.h> 20 #include <sound/pcm_params.h> 21 #include <sound/soc.h> 22 23 #include "mxs-saif.h" 24 25 #define MXS_SET_ADDR 0x4 26 #define MXS_CLR_ADDR 0x8 27 28 static struct mxs_saif *mxs_saif[2]; 29 30 /* 31 * SAIF is a little different with other normal SOC DAIs on clock using. 32 * 33 * For MXS, two SAIF modules are instantiated on-chip. 34 * Each SAIF has a set of clock pins and can be operating in master 35 * mode simultaneously if they are connected to different off-chip codecs. 36 * Also, one of the two SAIFs can master or drive the clock pins while the 37 * other SAIF, in slave mode, receives clocking from the master SAIF. 38 * This also means that both SAIFs must operate at the same sample rate. 39 * 40 * We abstract this as each saif has a master, the master could be 41 * itself or other saifs. In the generic saif driver, saif does not need 42 * to know the different clkmux. Saif only needs to know who is its master 43 * and operating its master to generate the proper clock rate for it. 44 * The master id is provided in mach-specific layer according to different 45 * clkmux setting. 46 */ 47 48 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 49 int clk_id, unsigned int freq, int dir) 50 { 51 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 52 53 switch (clk_id) { 54 case MXS_SAIF_MCLK: 55 saif->mclk = freq; 56 break; 57 default: 58 return -EINVAL; 59 } 60 return 0; 61 } 62 63 /* 64 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 65 * is provided by other SAIF, we provide a interface here to get its master 66 * from its master_id. 67 * Note that the master could be itself. 68 */ 69 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 70 { 71 return mxs_saif[saif->master_id]; 72 } 73 74 /* 75 * Set SAIF clock and MCLK 76 */ 77 static int mxs_saif_set_clk(struct mxs_saif *saif, 78 unsigned int mclk, 79 unsigned int rate) 80 { 81 u32 scr; 82 int ret; 83 struct mxs_saif *master_saif; 84 85 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 86 87 /* Set master saif to generate proper clock */ 88 master_saif = mxs_saif_get_master(saif); 89 if (!master_saif) 90 return -EINVAL; 91 92 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 93 94 /* Checking if can playback and capture simutaneously */ 95 if (master_saif->ongoing && rate != master_saif->cur_rate) { 96 dev_err(saif->dev, 97 "can not change clock, master saif%d(rate %d) is ongoing\n", 98 master_saif->id, master_saif->cur_rate); 99 return -EINVAL; 100 } 101 102 scr = __raw_readl(master_saif->base + SAIF_CTRL); 103 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 104 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 105 106 /* 107 * Set SAIF clock 108 * 109 * The SAIF clock should be either 384*fs or 512*fs. 110 * If MCLK is used, the SAIF clk ratio needs to match mclk ratio. 111 * For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs. 112 * For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs. 113 * 114 * If MCLK is not used, we just set saif clk to 512*fs. 115 */ 116 ret = clk_prepare_enable(master_saif->clk); 117 if (ret) 118 return ret; 119 120 if (master_saif->mclk_in_use) { 121 switch (mclk / rate) { 122 case 32: 123 case 64: 124 case 128: 125 case 256: 126 case 512: 127 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 128 ret = clk_set_rate(master_saif->clk, 512 * rate); 129 break; 130 case 48: 131 case 96: 132 case 192: 133 case 384: 134 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 135 ret = clk_set_rate(master_saif->clk, 384 * rate); 136 break; 137 default: 138 /* SAIF MCLK should be a sub-rate of 512x or 384x */ 139 clk_disable_unprepare(master_saif->clk); 140 return -EINVAL; 141 } 142 } else { 143 ret = clk_set_rate(master_saif->clk, 512 * rate); 144 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 145 } 146 147 clk_disable_unprepare(master_saif->clk); 148 149 if (ret) 150 return ret; 151 152 master_saif->cur_rate = rate; 153 154 if (!master_saif->mclk_in_use) { 155 __raw_writel(scr, master_saif->base + SAIF_CTRL); 156 return 0; 157 } 158 159 /* 160 * Program the over-sample rate for MCLK output 161 * 162 * The available MCLK range is 32x, 48x... 512x. The rate 163 * could be from 8kHz to 192kH. 164 */ 165 switch (mclk / rate) { 166 case 32: 167 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 168 break; 169 case 64: 170 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 171 break; 172 case 128: 173 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 174 break; 175 case 256: 176 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 177 break; 178 case 512: 179 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 180 break; 181 case 48: 182 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 183 break; 184 case 96: 185 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 186 break; 187 case 192: 188 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 189 break; 190 case 384: 191 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 192 break; 193 default: 194 return -EINVAL; 195 } 196 197 __raw_writel(scr, master_saif->base + SAIF_CTRL); 198 199 return 0; 200 } 201 202 /* 203 * Put and disable MCLK. 204 */ 205 int mxs_saif_put_mclk(unsigned int saif_id) 206 { 207 struct mxs_saif *saif = mxs_saif[saif_id]; 208 u32 stat; 209 210 if (!saif) 211 return -EINVAL; 212 213 stat = __raw_readl(saif->base + SAIF_STAT); 214 if (stat & BM_SAIF_STAT_BUSY) { 215 dev_err(saif->dev, "error: busy\n"); 216 return -EBUSY; 217 } 218 219 clk_disable_unprepare(saif->clk); 220 221 /* disable MCLK output */ 222 __raw_writel(BM_SAIF_CTRL_CLKGATE, 223 saif->base + SAIF_CTRL + MXS_SET_ADDR); 224 __raw_writel(BM_SAIF_CTRL_RUN, 225 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 226 227 saif->mclk_in_use = 0; 228 return 0; 229 } 230 EXPORT_SYMBOL_GPL(mxs_saif_put_mclk); 231 232 /* 233 * Get MCLK and set clock rate, then enable it 234 * 235 * This interface is used for codecs who are using MCLK provided 236 * by saif. 237 */ 238 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 239 unsigned int rate) 240 { 241 struct mxs_saif *saif = mxs_saif[saif_id]; 242 u32 stat; 243 int ret; 244 struct mxs_saif *master_saif; 245 246 if (!saif) 247 return -EINVAL; 248 249 /* Clear Reset */ 250 __raw_writel(BM_SAIF_CTRL_SFTRST, 251 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 252 253 /* FIXME: need clear clk gate for register r/w */ 254 __raw_writel(BM_SAIF_CTRL_CLKGATE, 255 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 256 257 master_saif = mxs_saif_get_master(saif); 258 if (saif != master_saif) { 259 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 260 return -EINVAL; 261 } 262 263 stat = __raw_readl(saif->base + SAIF_STAT); 264 if (stat & BM_SAIF_STAT_BUSY) { 265 dev_err(saif->dev, "error: busy\n"); 266 return -EBUSY; 267 } 268 269 saif->mclk_in_use = 1; 270 ret = mxs_saif_set_clk(saif, mclk, rate); 271 if (ret) 272 return ret; 273 274 ret = clk_prepare_enable(saif->clk); 275 if (ret) 276 return ret; 277 278 /* enable MCLK output */ 279 __raw_writel(BM_SAIF_CTRL_RUN, 280 saif->base + SAIF_CTRL + MXS_SET_ADDR); 281 282 return 0; 283 } 284 EXPORT_SYMBOL_GPL(mxs_saif_get_mclk); 285 286 /* 287 * SAIF DAI format configuration. 288 * Should only be called when port is inactive. 289 */ 290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 291 { 292 u32 scr, stat; 293 u32 scr0; 294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 295 296 stat = __raw_readl(saif->base + SAIF_STAT); 297 if (stat & BM_SAIF_STAT_BUSY) { 298 dev_err(cpu_dai->dev, "error: busy\n"); 299 return -EBUSY; 300 } 301 302 /* If SAIF1 is configured as slave, the clk gate needs to be cleared 303 * before the register can be written. 304 */ 305 if (saif->id != saif->master_id) { 306 __raw_writel(BM_SAIF_CTRL_SFTRST, 307 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 308 __raw_writel(BM_SAIF_CTRL_CLKGATE, 309 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 310 } 311 312 scr0 = __raw_readl(saif->base + SAIF_CTRL); 313 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 314 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 315 scr = 0; 316 317 /* DAI mode */ 318 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 319 case SND_SOC_DAIFMT_I2S: 320 /* data frame low 1clk before data */ 321 scr |= BM_SAIF_CTRL_DELAY; 322 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 323 break; 324 case SND_SOC_DAIFMT_LEFT_J: 325 /* data frame high with data */ 326 scr &= ~BM_SAIF_CTRL_DELAY; 327 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 328 scr &= ~BM_SAIF_CTRL_JUSTIFY; 329 break; 330 default: 331 return -EINVAL; 332 } 333 334 /* DAI clock inversion */ 335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 336 case SND_SOC_DAIFMT_IB_IF: 337 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 338 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 339 break; 340 case SND_SOC_DAIFMT_IB_NF: 341 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 342 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 343 break; 344 case SND_SOC_DAIFMT_NB_IF: 345 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 346 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 347 break; 348 case SND_SOC_DAIFMT_NB_NF: 349 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 350 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 351 break; 352 } 353 354 /* 355 * Note: We simply just support master mode since SAIF TX can only 356 * work as master. 357 * Here the master is relative to codec side. 358 * Saif internally could be slave when working on EXTMASTER mode. 359 * We just hide this to machine driver. 360 */ 361 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 362 case SND_SOC_DAIFMT_CBS_CFS: 363 if (saif->id == saif->master_id) 364 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 365 else 366 scr |= BM_SAIF_CTRL_SLAVE_MODE; 367 368 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 369 break; 370 default: 371 return -EINVAL; 372 } 373 374 return 0; 375 } 376 377 static int mxs_saif_startup(struct snd_pcm_substream *substream, 378 struct snd_soc_dai *cpu_dai) 379 { 380 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 381 int ret; 382 383 /* clear error status to 0 for each re-open */ 384 saif->fifo_underrun = 0; 385 saif->fifo_overrun = 0; 386 387 /* Clear Reset for normal operations */ 388 __raw_writel(BM_SAIF_CTRL_SFTRST, 389 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 390 391 /* clear clock gate */ 392 __raw_writel(BM_SAIF_CTRL_CLKGATE, 393 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 394 395 ret = clk_prepare(saif->clk); 396 if (ret) 397 return ret; 398 399 return 0; 400 } 401 402 static void mxs_saif_shutdown(struct snd_pcm_substream *substream, 403 struct snd_soc_dai *cpu_dai) 404 { 405 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 406 407 clk_unprepare(saif->clk); 408 } 409 410 /* 411 * Should only be called when port is inactive. 412 * although can be called multiple times by upper layers. 413 */ 414 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 415 struct snd_pcm_hw_params *params, 416 struct snd_soc_dai *cpu_dai) 417 { 418 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 419 struct mxs_saif *master_saif; 420 u32 scr, stat; 421 int ret; 422 423 master_saif = mxs_saif_get_master(saif); 424 if (!master_saif) 425 return -EINVAL; 426 427 /* mclk should already be set */ 428 if (!saif->mclk && saif->mclk_in_use) { 429 dev_err(cpu_dai->dev, "set mclk first\n"); 430 return -EINVAL; 431 } 432 433 stat = __raw_readl(saif->base + SAIF_STAT); 434 if (!saif->mclk_in_use && (stat & BM_SAIF_STAT_BUSY)) { 435 dev_err(cpu_dai->dev, "error: busy\n"); 436 return -EBUSY; 437 } 438 439 /* 440 * Set saif clk based on sample rate. 441 * If mclk is used, we also set mclk, if not, saif->mclk is 442 * default 0, means not used. 443 */ 444 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 445 if (ret) { 446 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 447 return ret; 448 } 449 450 if (saif != master_saif) { 451 /* 452 * Set an initial clock rate for the saif internal logic to work 453 * properly. This is important when working in EXTMASTER mode 454 * that uses the other saif's BITCLK&LRCLK but it still needs a 455 * basic clock which should be fast enough for the internal 456 * logic. 457 */ 458 clk_enable(saif->clk); 459 ret = clk_set_rate(saif->clk, 24000000); 460 clk_disable(saif->clk); 461 if (ret) 462 return ret; 463 464 ret = clk_prepare(master_saif->clk); 465 if (ret) 466 return ret; 467 } 468 469 scr = __raw_readl(saif->base + SAIF_CTRL); 470 471 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 472 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 473 switch (params_format(params)) { 474 case SNDRV_PCM_FORMAT_S16_LE: 475 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 476 break; 477 case SNDRV_PCM_FORMAT_S20_3LE: 478 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 479 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 480 break; 481 case SNDRV_PCM_FORMAT_S24_LE: 482 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 483 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 /* Tx/Rx config */ 490 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 491 /* enable TX mode */ 492 scr &= ~BM_SAIF_CTRL_READ_MODE; 493 } else { 494 /* enable RX mode */ 495 scr |= BM_SAIF_CTRL_READ_MODE; 496 } 497 498 __raw_writel(scr, saif->base + SAIF_CTRL); 499 return 0; 500 } 501 502 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 503 struct snd_soc_dai *cpu_dai) 504 { 505 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 506 507 /* enable FIFO error irqs */ 508 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 509 saif->base + SAIF_CTRL + MXS_SET_ADDR); 510 511 return 0; 512 } 513 514 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 515 struct snd_soc_dai *cpu_dai) 516 { 517 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 518 struct mxs_saif *master_saif; 519 u32 delay; 520 int ret; 521 522 master_saif = mxs_saif_get_master(saif); 523 if (!master_saif) 524 return -EINVAL; 525 526 switch (cmd) { 527 case SNDRV_PCM_TRIGGER_START: 528 case SNDRV_PCM_TRIGGER_RESUME: 529 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 530 if (saif->state == MXS_SAIF_STATE_RUNNING) 531 return 0; 532 533 dev_dbg(cpu_dai->dev, "start\n"); 534 535 ret = clk_enable(master_saif->clk); 536 if (ret) { 537 dev_err(saif->dev, "Failed to enable master clock\n"); 538 return ret; 539 } 540 541 /* 542 * If the saif's master is not itself, we also need to enable 543 * itself clk for its internal basic logic to work. 544 */ 545 if (saif != master_saif) { 546 ret = clk_enable(saif->clk); 547 if (ret) { 548 dev_err(saif->dev, "Failed to enable master clock\n"); 549 clk_disable(master_saif->clk); 550 return ret; 551 } 552 553 __raw_writel(BM_SAIF_CTRL_RUN, 554 saif->base + SAIF_CTRL + MXS_SET_ADDR); 555 } 556 557 if (!master_saif->mclk_in_use) 558 __raw_writel(BM_SAIF_CTRL_RUN, 559 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 560 561 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 562 /* 563 * write data to saif data register to trigger 564 * the transfer. 565 * For 24-bit format the 32-bit FIFO register stores 566 * only one channel, so we need to write twice. 567 * This is also safe for the other non 24-bit formats. 568 */ 569 __raw_writel(0, saif->base + SAIF_DATA); 570 __raw_writel(0, saif->base + SAIF_DATA); 571 } else { 572 /* 573 * read data from saif data register to trigger 574 * the receive. 575 * For 24-bit format the 32-bit FIFO register stores 576 * only one channel, so we need to read twice. 577 * This is also safe for the other non 24-bit formats. 578 */ 579 __raw_readl(saif->base + SAIF_DATA); 580 __raw_readl(saif->base + SAIF_DATA); 581 } 582 583 master_saif->ongoing = 1; 584 saif->state = MXS_SAIF_STATE_RUNNING; 585 586 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 587 __raw_readl(saif->base + SAIF_CTRL), 588 __raw_readl(saif->base + SAIF_STAT)); 589 590 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 591 __raw_readl(master_saif->base + SAIF_CTRL), 592 __raw_readl(master_saif->base + SAIF_STAT)); 593 break; 594 case SNDRV_PCM_TRIGGER_SUSPEND: 595 case SNDRV_PCM_TRIGGER_STOP: 596 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 597 if (saif->state == MXS_SAIF_STATE_STOPPED) 598 return 0; 599 600 dev_dbg(cpu_dai->dev, "stop\n"); 601 602 /* wait a while for the current sample to complete */ 603 delay = USEC_PER_SEC / master_saif->cur_rate; 604 605 if (!master_saif->mclk_in_use) { 606 __raw_writel(BM_SAIF_CTRL_RUN, 607 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 608 udelay(delay); 609 } 610 clk_disable(master_saif->clk); 611 612 if (saif != master_saif) { 613 __raw_writel(BM_SAIF_CTRL_RUN, 614 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 615 udelay(delay); 616 clk_disable(saif->clk); 617 } 618 619 master_saif->ongoing = 0; 620 saif->state = MXS_SAIF_STATE_STOPPED; 621 622 break; 623 default: 624 return -EINVAL; 625 } 626 627 return 0; 628 } 629 630 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 631 #define MXS_SAIF_FORMATS \ 632 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 633 SNDRV_PCM_FMTBIT_S24_LE) 634 635 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 636 .startup = mxs_saif_startup, 637 .shutdown = mxs_saif_shutdown, 638 .trigger = mxs_saif_trigger, 639 .prepare = mxs_saif_prepare, 640 .hw_params = mxs_saif_hw_params, 641 .set_sysclk = mxs_saif_set_dai_sysclk, 642 .set_fmt = mxs_saif_set_dai_fmt, 643 }; 644 645 static struct snd_soc_dai_driver mxs_saif_dai = { 646 .name = "mxs-saif", 647 .playback = { 648 .channels_min = 2, 649 .channels_max = 2, 650 .rates = MXS_SAIF_RATES, 651 .formats = MXS_SAIF_FORMATS, 652 }, 653 .capture = { 654 .channels_min = 2, 655 .channels_max = 2, 656 .rates = MXS_SAIF_RATES, 657 .formats = MXS_SAIF_FORMATS, 658 }, 659 .ops = &mxs_saif_dai_ops, 660 }; 661 662 static const struct snd_soc_component_driver mxs_saif_component = { 663 .name = "mxs-saif", 664 }; 665 666 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 667 { 668 struct mxs_saif *saif = dev_id; 669 unsigned int stat; 670 671 stat = __raw_readl(saif->base + SAIF_STAT); 672 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 673 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 674 return IRQ_NONE; 675 676 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 677 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 678 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 679 saif->base + SAIF_STAT + MXS_CLR_ADDR); 680 } 681 682 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 683 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 684 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 685 saif->base + SAIF_STAT + MXS_CLR_ADDR); 686 } 687 688 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 689 __raw_readl(saif->base + SAIF_CTRL), 690 __raw_readl(saif->base + SAIF_STAT)); 691 692 return IRQ_HANDLED; 693 } 694 695 static int mxs_saif_mclk_init(struct platform_device *pdev) 696 { 697 struct mxs_saif *saif = platform_get_drvdata(pdev); 698 struct device_node *np = pdev->dev.of_node; 699 struct clk *clk; 700 int ret; 701 702 clk = clk_register_divider(&pdev->dev, "mxs_saif_mclk", 703 __clk_get_name(saif->clk), 0, 704 saif->base + SAIF_CTRL, 705 BP_SAIF_CTRL_BITCLK_MULT_RATE, 3, 706 0, NULL); 707 if (IS_ERR(clk)) { 708 ret = PTR_ERR(clk); 709 if (ret == -EEXIST) 710 return 0; 711 dev_err(&pdev->dev, "failed to register mclk: %d\n", ret); 712 return PTR_ERR(clk); 713 } 714 715 ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); 716 if (ret) 717 return ret; 718 719 return 0; 720 } 721 722 static int mxs_saif_probe(struct platform_device *pdev) 723 { 724 struct device_node *np = pdev->dev.of_node; 725 struct mxs_saif *saif; 726 int irq, ret; 727 struct device_node *master; 728 729 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 730 if (!saif) 731 return -ENOMEM; 732 733 ret = of_alias_get_id(np, "saif"); 734 if (ret < 0) 735 return ret; 736 else 737 saif->id = ret; 738 739 if (saif->id >= ARRAY_SIZE(mxs_saif)) { 740 dev_err(&pdev->dev, "get wrong saif id\n"); 741 return -EINVAL; 742 } 743 744 /* 745 * If there is no "fsl,saif-master" phandle, it's a saif 746 * master. Otherwise, it's a slave and its phandle points 747 * to the master. 748 */ 749 master = of_parse_phandle(np, "fsl,saif-master", 0); 750 if (!master) { 751 saif->master_id = saif->id; 752 } else { 753 ret = of_alias_get_id(master, "saif"); 754 if (ret < 0) 755 return ret; 756 else 757 saif->master_id = ret; 758 759 if (saif->master_id >= ARRAY_SIZE(mxs_saif)) { 760 dev_err(&pdev->dev, "get wrong master id\n"); 761 return -EINVAL; 762 } 763 } 764 765 mxs_saif[saif->id] = saif; 766 767 saif->clk = devm_clk_get(&pdev->dev, NULL); 768 if (IS_ERR(saif->clk)) { 769 ret = PTR_ERR(saif->clk); 770 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 771 ret); 772 return ret; 773 } 774 775 saif->base = devm_platform_ioremap_resource(pdev, 0); 776 if (IS_ERR(saif->base)) 777 return PTR_ERR(saif->base); 778 779 irq = platform_get_irq(pdev, 0); 780 if (irq < 0) 781 return irq; 782 783 saif->dev = &pdev->dev; 784 ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0, 785 dev_name(&pdev->dev), saif); 786 if (ret) { 787 dev_err(&pdev->dev, "failed to request irq\n"); 788 return ret; 789 } 790 791 platform_set_drvdata(pdev, saif); 792 793 /* We only support saif0 being tx and clock master */ 794 if (saif->id == 0) { 795 ret = mxs_saif_mclk_init(pdev); 796 if (ret) 797 dev_warn(&pdev->dev, "failed to init clocks\n"); 798 } 799 800 ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component, 801 &mxs_saif_dai, 1); 802 if (ret) { 803 dev_err(&pdev->dev, "register DAI failed\n"); 804 return ret; 805 } 806 807 ret = mxs_pcm_platform_register(&pdev->dev); 808 if (ret) { 809 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 810 return ret; 811 } 812 813 return 0; 814 } 815 816 static const struct of_device_id mxs_saif_dt_ids[] = { 817 { .compatible = "fsl,imx28-saif", }, 818 { /* sentinel */ } 819 }; 820 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 821 822 static struct platform_driver mxs_saif_driver = { 823 .probe = mxs_saif_probe, 824 825 .driver = { 826 .name = "mxs-saif", 827 .of_match_table = mxs_saif_dt_ids, 828 }, 829 }; 830 831 module_platform_driver(mxs_saif_driver); 832 833 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 834 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 835 MODULE_LICENSE("GPL"); 836 MODULE_ALIAS("platform:mxs-saif"); 837