1 /* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License along 15 * with this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 17 */ 18 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/slab.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/delay.h> 28 #include <linux/time.h> 29 #include <linux/fsl/mxs-dma.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <sound/core.h> 32 #include <sound/pcm.h> 33 #include <sound/pcm_params.h> 34 #include <sound/soc.h> 35 #include <sound/saif.h> 36 #include <asm/mach-types.h> 37 #include <mach/hardware.h> 38 #include <mach/mxs.h> 39 40 #include "mxs-saif.h" 41 42 static struct mxs_saif *mxs_saif[2]; 43 44 /* 45 * SAIF is a little different with other normal SOC DAIs on clock using. 46 * 47 * For MXS, two SAIF modules are instantiated on-chip. 48 * Each SAIF has a set of clock pins and can be operating in master 49 * mode simultaneously if they are connected to different off-chip codecs. 50 * Also, one of the two SAIFs can master or drive the clock pins while the 51 * other SAIF, in slave mode, receives clocking from the master SAIF. 52 * This also means that both SAIFs must operate at the same sample rate. 53 * 54 * We abstract this as each saif has a master, the master could be 55 * himself or other saifs. In the generic saif driver, saif does not need 56 * to know the different clkmux. Saif only needs to know who is his master 57 * and operating his master to generate the proper clock rate for him. 58 * The master id is provided in mach-specific layer according to different 59 * clkmux setting. 60 */ 61 62 static int mxs_saif_set_dai_sysclk(struct snd_soc_dai *cpu_dai, 63 int clk_id, unsigned int freq, int dir) 64 { 65 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 66 67 switch (clk_id) { 68 case MXS_SAIF_MCLK: 69 saif->mclk = freq; 70 break; 71 default: 72 return -EINVAL; 73 } 74 return 0; 75 } 76 77 /* 78 * Since SAIF may work on EXTMASTER mode, IOW, it's working BITCLK&LRCLK 79 * is provided by other SAIF, we provide a interface here to get its master 80 * from its master_id. 81 * Note that the master could be himself. 82 */ 83 static inline struct mxs_saif *mxs_saif_get_master(struct mxs_saif * saif) 84 { 85 return mxs_saif[saif->master_id]; 86 } 87 88 /* 89 * Set SAIF clock and MCLK 90 */ 91 static int mxs_saif_set_clk(struct mxs_saif *saif, 92 unsigned int mclk, 93 unsigned int rate) 94 { 95 u32 scr; 96 int ret; 97 struct mxs_saif *master_saif; 98 99 dev_dbg(saif->dev, "mclk %d rate %d\n", mclk, rate); 100 101 /* Set master saif to generate proper clock */ 102 master_saif = mxs_saif_get_master(saif); 103 if (!master_saif) 104 return -EINVAL; 105 106 dev_dbg(saif->dev, "master saif%d\n", master_saif->id); 107 108 /* Checking if can playback and capture simutaneously */ 109 if (master_saif->ongoing && rate != master_saif->cur_rate) { 110 dev_err(saif->dev, 111 "can not change clock, master saif%d(rate %d) is ongoing\n", 112 master_saif->id, master_saif->cur_rate); 113 return -EINVAL; 114 } 115 116 scr = __raw_readl(master_saif->base + SAIF_CTRL); 117 scr &= ~BM_SAIF_CTRL_BITCLK_MULT_RATE; 118 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 119 120 /* 121 * Set SAIF clock 122 * 123 * The SAIF clock should be either 384*fs or 512*fs. 124 * If MCLK is used, the SAIF clk ratio need to match mclk ratio. 125 * For 32x mclk, set saif clk as 512*fs. 126 * For 48x mclk, set saif clk as 384*fs. 127 * 128 * If MCLK is not used, we just set saif clk to 512*fs. 129 */ 130 clk_prepare_enable(master_saif->clk); 131 132 if (master_saif->mclk_in_use) { 133 if (mclk % 32 == 0) { 134 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 135 ret = clk_set_rate(master_saif->clk, 512 * rate); 136 } else if (mclk % 48 == 0) { 137 scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE; 138 ret = clk_set_rate(master_saif->clk, 384 * rate); 139 } else { 140 /* SAIF MCLK should be either 32x or 48x */ 141 clk_disable_unprepare(master_saif->clk); 142 return -EINVAL; 143 } 144 } else { 145 ret = clk_set_rate(master_saif->clk, 512 * rate); 146 scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE; 147 } 148 149 clk_disable_unprepare(master_saif->clk); 150 151 if (ret) 152 return ret; 153 154 master_saif->cur_rate = rate; 155 156 if (!master_saif->mclk_in_use) { 157 __raw_writel(scr, master_saif->base + SAIF_CTRL); 158 return 0; 159 } 160 161 /* 162 * Program the over-sample rate for MCLK output 163 * 164 * The available MCLK range is 32x, 48x... 512x. The rate 165 * could be from 8kHz to 192kH. 166 */ 167 switch (mclk / rate) { 168 case 32: 169 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(4); 170 break; 171 case 64: 172 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 173 break; 174 case 128: 175 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 176 break; 177 case 256: 178 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 179 break; 180 case 512: 181 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 182 break; 183 case 48: 184 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(3); 185 break; 186 case 96: 187 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(2); 188 break; 189 case 192: 190 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(1); 191 break; 192 case 384: 193 scr |= BF_SAIF_CTRL_BITCLK_MULT_RATE(0); 194 break; 195 default: 196 return -EINVAL; 197 } 198 199 __raw_writel(scr, master_saif->base + SAIF_CTRL); 200 201 return 0; 202 } 203 204 /* 205 * Put and disable MCLK. 206 */ 207 int mxs_saif_put_mclk(unsigned int saif_id) 208 { 209 struct mxs_saif *saif = mxs_saif[saif_id]; 210 u32 stat; 211 212 if (!saif) 213 return -EINVAL; 214 215 stat = __raw_readl(saif->base + SAIF_STAT); 216 if (stat & BM_SAIF_STAT_BUSY) { 217 dev_err(saif->dev, "error: busy\n"); 218 return -EBUSY; 219 } 220 221 clk_disable_unprepare(saif->clk); 222 223 /* disable MCLK output */ 224 __raw_writel(BM_SAIF_CTRL_CLKGATE, 225 saif->base + SAIF_CTRL + MXS_SET_ADDR); 226 __raw_writel(BM_SAIF_CTRL_RUN, 227 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 228 229 saif->mclk_in_use = 0; 230 return 0; 231 } 232 233 /* 234 * Get MCLK and set clock rate, then enable it 235 * 236 * This interface is used for codecs who are using MCLK provided 237 * by saif. 238 */ 239 int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk, 240 unsigned int rate) 241 { 242 struct mxs_saif *saif = mxs_saif[saif_id]; 243 u32 stat; 244 int ret; 245 struct mxs_saif *master_saif; 246 247 if (!saif) 248 return -EINVAL; 249 250 /* Clear Reset */ 251 __raw_writel(BM_SAIF_CTRL_SFTRST, 252 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 253 254 /* FIXME: need clear clk gate for register r/w */ 255 __raw_writel(BM_SAIF_CTRL_CLKGATE, 256 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 257 258 master_saif = mxs_saif_get_master(saif); 259 if (saif != master_saif) { 260 dev_err(saif->dev, "can not get mclk from a non-master saif\n"); 261 return -EINVAL; 262 } 263 264 stat = __raw_readl(saif->base + SAIF_STAT); 265 if (stat & BM_SAIF_STAT_BUSY) { 266 dev_err(saif->dev, "error: busy\n"); 267 return -EBUSY; 268 } 269 270 saif->mclk_in_use = 1; 271 ret = mxs_saif_set_clk(saif, mclk, rate); 272 if (ret) 273 return ret; 274 275 ret = clk_prepare_enable(saif->clk); 276 if (ret) 277 return ret; 278 279 /* enable MCLK output */ 280 __raw_writel(BM_SAIF_CTRL_RUN, 281 saif->base + SAIF_CTRL + MXS_SET_ADDR); 282 283 return 0; 284 } 285 286 /* 287 * SAIF DAI format configuration. 288 * Should only be called when port is inactive. 289 */ 290 static int mxs_saif_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt) 291 { 292 u32 scr, stat; 293 u32 scr0; 294 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 295 296 stat = __raw_readl(saif->base + SAIF_STAT); 297 if (stat & BM_SAIF_STAT_BUSY) { 298 dev_err(cpu_dai->dev, "error: busy\n"); 299 return -EBUSY; 300 } 301 302 scr0 = __raw_readl(saif->base + SAIF_CTRL); 303 scr0 = scr0 & ~BM_SAIF_CTRL_BITCLK_EDGE & ~BM_SAIF_CTRL_LRCLK_POLARITY \ 304 & ~BM_SAIF_CTRL_JUSTIFY & ~BM_SAIF_CTRL_DELAY; 305 scr = 0; 306 307 /* DAI mode */ 308 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 309 case SND_SOC_DAIFMT_I2S: 310 /* data frame low 1clk before data */ 311 scr |= BM_SAIF_CTRL_DELAY; 312 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 313 break; 314 case SND_SOC_DAIFMT_LEFT_J: 315 /* data frame high with data */ 316 scr &= ~BM_SAIF_CTRL_DELAY; 317 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 318 scr &= ~BM_SAIF_CTRL_JUSTIFY; 319 break; 320 default: 321 return -EINVAL; 322 } 323 324 /* DAI clock inversion */ 325 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 326 case SND_SOC_DAIFMT_IB_IF: 327 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 328 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 329 break; 330 case SND_SOC_DAIFMT_IB_NF: 331 scr |= BM_SAIF_CTRL_BITCLK_EDGE; 332 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 333 break; 334 case SND_SOC_DAIFMT_NB_IF: 335 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 336 scr |= BM_SAIF_CTRL_LRCLK_POLARITY; 337 break; 338 case SND_SOC_DAIFMT_NB_NF: 339 scr &= ~BM_SAIF_CTRL_BITCLK_EDGE; 340 scr &= ~BM_SAIF_CTRL_LRCLK_POLARITY; 341 break; 342 } 343 344 /* 345 * Note: We simply just support master mode since SAIF TX can only 346 * work as master. 347 * Here the master is relative to codec side. 348 * Saif internally could be slave when working on EXTMASTER mode. 349 * We just hide this to machine driver. 350 */ 351 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 352 case SND_SOC_DAIFMT_CBS_CFS: 353 if (saif->id == saif->master_id) 354 scr &= ~BM_SAIF_CTRL_SLAVE_MODE; 355 else 356 scr |= BM_SAIF_CTRL_SLAVE_MODE; 357 358 __raw_writel(scr | scr0, saif->base + SAIF_CTRL); 359 break; 360 default: 361 return -EINVAL; 362 } 363 364 return 0; 365 } 366 367 static int mxs_saif_startup(struct snd_pcm_substream *substream, 368 struct snd_soc_dai *cpu_dai) 369 { 370 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 371 snd_soc_dai_set_dma_data(cpu_dai, substream, &saif->dma_param); 372 373 /* clear error status to 0 for each re-open */ 374 saif->fifo_underrun = 0; 375 saif->fifo_overrun = 0; 376 377 /* Clear Reset for normal operations */ 378 __raw_writel(BM_SAIF_CTRL_SFTRST, 379 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 380 381 /* clear clock gate */ 382 __raw_writel(BM_SAIF_CTRL_CLKGATE, 383 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 384 385 return 0; 386 } 387 388 /* 389 * Should only be called when port is inactive. 390 * although can be called multiple times by upper layers. 391 */ 392 static int mxs_saif_hw_params(struct snd_pcm_substream *substream, 393 struct snd_pcm_hw_params *params, 394 struct snd_soc_dai *cpu_dai) 395 { 396 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 397 struct mxs_saif *master_saif; 398 u32 scr, stat; 399 int ret; 400 401 master_saif = mxs_saif_get_master(saif); 402 if (!master_saif) 403 return -EINVAL; 404 405 /* mclk should already be set */ 406 if (!saif->mclk && saif->mclk_in_use) { 407 dev_err(cpu_dai->dev, "set mclk first\n"); 408 return -EINVAL; 409 } 410 411 stat = __raw_readl(saif->base + SAIF_STAT); 412 if (stat & BM_SAIF_STAT_BUSY) { 413 dev_err(cpu_dai->dev, "error: busy\n"); 414 return -EBUSY; 415 } 416 417 /* 418 * Set saif clk based on sample rate. 419 * If mclk is used, we also set mclk, if not, saif->mclk is 420 * default 0, means not used. 421 */ 422 ret = mxs_saif_set_clk(saif, saif->mclk, params_rate(params)); 423 if (ret) { 424 dev_err(cpu_dai->dev, "unable to get proper clk\n"); 425 return ret; 426 } 427 428 /* prepare clk in hw_param, enable in trigger */ 429 clk_prepare(saif->clk); 430 if (saif != master_saif) { 431 /* 432 * Set an initial clock rate for the saif internal logic to work 433 * properly. This is important when working in EXTMASTER mode 434 * that uses the other saif's BITCLK&LRCLK but it still needs a 435 * basic clock which should be fast enough for the internal 436 * logic. 437 */ 438 clk_enable(saif->clk); 439 ret = clk_set_rate(saif->clk, 24000000); 440 clk_disable(saif->clk); 441 if (ret) 442 return ret; 443 444 clk_prepare(master_saif->clk); 445 } 446 447 scr = __raw_readl(saif->base + SAIF_CTRL); 448 449 scr &= ~BM_SAIF_CTRL_WORD_LENGTH; 450 scr &= ~BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 451 switch (params_format(params)) { 452 case SNDRV_PCM_FORMAT_S16_LE: 453 scr |= BF_SAIF_CTRL_WORD_LENGTH(0); 454 break; 455 case SNDRV_PCM_FORMAT_S20_3LE: 456 scr |= BF_SAIF_CTRL_WORD_LENGTH(4); 457 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 458 break; 459 case SNDRV_PCM_FORMAT_S24_LE: 460 scr |= BF_SAIF_CTRL_WORD_LENGTH(8); 461 scr |= BM_SAIF_CTRL_BITCLK_48XFS_ENABLE; 462 break; 463 default: 464 return -EINVAL; 465 } 466 467 /* Tx/Rx config */ 468 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 469 /* enable TX mode */ 470 scr &= ~BM_SAIF_CTRL_READ_MODE; 471 } else { 472 /* enable RX mode */ 473 scr |= BM_SAIF_CTRL_READ_MODE; 474 } 475 476 __raw_writel(scr, saif->base + SAIF_CTRL); 477 return 0; 478 } 479 480 static int mxs_saif_prepare(struct snd_pcm_substream *substream, 481 struct snd_soc_dai *cpu_dai) 482 { 483 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 484 485 /* enable FIFO error irqs */ 486 __raw_writel(BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN, 487 saif->base + SAIF_CTRL + MXS_SET_ADDR); 488 489 return 0; 490 } 491 492 static int mxs_saif_trigger(struct snd_pcm_substream *substream, int cmd, 493 struct snd_soc_dai *cpu_dai) 494 { 495 struct mxs_saif *saif = snd_soc_dai_get_drvdata(cpu_dai); 496 struct mxs_saif *master_saif; 497 u32 delay; 498 499 master_saif = mxs_saif_get_master(saif); 500 if (!master_saif) 501 return -EINVAL; 502 503 switch (cmd) { 504 case SNDRV_PCM_TRIGGER_START: 505 case SNDRV_PCM_TRIGGER_RESUME: 506 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 507 dev_dbg(cpu_dai->dev, "start\n"); 508 509 clk_enable(master_saif->clk); 510 if (!master_saif->mclk_in_use) 511 __raw_writel(BM_SAIF_CTRL_RUN, 512 master_saif->base + SAIF_CTRL + MXS_SET_ADDR); 513 514 /* 515 * If the saif's master is not himself, we also need to enable 516 * itself clk for its internal basic logic to work. 517 */ 518 if (saif != master_saif) { 519 clk_enable(saif->clk); 520 __raw_writel(BM_SAIF_CTRL_RUN, 521 saif->base + SAIF_CTRL + MXS_SET_ADDR); 522 } 523 524 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 525 /* 526 * write data to saif data register to trigger 527 * the transfer. 528 * For 24-bit format the 32-bit FIFO register stores 529 * only one channel, so we need to write twice. 530 * This is also safe for the other non 24-bit formats. 531 */ 532 __raw_writel(0, saif->base + SAIF_DATA); 533 __raw_writel(0, saif->base + SAIF_DATA); 534 } else { 535 /* 536 * read data from saif data register to trigger 537 * the receive. 538 * For 24-bit format the 32-bit FIFO register stores 539 * only one channel, so we need to read twice. 540 * This is also safe for the other non 24-bit formats. 541 */ 542 __raw_readl(saif->base + SAIF_DATA); 543 __raw_readl(saif->base + SAIF_DATA); 544 } 545 546 master_saif->ongoing = 1; 547 548 dev_dbg(saif->dev, "CTRL 0x%x STAT 0x%x\n", 549 __raw_readl(saif->base + SAIF_CTRL), 550 __raw_readl(saif->base + SAIF_STAT)); 551 552 dev_dbg(master_saif->dev, "CTRL 0x%x STAT 0x%x\n", 553 __raw_readl(master_saif->base + SAIF_CTRL), 554 __raw_readl(master_saif->base + SAIF_STAT)); 555 break; 556 case SNDRV_PCM_TRIGGER_SUSPEND: 557 case SNDRV_PCM_TRIGGER_STOP: 558 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 559 dev_dbg(cpu_dai->dev, "stop\n"); 560 561 /* wait a while for the current sample to complete */ 562 delay = USEC_PER_SEC / master_saif->cur_rate; 563 564 if (!master_saif->mclk_in_use) { 565 __raw_writel(BM_SAIF_CTRL_RUN, 566 master_saif->base + SAIF_CTRL + MXS_CLR_ADDR); 567 udelay(delay); 568 } 569 clk_disable(master_saif->clk); 570 571 if (saif != master_saif) { 572 __raw_writel(BM_SAIF_CTRL_RUN, 573 saif->base + SAIF_CTRL + MXS_CLR_ADDR); 574 udelay(delay); 575 clk_disable(saif->clk); 576 } 577 578 master_saif->ongoing = 0; 579 580 break; 581 default: 582 return -EINVAL; 583 } 584 585 return 0; 586 } 587 588 #define MXS_SAIF_RATES SNDRV_PCM_RATE_8000_192000 589 #define MXS_SAIF_FORMATS \ 590 (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ 591 SNDRV_PCM_FMTBIT_S24_LE) 592 593 static const struct snd_soc_dai_ops mxs_saif_dai_ops = { 594 .startup = mxs_saif_startup, 595 .trigger = mxs_saif_trigger, 596 .prepare = mxs_saif_prepare, 597 .hw_params = mxs_saif_hw_params, 598 .set_sysclk = mxs_saif_set_dai_sysclk, 599 .set_fmt = mxs_saif_set_dai_fmt, 600 }; 601 602 static int mxs_saif_dai_probe(struct snd_soc_dai *dai) 603 { 604 struct mxs_saif *saif = dev_get_drvdata(dai->dev); 605 606 snd_soc_dai_set_drvdata(dai, saif); 607 608 return 0; 609 } 610 611 static struct snd_soc_dai_driver mxs_saif_dai = { 612 .name = "mxs-saif", 613 .probe = mxs_saif_dai_probe, 614 .playback = { 615 .channels_min = 2, 616 .channels_max = 2, 617 .rates = MXS_SAIF_RATES, 618 .formats = MXS_SAIF_FORMATS, 619 }, 620 .capture = { 621 .channels_min = 2, 622 .channels_max = 2, 623 .rates = MXS_SAIF_RATES, 624 .formats = MXS_SAIF_FORMATS, 625 }, 626 .ops = &mxs_saif_dai_ops, 627 }; 628 629 static irqreturn_t mxs_saif_irq(int irq, void *dev_id) 630 { 631 struct mxs_saif *saif = dev_id; 632 unsigned int stat; 633 634 stat = __raw_readl(saif->base + SAIF_STAT); 635 if (!(stat & (BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ | 636 BM_SAIF_STAT_FIFO_OVERFLOW_IRQ))) 637 return IRQ_NONE; 638 639 if (stat & BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ) { 640 dev_dbg(saif->dev, "underrun!!! %d\n", ++saif->fifo_underrun); 641 __raw_writel(BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ, 642 saif->base + SAIF_STAT + MXS_CLR_ADDR); 643 } 644 645 if (stat & BM_SAIF_STAT_FIFO_OVERFLOW_IRQ) { 646 dev_dbg(saif->dev, "overrun!!! %d\n", ++saif->fifo_overrun); 647 __raw_writel(BM_SAIF_STAT_FIFO_OVERFLOW_IRQ, 648 saif->base + SAIF_STAT + MXS_CLR_ADDR); 649 } 650 651 dev_dbg(saif->dev, "SAIF_CTRL %x SAIF_STAT %x\n", 652 __raw_readl(saif->base + SAIF_CTRL), 653 __raw_readl(saif->base + SAIF_STAT)); 654 655 return IRQ_HANDLED; 656 } 657 658 static int __devinit mxs_saif_probe(struct platform_device *pdev) 659 { 660 struct device_node *np = pdev->dev.of_node; 661 struct resource *iores, *dmares; 662 struct mxs_saif *saif; 663 struct mxs_saif_platform_data *pdata; 664 struct pinctrl *pinctrl; 665 int ret = 0; 666 667 668 if (!np && pdev->id >= ARRAY_SIZE(mxs_saif)) 669 return -EINVAL; 670 671 saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL); 672 if (!saif) 673 return -ENOMEM; 674 675 if (np) { 676 struct device_node *master; 677 saif->id = of_alias_get_id(np, "saif"); 678 if (saif->id < 0) 679 return saif->id; 680 /* 681 * If there is no "fsl,saif-master" phandle, it's a saif 682 * master. Otherwise, it's a slave and its phandle points 683 * to the master. 684 */ 685 master = of_parse_phandle(np, "fsl,saif-master", 0); 686 if (!master) { 687 saif->master_id = saif->id; 688 } else { 689 saif->master_id = of_alias_get_id(master, "saif"); 690 if (saif->master_id < 0) 691 return saif->master_id; 692 } 693 } else { 694 saif->id = pdev->id; 695 pdata = pdev->dev.platform_data; 696 if (pdata && !pdata->master_mode) 697 saif->master_id = pdata->master_id; 698 else 699 saif->master_id = saif->id; 700 } 701 702 if (saif->master_id < 0 || saif->master_id >= ARRAY_SIZE(mxs_saif)) { 703 dev_err(&pdev->dev, "get wrong master id\n"); 704 return -EINVAL; 705 } 706 707 mxs_saif[saif->id] = saif; 708 709 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 710 if (IS_ERR(pinctrl)) { 711 ret = PTR_ERR(pinctrl); 712 return ret; 713 } 714 715 saif->clk = devm_clk_get(&pdev->dev, NULL); 716 if (IS_ERR(saif->clk)) { 717 ret = PTR_ERR(saif->clk); 718 dev_err(&pdev->dev, "Cannot get the clock: %d\n", 719 ret); 720 return ret; 721 } 722 723 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 724 725 saif->base = devm_request_and_ioremap(&pdev->dev, iores); 726 if (!saif->base) { 727 dev_err(&pdev->dev, "ioremap failed\n"); 728 return -ENODEV; 729 } 730 731 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0); 732 if (!dmares) { 733 /* 734 * TODO: This is a temporary solution and should be changed 735 * to use generic DMA binding later when the helplers get in. 736 */ 737 ret = of_property_read_u32(np, "fsl,saif-dma-channel", 738 &saif->dma_param.chan_num); 739 if (ret) { 740 dev_err(&pdev->dev, "failed to get dma channel\n"); 741 return ret; 742 } 743 } else { 744 saif->dma_param.chan_num = dmares->start; 745 } 746 747 saif->irq = platform_get_irq(pdev, 0); 748 if (saif->irq < 0) { 749 ret = saif->irq; 750 dev_err(&pdev->dev, "failed to get irq resource: %d\n", 751 ret); 752 return ret; 753 } 754 755 saif->dev = &pdev->dev; 756 ret = devm_request_irq(&pdev->dev, saif->irq, mxs_saif_irq, 0, 757 "mxs-saif", saif); 758 if (ret) { 759 dev_err(&pdev->dev, "failed to request irq\n"); 760 return ret; 761 } 762 763 saif->dma_param.chan_irq = platform_get_irq(pdev, 1); 764 if (saif->dma_param.chan_irq < 0) { 765 ret = saif->dma_param.chan_irq; 766 dev_err(&pdev->dev, "failed to get dma irq resource: %d\n", 767 ret); 768 return ret; 769 } 770 771 platform_set_drvdata(pdev, saif); 772 773 ret = snd_soc_register_dai(&pdev->dev, &mxs_saif_dai); 774 if (ret) { 775 dev_err(&pdev->dev, "register DAI failed\n"); 776 return ret; 777 } 778 779 ret = mxs_pcm_platform_register(&pdev->dev); 780 if (ret) { 781 dev_err(&pdev->dev, "register PCM failed: %d\n", ret); 782 goto failed_pdev_alloc; 783 } 784 785 return 0; 786 787 failed_pdev_alloc: 788 snd_soc_unregister_dai(&pdev->dev); 789 790 return ret; 791 } 792 793 static int __devexit mxs_saif_remove(struct platform_device *pdev) 794 { 795 mxs_pcm_platform_unregister(&pdev->dev); 796 snd_soc_unregister_dai(&pdev->dev); 797 798 return 0; 799 } 800 801 static const struct of_device_id mxs_saif_dt_ids[] = { 802 { .compatible = "fsl,imx28-saif", }, 803 { /* sentinel */ } 804 }; 805 MODULE_DEVICE_TABLE(of, mxs_saif_dt_ids); 806 807 static struct platform_driver mxs_saif_driver = { 808 .probe = mxs_saif_probe, 809 .remove = __devexit_p(mxs_saif_remove), 810 811 .driver = { 812 .name = "mxs-saif", 813 .owner = THIS_MODULE, 814 .of_match_table = mxs_saif_dt_ids, 815 }, 816 }; 817 818 module_platform_driver(mxs_saif_driver); 819 820 MODULE_AUTHOR("Freescale Semiconductor, Inc."); 821 MODULE_DESCRIPTION("MXS ASoC SAIF driver"); 822 MODULE_LICENSE("GPL"); 823 MODULE_ALIAS("platform:mxs-saif"); 824