1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #ifndef _MESON_AIU_H 8 #define _MESON_AIU_H 9 10 struct clk; 11 struct clk_bulk_data; 12 struct device; 13 struct of_phandle_args; 14 struct snd_soc_component_driver; 15 struct snd_soc_dai; 16 struct snd_soc_dai_driver; 17 struct snd_soc_dai_ops; 18 19 enum aiu_clk_ids { 20 PCLK = 0, 21 AOCLK, 22 MCLK, 23 MIXER 24 }; 25 26 struct aiu_interface { 27 struct clk_bulk_data *clks; 28 unsigned int clk_num; 29 unsigned int irq; 30 }; 31 32 struct aiu { 33 struct clk *pclk; 34 struct clk *spdif_mclk; 35 struct aiu_interface i2s; 36 struct aiu_interface spdif; 37 }; 38 39 #define AIU_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \ 40 SNDRV_PCM_FMTBIT_S20_LE | \ 41 SNDRV_PCM_FMTBIT_S24_LE) 42 43 int aiu_of_xlate_dai_name(struct snd_soc_component *component, 44 struct of_phandle_args *args, 45 const char **dai_name, 46 unsigned int component_id); 47 48 int aiu_add_component(struct device *dev, 49 const struct snd_soc_component_driver *component_driver, 50 struct snd_soc_dai_driver *dai_drv, 51 int num_dai, 52 const char *debugfs_prefix); 53 54 int aiu_hdmi_ctrl_register_component(struct device *dev); 55 56 int aiu_fifo_i2s_dai_probe(struct snd_soc_dai *dai); 57 int aiu_fifo_spdif_dai_probe(struct snd_soc_dai *dai); 58 59 extern const struct snd_soc_dai_ops aiu_fifo_i2s_dai_ops; 60 extern const struct snd_soc_dai_ops aiu_fifo_spdif_dai_ops; 61 extern const struct snd_soc_dai_ops aiu_encoder_i2s_dai_ops; 62 extern const struct snd_soc_dai_ops aiu_encoder_spdif_dai_ops; 63 64 #define AIU_IEC958_BPF 0x000 65 #define AIU_958_MISC 0x010 66 #define AIU_IEC958_DCU_FF_CTRL 0x01c 67 #define AIU_958_CHSTAT_L0 0x020 68 #define AIU_958_CHSTAT_L1 0x024 69 #define AIU_958_CTRL 0x028 70 #define AIU_I2S_SOURCE_DESC 0x034 71 #define AIU_I2S_DAC_CFG 0x040 72 #define AIU_I2S_SYNC 0x044 73 #define AIU_I2S_MISC 0x048 74 #define AIU_RST_SOFT 0x054 75 #define AIU_CLK_CTRL 0x058 76 #define AIU_CLK_CTRL_MORE 0x064 77 #define AIU_CODEC_DAC_LRCLK_CTRL 0x0a0 78 #define AIU_HDMI_CLK_DATA_CTRL 0x0a8 79 #define AIU_ACODEC_CTRL 0x0b0 80 #define AIU_958_CHSTAT_R0 0x0c0 81 #define AIU_958_CHSTAT_R1 0x0c4 82 #define AIU_MEM_I2S_START 0x180 83 #define AIU_MEM_I2S_MASKS 0x18c 84 #define AIU_MEM_I2S_CONTROL 0x190 85 #define AIU_MEM_IEC958_START 0x194 86 #define AIU_MEM_IEC958_CONTROL 0x1a4 87 #define AIU_MEM_I2S_BUF_CNTL 0x1d8 88 #define AIU_MEM_IEC958_BUF_CNTL 0x1fc 89 90 #endif /* _MESON_AIU_H */ 91