1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek 8365 ALSA SoC AFE platform driver 4 * 5 * Copyright (c) 2024 MediaTek Inc. 6 * Authors: Jia Zeng <jia.zeng@mediatek.com> 7 * Alexandre Mergnat <amergnat@baylibre.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/pm_runtime.h> 16 #include <sound/soc.h> 17 #include <sound/pcm_params.h> 18 #include "mt8365-afe-common.h" 19 #include "mt8365-afe-clk.h" 20 #include "mt8365-reg.h" 21 #include "../common/mtk-base-afe.h" 22 #include "../common/mtk-afe-platform-driver.h" 23 #include "../common/mtk-afe-fe-dai.h" 24 25 #define AFE_BASE_END_OFFSET 8 26 27 static unsigned int mCM2Input; 28 29 static const unsigned int mt8365_afe_backup_list[] = { 30 AUDIO_TOP_CON0, 31 AFE_CONN0, 32 AFE_CONN1, 33 AFE_CONN3, 34 AFE_CONN4, 35 AFE_CONN5, 36 AFE_CONN6, 37 AFE_CONN7, 38 AFE_CONN8, 39 AFE_CONN9, 40 AFE_CONN10, 41 AFE_CONN11, 42 AFE_CONN12, 43 AFE_CONN13, 44 AFE_CONN14, 45 AFE_CONN15, 46 AFE_CONN16, 47 AFE_CONN17, 48 AFE_CONN18, 49 AFE_CONN19, 50 AFE_CONN20, 51 AFE_CONN21, 52 AFE_CONN26, 53 AFE_CONN27, 54 AFE_CONN28, 55 AFE_CONN29, 56 AFE_CONN30, 57 AFE_CONN31, 58 AFE_CONN32, 59 AFE_CONN33, 60 AFE_CONN34, 61 AFE_CONN35, 62 AFE_CONN36, 63 AFE_CONN_24BIT, 64 AFE_CONN_24BIT_1, 65 AFE_DAC_CON0, 66 AFE_DAC_CON1, 67 AFE_DL1_BASE, 68 AFE_DL1_END, 69 AFE_DL2_BASE, 70 AFE_DL2_END, 71 AFE_VUL_BASE, 72 AFE_VUL_END, 73 AFE_AWB_BASE, 74 AFE_AWB_END, 75 AFE_VUL3_BASE, 76 AFE_VUL3_END, 77 AFE_HDMI_OUT_BASE, 78 AFE_HDMI_OUT_END, 79 AFE_HDMI_IN_2CH_BASE, 80 AFE_HDMI_IN_2CH_END, 81 AFE_ADDA_UL_DL_CON0, 82 AFE_ADDA_DL_SRC2_CON0, 83 AFE_ADDA_DL_SRC2_CON1, 84 AFE_I2S_CON, 85 AFE_I2S_CON1, 86 AFE_I2S_CON2, 87 AFE_I2S_CON3, 88 AFE_ADDA_UL_SRC_CON0, 89 AFE_AUD_PAD_TOP, 90 AFE_HD_ENGEN_ENABLE, 91 }; 92 93 static const struct snd_pcm_hardware mt8365_afe_hardware = { 94 .info = (SNDRV_PCM_INFO_MMAP | 95 SNDRV_PCM_INFO_INTERLEAVED | 96 SNDRV_PCM_INFO_MMAP_VALID), 97 .buffer_bytes_max = 256 * 1024, 98 .period_bytes_min = 512, 99 .period_bytes_max = 128 * 1024, 100 .periods_min = 2, 101 .periods_max = 256, 102 .fifo_size = 0, 103 }; 104 105 struct mt8365_afe_rate { 106 unsigned int rate; 107 unsigned int reg_val; 108 }; 109 110 static const struct mt8365_afe_rate mt8365_afe_fs_rates[] = { 111 { .rate = 8000, .reg_val = MT8365_FS_8K }, 112 { .rate = 11025, .reg_val = MT8365_FS_11D025K }, 113 { .rate = 12000, .reg_val = MT8365_FS_12K }, 114 { .rate = 16000, .reg_val = MT8365_FS_16K }, 115 { .rate = 22050, .reg_val = MT8365_FS_22D05K }, 116 { .rate = 24000, .reg_val = MT8365_FS_24K }, 117 { .rate = 32000, .reg_val = MT8365_FS_32K }, 118 { .rate = 44100, .reg_val = MT8365_FS_44D1K }, 119 { .rate = 48000, .reg_val = MT8365_FS_48K }, 120 { .rate = 88200, .reg_val = MT8365_FS_88D2K }, 121 { .rate = 96000, .reg_val = MT8365_FS_96K }, 122 { .rate = 176400, .reg_val = MT8365_FS_176D4K }, 123 { .rate = 192000, .reg_val = MT8365_FS_192K }, 124 }; 125 126 int mt8365_afe_fs_timing(unsigned int rate) 127 { 128 int i; 129 130 for (i = 0; i < ARRAY_SIZE(mt8365_afe_fs_rates); i++) 131 if (mt8365_afe_fs_rates[i].rate == rate) 132 return mt8365_afe_fs_rates[i].reg_val; 133 134 return -EINVAL; 135 } 136 137 bool mt8365_afe_rate_supported(unsigned int rate, unsigned int id) 138 { 139 switch (id) { 140 case MT8365_AFE_IO_TDM_IN: 141 if (rate >= 8000 && rate <= 192000) 142 return true; 143 break; 144 case MT8365_AFE_IO_DMIC: 145 if (rate >= 8000 && rate <= 48000) 146 return true; 147 break; 148 default: 149 break; 150 } 151 152 return false; 153 } 154 155 bool mt8365_afe_channel_supported(unsigned int channel, unsigned int id) 156 { 157 switch (id) { 158 case MT8365_AFE_IO_TDM_IN: 159 if (channel >= 1 && channel <= 8) 160 return true; 161 break; 162 case MT8365_AFE_IO_DMIC: 163 if (channel >= 1 && channel <= 8) 164 return true; 165 break; 166 default: 167 break; 168 } 169 170 return false; 171 } 172 173 static bool mt8365_afe_clk_group_44k(int sample_rate) 174 { 175 if (sample_rate == 11025 || 176 sample_rate == 22050 || 177 sample_rate == 44100 || 178 sample_rate == 88200 || 179 sample_rate == 176400) 180 return true; 181 else 182 return false; 183 } 184 185 static bool mt8365_afe_clk_group_48k(int sample_rate) 186 { 187 return (!mt8365_afe_clk_group_44k(sample_rate)); 188 } 189 190 int mt8365_dai_set_priv(struct mtk_base_afe *afe, int id, 191 int priv_size, const void *priv_data) 192 { 193 struct mt8365_afe_private *afe_priv = afe->platform_priv; 194 void *temp_data; 195 196 temp_data = devm_kzalloc(afe->dev, priv_size, GFP_KERNEL); 197 if (!temp_data) 198 return -ENOMEM; 199 200 if (priv_data) 201 memcpy(temp_data, priv_data, priv_size); 202 203 afe_priv->dai_priv[id] = temp_data; 204 205 return 0; 206 } 207 208 static int mt8365_afe_irq_direction_enable(struct mtk_base_afe *afe, 209 int irq_id, int direction) 210 { 211 struct mtk_base_afe_irq *irq; 212 213 if (irq_id >= MT8365_AFE_IRQ_NUM) 214 return -1; 215 216 irq = &afe->irqs[irq_id]; 217 218 if (direction == MT8365_AFE_IRQ_DIR_MCU) { 219 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN, 220 (1 << irq->irq_data->irq_clr_shift), 221 0); 222 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 223 (1 << irq->irq_data->irq_clr_shift), 224 (1 << irq->irq_data->irq_clr_shift)); 225 } else if (direction == MT8365_AFE_IRQ_DIR_DSP) { 226 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN, 227 (1 << irq->irq_data->irq_clr_shift), 228 (1 << irq->irq_data->irq_clr_shift)); 229 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 230 (1 << irq->irq_data->irq_clr_shift), 231 0); 232 } else { 233 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_DSP_EN, 234 (1 << irq->irq_data->irq_clr_shift), 235 (1 << irq->irq_data->irq_clr_shift)); 236 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 237 (1 << irq->irq_data->irq_clr_shift), 238 (1 << irq->irq_data->irq_clr_shift)); 239 } 240 return 0; 241 } 242 243 static int mt8365_memif_fs(struct snd_pcm_substream *substream, 244 unsigned int rate) 245 { 246 return mt8365_afe_fs_timing(rate); 247 } 248 249 static int mt8365_irq_fs(struct snd_pcm_substream *substream, 250 unsigned int rate) 251 { 252 return mt8365_memif_fs(substream, rate); 253 } 254 255 static const struct mt8365_cm_ctrl_reg cm_ctrl_reg[MT8365_CM_NUM] = { 256 [MT8365_CM1] = { 257 .con0 = AFE_CM1_CON0, 258 .con1 = AFE_CM1_CON1, 259 .con2 = AFE_CM1_CON2, 260 .con3 = AFE_CM1_CON3, 261 .con4 = AFE_CM1_CON4, 262 }, 263 [MT8365_CM2] = { 264 .con0 = AFE_CM2_CON0, 265 .con1 = AFE_CM2_CON1, 266 .con2 = AFE_CM2_CON2, 267 .con3 = AFE_CM2_CON3, 268 .con4 = AFE_CM2_CON4, 269 } 270 }; 271 272 static int mt8365_afe_cm2_mux_conn(struct mtk_base_afe *afe) 273 { 274 struct mt8365_afe_private *afe_priv = afe->platform_priv; 275 unsigned int input = afe_priv->cm2_mux_input; 276 277 /* TDM_IN interconnect to CM2 */ 278 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 279 CM2_AFE_CM2_CONN_CFG1_MASK, 280 CM2_AFE_CM2_CONN_CFG1(TDM_IN_CH0)); 281 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 282 CM2_AFE_CM2_CONN_CFG2_MASK, 283 CM2_AFE_CM2_CONN_CFG2(TDM_IN_CH1)); 284 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 285 CM2_AFE_CM2_CONN_CFG3_MASK, 286 CM2_AFE_CM2_CONN_CFG3(TDM_IN_CH2)); 287 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 288 CM2_AFE_CM2_CONN_CFG4_MASK, 289 CM2_AFE_CM2_CONN_CFG4(TDM_IN_CH3)); 290 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 291 CM2_AFE_CM2_CONN_CFG5_MASK, 292 CM2_AFE_CM2_CONN_CFG5(TDM_IN_CH4)); 293 regmap_update_bits(afe->regmap, AFE_CM2_CONN0, 294 CM2_AFE_CM2_CONN_CFG6_MASK, 295 CM2_AFE_CM2_CONN_CFG6(TDM_IN_CH5)); 296 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 297 CM2_AFE_CM2_CONN_CFG7_MASK, 298 CM2_AFE_CM2_CONN_CFG7(TDM_IN_CH6)); 299 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 300 CM2_AFE_CM2_CONN_CFG8_MASK, 301 CM2_AFE_CM2_CONN_CFG8(TDM_IN_CH7)); 302 303 /* ref data interconnect to CM2 */ 304 if (input == MT8365_FROM_GASRC1) { 305 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 306 CM2_AFE_CM2_CONN_CFG9_MASK, 307 CM2_AFE_CM2_CONN_CFG9(GENERAL1_ASRC_OUT_LCH)); 308 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 309 CM2_AFE_CM2_CONN_CFG10_MASK, 310 CM2_AFE_CM2_CONN_CFG10(GENERAL1_ASRC_OUT_RCH)); 311 } else if (input == MT8365_FROM_GASRC2) { 312 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 313 CM2_AFE_CM2_CONN_CFG9_MASK, 314 CM2_AFE_CM2_CONN_CFG9(GENERAL2_ASRC_OUT_LCH)); 315 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 316 CM2_AFE_CM2_CONN_CFG10_MASK, 317 CM2_AFE_CM2_CONN_CFG10(GENERAL2_ASRC_OUT_RCH)); 318 } else if (input == MT8365_FROM_TDM_ASRC) { 319 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 320 CM2_AFE_CM2_CONN_CFG9_MASK, 321 CM2_AFE_CM2_CONN_CFG9(TDM_OUT_ASRC_CH0)); 322 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 323 CM2_AFE_CM2_CONN_CFG10_MASK, 324 CM2_AFE_CM2_CONN_CFG10(TDM_OUT_ASRC_CH1)); 325 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 326 CM2_AFE_CM2_CONN_CFG11_MASK, 327 CM2_AFE_CM2_CONN_CFG11(TDM_OUT_ASRC_CH2)); 328 regmap_update_bits(afe->regmap, AFE_CM2_CONN1, 329 CM2_AFE_CM2_CONN_CFG12_MASK, 330 CM2_AFE_CM2_CONN_CFG12(TDM_OUT_ASRC_CH3)); 331 regmap_update_bits(afe->regmap, AFE_CM2_CONN2, 332 CM2_AFE_CM2_CONN_CFG13_MASK, 333 CM2_AFE_CM2_CONN_CFG13(TDM_OUT_ASRC_CH4)); 334 regmap_update_bits(afe->regmap, AFE_CM2_CONN2, 335 CM2_AFE_CM2_CONN_CFG14_MASK, 336 CM2_AFE_CM2_CONN_CFG14(TDM_OUT_ASRC_CH5)); 337 regmap_update_bits(afe->regmap, AFE_CM2_CONN2, 338 CM2_AFE_CM2_CONN_CFG15_MASK, 339 CM2_AFE_CM2_CONN_CFG15(TDM_OUT_ASRC_CH6)); 340 regmap_update_bits(afe->regmap, AFE_CM2_CONN2, 341 CM2_AFE_CM2_CONN_CFG16_MASK, 342 CM2_AFE_CM2_CONN_CFG16(TDM_OUT_ASRC_CH7)); 343 } else { 344 dev_err(afe->dev, "%s wrong CM2 input %d\n", __func__, input); 345 return -1; 346 } 347 348 return 0; 349 } 350 351 static int mt8365_afe_get_cm_update_cnt(struct mtk_base_afe *afe, 352 enum mt8365_cm_num cmNum, 353 unsigned int rate, unsigned int channel) 354 { 355 unsigned int total_cnt, div_cnt, ch_pair, best_cnt; 356 unsigned int ch_update_cnt[MT8365_CM_UPDATA_CNT_SET]; 357 int i; 358 359 /* calculate cm update cnt 360 * total_cnt = clk / fs, clk is 26m or 24m or 22m 361 * div_cnt = total_cnt / ch_pair, max ch 16ch ,2ch is a set 362 * best_cnt < div_cnt ,we set best_cnt = div_cnt -10 363 * ch01 = best_cnt, ch23 = 2* ch01_up_cnt 364 * ch45 = 3* ch01_up_cnt ...ch1415 = 8* ch01_up_cnt 365 */ 366 367 if (cmNum == MT8365_CM1) { 368 total_cnt = MT8365_CLK_26M / rate; 369 } else if (cmNum == MT8365_CM2) { 370 if (mt8365_afe_clk_group_48k(rate)) 371 total_cnt = MT8365_CLK_24M / rate; 372 else 373 total_cnt = MT8365_CLK_22M / rate; 374 } else { 375 return -1; 376 } 377 378 if (channel % 2) 379 ch_pair = (channel / 2) + 1; 380 else 381 ch_pair = channel / 2; 382 383 div_cnt = total_cnt / ch_pair; 384 best_cnt = div_cnt - 10; 385 386 if (best_cnt <= 0) 387 return -1; 388 389 for (i = 0; i < ch_pair; i++) 390 ch_update_cnt[i] = (i + 1) * best_cnt; 391 392 switch (channel) { 393 case 16: 394 fallthrough; 395 case 15: 396 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4, 397 CM_AFE_CM_UPDATE_CNT2_MASK, 398 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[7])); 399 fallthrough; 400 case 14: 401 fallthrough; 402 case 13: 403 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con4, 404 CM_AFE_CM_UPDATE_CNT1_MASK, 405 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[6])); 406 fallthrough; 407 case 12: 408 fallthrough; 409 case 11: 410 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3, 411 CM_AFE_CM_UPDATE_CNT2_MASK, 412 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[5])); 413 fallthrough; 414 case 10: 415 fallthrough; 416 case 9: 417 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con3, 418 CM_AFE_CM_UPDATE_CNT1_MASK, 419 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[4])); 420 fallthrough; 421 case 8: 422 fallthrough; 423 case 7: 424 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2, 425 CM_AFE_CM_UPDATE_CNT2_MASK, 426 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[3])); 427 fallthrough; 428 case 6: 429 fallthrough; 430 case 5: 431 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con2, 432 CM_AFE_CM_UPDATE_CNT1_MASK, 433 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[2])); 434 fallthrough; 435 case 4: 436 fallthrough; 437 case 3: 438 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1, 439 CM_AFE_CM_UPDATE_CNT2_MASK, 440 CM_AFE_CM_UPDATE_CNT2(ch_update_cnt[1])); 441 fallthrough; 442 case 2: 443 fallthrough; 444 case 1: 445 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con1, 446 CM_AFE_CM_UPDATE_CNT1_MASK, 447 CM_AFE_CM_UPDATE_CNT1(ch_update_cnt[0])); 448 break; 449 default: 450 return -1; 451 } 452 453 return 0; 454 } 455 456 static int mt8365_afe_configure_cm(struct mtk_base_afe *afe, 457 enum mt8365_cm_num cmNum, 458 unsigned int channels, 459 unsigned int rate) 460 { 461 unsigned int val, mask; 462 unsigned int fs = mt8365_afe_fs_timing(rate); 463 464 val = FIELD_PREP(CM_AFE_CM_CH_NUM_MASK, (channels - 1)) | 465 FIELD_PREP(CM_AFE_CM_START_DATA_MASK, 0); 466 467 mask = CM_AFE_CM_CH_NUM_MASK | 468 CM_AFE_CM_START_DATA_MASK; 469 470 if (cmNum == MT8365_CM1) { 471 val |= FIELD_PREP(CM_AFE_CM1_IN_MODE_MASK, fs); 472 473 mask |= CM_AFE_CM1_VUL_SEL | 474 CM_AFE_CM1_IN_MODE_MASK; 475 } else if (cmNum == MT8365_CM2) { 476 if (mt8365_afe_clk_group_48k(rate)) 477 val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 0); 478 else 479 val |= FIELD_PREP(CM_AFE_CM2_CLK_SEL, 1); 480 481 val |= FIELD_PREP(CM_AFE_CM2_TDM_SEL, 1); 482 483 mask |= CM_AFE_CM2_TDM_SEL | 484 CM_AFE_CM1_IN_MODE_MASK | 485 CM_AFE_CM2_CLK_SEL; 486 487 mt8365_afe_cm2_mux_conn(afe); 488 } else { 489 return -1; 490 } 491 492 regmap_update_bits(afe->regmap, cm_ctrl_reg[cmNum].con0, mask, val); 493 494 mt8365_afe_get_cm_update_cnt(afe, cmNum, rate, channels); 495 496 return 0; 497 } 498 499 static int mt8365_afe_fe_startup(struct snd_pcm_substream *substream, 500 struct snd_soc_dai *dai) 501 { 502 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 503 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 504 struct snd_pcm_runtime *runtime = substream->runtime; 505 int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id; 506 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 507 int ret; 508 509 memif->substream = substream; 510 511 snd_pcm_hw_constraint_step(substream->runtime, 0, 512 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16); 513 514 snd_soc_set_runtime_hwparams(substream, afe->mtk_afe_hardware); 515 516 ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); 517 if (ret < 0) 518 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); 519 520 mt8365_afe_enable_main_clk(afe); 521 return ret; 522 } 523 524 static void mt8365_afe_fe_shutdown(struct snd_pcm_substream *substream, 525 struct snd_soc_dai *dai) 526 { 527 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 528 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 529 int memif_num = snd_soc_rtd_to_cpu(rtd, 0)->id; 530 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 531 532 memif->substream = NULL; 533 534 mt8365_afe_disable_main_clk(afe); 535 } 536 537 static int mt8365_afe_fe_hw_params(struct snd_pcm_substream *substream, 538 struct snd_pcm_hw_params *params, 539 struct snd_soc_dai *dai) 540 { 541 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 542 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 543 struct mt8365_afe_private *afe_priv = afe->platform_priv; 544 struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data; 545 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id; 546 struct mtk_base_afe_memif *memif = &afe->memif[dai_id]; 547 struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id]; 548 size_t request_size = params_buffer_bytes(params); 549 unsigned int channels = params_channels(params); 550 unsigned int rate = params_rate(params); 551 unsigned int base_end_offset = 8; 552 int ret, fs; 553 554 dev_info(afe->dev, "%s %s period = %d rate = %d channels = %d\n", 555 __func__, memif->data->name, params_period_size(params), 556 rate, channels); 557 558 if (dai_id == MT8365_AFE_MEMIF_VUL2) { 559 if (!ctrl_data->bypass_cm1) 560 /* configure cm1 */ 561 mt8365_afe_configure_cm(afe, MT8365_CM1, 562 channels, rate); 563 else 564 regmap_update_bits(afe->regmap, AFE_CM1_CON0, 565 CM_AFE_CM1_VUL_SEL, 566 CM_AFE_CM1_VUL_SEL); 567 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN) { 568 if (!ctrl_data->bypass_cm2) 569 /* configure cm2 */ 570 mt8365_afe_configure_cm(afe, MT8365_CM2, 571 channels, rate); 572 else 573 regmap_update_bits(afe->regmap, AFE_CM2_CON0, 574 CM_AFE_CM2_TDM_SEL, 575 ~CM_AFE_CM2_TDM_SEL); 576 577 base_end_offset = 4; 578 } 579 580 if (request_size > fe_data->sram_size) { 581 ret = snd_pcm_lib_malloc_pages(substream, request_size); 582 if (ret < 0) { 583 dev_err(afe->dev, 584 "%s %s malloc pages %zu bytes failed %d\n", 585 __func__, memif->data->name, request_size, ret); 586 return ret; 587 } 588 589 fe_data->use_sram = false; 590 591 mt8365_afe_emi_clk_on(afe); 592 } else { 593 struct snd_dma_buffer *dma_buf = &substream->dma_buffer; 594 595 dma_buf->dev.type = SNDRV_DMA_TYPE_DEV; 596 dma_buf->dev.dev = substream->pcm->card->dev; 597 dma_buf->area = (unsigned char *)fe_data->sram_vir_addr; 598 dma_buf->addr = fe_data->sram_phy_addr; 599 dma_buf->bytes = request_size; 600 snd_pcm_set_runtime_buffer(substream, dma_buf); 601 602 fe_data->use_sram = true; 603 } 604 605 memif->phys_buf_addr = lower_32_bits(substream->runtime->dma_addr); 606 memif->buffer_size = substream->runtime->dma_bytes; 607 608 /* start */ 609 regmap_write(afe->regmap, memif->data->reg_ofs_base, 610 memif->phys_buf_addr); 611 /* end */ 612 regmap_write(afe->regmap, 613 memif->data->reg_ofs_base + base_end_offset, 614 memif->phys_buf_addr + memif->buffer_size - 1); 615 616 /* set channel */ 617 if (memif->data->mono_shift >= 0) { 618 unsigned int mono = (params_channels(params) == 1) ? 1 : 0; 619 620 if (memif->data->mono_reg < 0) 621 dev_info(afe->dev, "%s mono_reg is NULL\n", __func__); 622 else 623 regmap_update_bits(afe->regmap, memif->data->mono_reg, 624 1 << memif->data->mono_shift, 625 mono << memif->data->mono_shift); 626 } 627 628 /* set rate */ 629 if (memif->data->fs_shift < 0) 630 return 0; 631 632 fs = afe->memif_fs(substream, params_rate(params)); 633 634 if (fs < 0) 635 return -EINVAL; 636 637 if (memif->data->fs_reg < 0) 638 dev_info(afe->dev, "%s fs_reg is NULL\n", __func__); 639 else 640 regmap_update_bits(afe->regmap, memif->data->fs_reg, 641 memif->data->fs_maskbit << memif->data->fs_shift, 642 fs << memif->data->fs_shift); 643 644 return 0; 645 } 646 647 static int mt8365_afe_fe_hw_free(struct snd_pcm_substream *substream, 648 struct snd_soc_dai *dai) 649 { 650 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 651 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 652 struct mt8365_afe_private *afe_priv = afe->platform_priv; 653 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id; 654 struct mtk_base_afe_memif *memif = &afe->memif[dai_id]; 655 struct mt8365_fe_dai_data *fe_data = &afe_priv->fe_data[dai_id]; 656 int ret = 0; 657 658 if (fe_data->use_sram) { 659 snd_pcm_set_runtime_buffer(substream, NULL); 660 } else { 661 ret = snd_pcm_lib_free_pages(substream); 662 663 mt8365_afe_emi_clk_off(afe); 664 } 665 666 return ret; 667 } 668 669 static int mt8365_afe_fe_prepare(struct snd_pcm_substream *substream, 670 struct snd_soc_dai *dai) 671 { 672 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 673 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 674 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id; 675 struct mtk_base_afe_memif *memif = &afe->memif[dai_id]; 676 677 /* set format */ 678 if (memif->data->hd_reg >= 0) { 679 switch (substream->runtime->format) { 680 case SNDRV_PCM_FORMAT_S16_LE: 681 regmap_update_bits(afe->regmap, memif->data->hd_reg, 682 3 << memif->data->hd_shift, 683 0 << memif->data->hd_shift); 684 break; 685 case SNDRV_PCM_FORMAT_S32_LE: 686 regmap_update_bits(afe->regmap, memif->data->hd_reg, 687 3 << memif->data->hd_shift, 688 3 << memif->data->hd_shift); 689 690 if (dai_id == MT8365_AFE_MEMIF_TDM_IN) { 691 regmap_update_bits(afe->regmap, 692 memif->data->hd_reg, 693 3 << memif->data->hd_shift, 694 1 << memif->data->hd_shift); 695 regmap_update_bits(afe->regmap, 696 memif->data->hd_reg, 697 1 << memif->data->hd_align_mshift, 698 1 << memif->data->hd_align_mshift); 699 } 700 break; 701 case SNDRV_PCM_FORMAT_S24_LE: 702 regmap_update_bits(afe->regmap, memif->data->hd_reg, 703 3 << memif->data->hd_shift, 704 1 << memif->data->hd_shift); 705 break; 706 default: 707 return -EINVAL; 708 } 709 } 710 711 mt8365_afe_irq_direction_enable(afe, memif->irq_usage, 712 MT8365_AFE_IRQ_DIR_MCU); 713 714 return 0; 715 } 716 717 static int mt8365_afe_fe_trigger(struct snd_pcm_substream *substream, int cmd, 718 struct snd_soc_dai *dai) 719 { 720 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 721 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 722 struct mt8365_afe_private *afe_priv = afe->platform_priv; 723 int dai_id = snd_soc_rtd_to_cpu(rtd, 0)->id; 724 struct mt8365_control_data *ctrl_data = &afe_priv->ctrl_data; 725 726 switch (cmd) { 727 case SNDRV_PCM_TRIGGER_START: 728 case SNDRV_PCM_TRIGGER_RESUME: 729 /* enable channel merge */ 730 if (dai_id == MT8365_AFE_MEMIF_VUL2 && 731 !ctrl_data->bypass_cm1) { 732 regmap_update_bits(afe->regmap, AFE_CM1_CON0, 733 CM_AFE_CM_ON, CM_AFE_CM_ON); 734 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN && 735 !ctrl_data->bypass_cm2) { 736 regmap_update_bits(afe->regmap, AFE_CM2_CON0, 737 CM_AFE_CM_ON, CM_AFE_CM_ON); 738 } 739 break; 740 case SNDRV_PCM_TRIGGER_STOP: 741 case SNDRV_PCM_TRIGGER_SUSPEND: 742 /* disable channel merge */ 743 if (dai_id == MT8365_AFE_MEMIF_VUL2 && 744 !ctrl_data->bypass_cm1) { 745 regmap_update_bits(afe->regmap, AFE_CM1_CON0, 746 CM_AFE_CM_ON, ~CM_AFE_CM_ON); 747 } else if (dai_id == MT8365_AFE_MEMIF_TDM_IN && 748 !ctrl_data->bypass_cm2) { 749 regmap_update_bits(afe->regmap, AFE_CM2_CON0, 750 CM_AFE_CM_ON, ~CM_AFE_CM_ON); 751 } 752 break; 753 default: 754 break; 755 } 756 757 return mtk_afe_fe_trigger(substream, cmd, dai); 758 } 759 760 static int mt8365_afe_hw_gain1_startup(struct snd_pcm_substream *substream, 761 struct snd_soc_dai *dai) 762 { 763 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 764 765 mt8365_afe_enable_main_clk(afe); 766 return 0; 767 } 768 769 static void mt8365_afe_hw_gain1_shutdown(struct snd_pcm_substream *substream, 770 struct snd_soc_dai *dai) 771 { 772 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 773 struct mt8365_afe_private *afe_priv = afe->platform_priv; 774 struct mt8365_be_dai_data *be = 775 &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE]; 776 777 if (be->prepared[substream->stream]) { 778 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0, 779 AFE_GAIN1_CON0_EN_MASK, 0); 780 be->prepared[substream->stream] = false; 781 } 782 mt8365_afe_disable_main_clk(afe); 783 } 784 785 static int mt8365_afe_hw_gain1_prepare(struct snd_pcm_substream *substream, 786 struct snd_soc_dai *dai) 787 { 788 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 789 struct mt8365_afe_private *afe_priv = afe->platform_priv; 790 struct mt8365_be_dai_data *be = 791 &afe_priv->be_data[dai->id - MT8365_AFE_BACKEND_BASE]; 792 793 int fs; 794 unsigned int val1 = 0, val2 = 0; 795 796 if (be->prepared[substream->stream]) { 797 dev_info(afe->dev, "%s prepared already\n", __func__); 798 return 0; 799 } 800 801 fs = mt8365_afe_fs_timing(substream->runtime->rate); 802 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0, 803 AFE_GAIN1_CON0_MODE_MASK, (unsigned int)fs << 4); 804 805 regmap_read(afe->regmap, AFE_GAIN1_CON1, &val1); 806 regmap_read(afe->regmap, AFE_GAIN1_CUR, &val2); 807 if ((val1 & AFE_GAIN1_CON1_MASK) != (val2 & AFE_GAIN1_CUR_MASK)) 808 regmap_update_bits(afe->regmap, AFE_GAIN1_CUR, 809 AFE_GAIN1_CUR_MASK, val1); 810 811 regmap_update_bits(afe->regmap, AFE_GAIN1_CON0, 812 AFE_GAIN1_CON0_EN_MASK, 1); 813 be->prepared[substream->stream] = true; 814 815 return 0; 816 } 817 818 static const struct snd_pcm_hardware mt8365_hostless_hardware = { 819 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 820 SNDRV_PCM_INFO_MMAP_VALID), 821 .period_bytes_min = 256, 822 .period_bytes_max = 4 * 48 * 1024, 823 .periods_min = 2, 824 .periods_max = 256, 825 .buffer_bytes_max = 8 * 48 * 1024, 826 .fifo_size = 0, 827 }; 828 829 /* dai ops */ 830 static int mtk_dai_hostless_startup(struct snd_pcm_substream *substream, 831 struct snd_soc_dai *dai) 832 { 833 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 834 struct snd_pcm_runtime *runtime = substream->runtime; 835 int ret; 836 837 snd_soc_set_runtime_hwparams(substream, &mt8365_hostless_hardware); 838 839 ret = snd_pcm_hw_constraint_integer(runtime, 840 SNDRV_PCM_HW_PARAM_PERIODS); 841 if (ret < 0) 842 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); 843 return ret; 844 } 845 846 /* FE DAIs */ 847 static const struct snd_soc_dai_ops mt8365_afe_fe_dai_ops = { 848 .startup = mt8365_afe_fe_startup, 849 .shutdown = mt8365_afe_fe_shutdown, 850 .hw_params = mt8365_afe_fe_hw_params, 851 .hw_free = mt8365_afe_fe_hw_free, 852 .prepare = mt8365_afe_fe_prepare, 853 .trigger = mt8365_afe_fe_trigger, 854 }; 855 856 static const struct snd_soc_dai_ops mt8365_dai_hostless_ops = { 857 .startup = mtk_dai_hostless_startup, 858 }; 859 860 static const struct snd_soc_dai_ops mt8365_afe_hw_gain1_ops = { 861 .startup = mt8365_afe_hw_gain1_startup, 862 .shutdown = mt8365_afe_hw_gain1_shutdown, 863 .prepare = mt8365_afe_hw_gain1_prepare, 864 }; 865 866 static struct snd_soc_dai_driver mt8365_memif_dai_driver[] = { 867 /* FE DAIs: memory intefaces to CPU */ 868 { 869 .name = "DL1", 870 .id = MT8365_AFE_MEMIF_DL1, 871 .playback = { 872 .stream_name = "DL1", 873 .channels_min = 1, 874 .channels_max = 2, 875 .rates = SNDRV_PCM_RATE_8000_192000, 876 .formats = SNDRV_PCM_FMTBIT_S16_LE | 877 SNDRV_PCM_FMTBIT_S32_LE, 878 }, 879 .ops = &mt8365_afe_fe_dai_ops, 880 }, { 881 .name = "DL2", 882 .id = MT8365_AFE_MEMIF_DL2, 883 .playback = { 884 .stream_name = "DL2", 885 .channels_min = 1, 886 .channels_max = 2, 887 .rates = SNDRV_PCM_RATE_8000_192000, 888 .formats = SNDRV_PCM_FMTBIT_S16_LE | 889 SNDRV_PCM_FMTBIT_S32_LE, 890 }, 891 .ops = &mt8365_afe_fe_dai_ops, 892 }, { 893 .name = "TDM_OUT", 894 .id = MT8365_AFE_MEMIF_TDM_OUT, 895 .playback = { 896 .stream_name = "TDM_OUT", 897 .channels_min = 1, 898 .channels_max = 8, 899 .rates = SNDRV_PCM_RATE_8000_192000, 900 .formats = SNDRV_PCM_FMTBIT_S16_LE | 901 SNDRV_PCM_FMTBIT_S32_LE, 902 }, 903 .ops = &mt8365_afe_fe_dai_ops, 904 }, { 905 .name = "AWB", 906 .id = MT8365_AFE_MEMIF_AWB, 907 .capture = { 908 .stream_name = "AWB", 909 .channels_min = 1, 910 .channels_max = 2, 911 .rates = SNDRV_PCM_RATE_8000_192000, 912 .formats = SNDRV_PCM_FMTBIT_S16_LE | 913 SNDRV_PCM_FMTBIT_S32_LE, 914 }, 915 .ops = &mt8365_afe_fe_dai_ops, 916 }, { 917 .name = "VUL", 918 .id = MT8365_AFE_MEMIF_VUL, 919 .capture = { 920 .stream_name = "VUL", 921 .channels_min = 1, 922 .channels_max = 2, 923 .rates = SNDRV_PCM_RATE_8000_192000, 924 .formats = SNDRV_PCM_FMTBIT_S16_LE | 925 SNDRV_PCM_FMTBIT_S32_LE, 926 }, 927 .ops = &mt8365_afe_fe_dai_ops, 928 }, { 929 .name = "VUL2", 930 .id = MT8365_AFE_MEMIF_VUL2, 931 .capture = { 932 .stream_name = "VUL2", 933 .channels_min = 1, 934 .channels_max = 16, 935 .rates = SNDRV_PCM_RATE_8000_192000, 936 .formats = SNDRV_PCM_FMTBIT_S16_LE | 937 SNDRV_PCM_FMTBIT_S32_LE, 938 }, 939 .ops = &mt8365_afe_fe_dai_ops, 940 }, { 941 .name = "VUL3", 942 .id = MT8365_AFE_MEMIF_VUL3, 943 .capture = { 944 .stream_name = "VUL3", 945 .channels_min = 1, 946 .channels_max = 2, 947 .rates = SNDRV_PCM_RATE_8000_192000, 948 .formats = SNDRV_PCM_FMTBIT_S16_LE | 949 SNDRV_PCM_FMTBIT_S32_LE, 950 }, 951 .ops = &mt8365_afe_fe_dai_ops, 952 }, { 953 .name = "TDM_IN", 954 .id = MT8365_AFE_MEMIF_TDM_IN, 955 .capture = { 956 .stream_name = "TDM_IN", 957 .channels_min = 1, 958 .channels_max = 16, 959 .rates = SNDRV_PCM_RATE_8000_192000, 960 .formats = SNDRV_PCM_FMTBIT_S16_LE | 961 SNDRV_PCM_FMTBIT_S32_LE, 962 }, 963 .ops = &mt8365_afe_fe_dai_ops, 964 }, { 965 .name = "Hostless FM DAI", 966 .id = MT8365_AFE_IO_VIRTUAL_FM, 967 .playback = { 968 .stream_name = "Hostless FM DL", 969 .channels_min = 1, 970 .channels_max = 2, 971 .rates = SNDRV_PCM_RATE_8000_192000, 972 .formats = SNDRV_PCM_FMTBIT_S16_LE | 973 SNDRV_PCM_FMTBIT_S24_LE | 974 SNDRV_PCM_FMTBIT_S32_LE, 975 }, 976 .capture = { 977 .stream_name = "Hostless FM UL", 978 .channels_min = 1, 979 .channels_max = 2, 980 .rates = SNDRV_PCM_RATE_8000_192000, 981 .formats = SNDRV_PCM_FMTBIT_S16_LE | 982 SNDRV_PCM_FMTBIT_S24_LE | 983 SNDRV_PCM_FMTBIT_S32_LE, 984 }, 985 .ops = &mt8365_dai_hostless_ops, 986 }, { 987 .name = "HW_GAIN1", 988 .id = MT8365_AFE_IO_HW_GAIN1, 989 .playback = { 990 .stream_name = "HW Gain 1 In", 991 .channels_min = 1, 992 .channels_max = 2, 993 .rates = SNDRV_PCM_RATE_8000_192000, 994 .formats = SNDRV_PCM_FMTBIT_S16_LE | 995 SNDRV_PCM_FMTBIT_S24_LE | 996 SNDRV_PCM_FMTBIT_S32_LE, 997 }, 998 .capture = { 999 .stream_name = "HW Gain 1 Out", 1000 .channels_min = 1, 1001 .channels_max = 2, 1002 .rates = SNDRV_PCM_RATE_8000_192000, 1003 .formats = SNDRV_PCM_FMTBIT_S16_LE | 1004 SNDRV_PCM_FMTBIT_S24_LE | 1005 SNDRV_PCM_FMTBIT_S32_LE, 1006 }, 1007 .ops = &mt8365_afe_hw_gain1_ops, 1008 .symmetric_rate = 1, 1009 .symmetric_channels = 1, 1010 .symmetric_sample_bits = 1, 1011 }, 1012 }; 1013 1014 static const struct snd_kcontrol_new mt8365_afe_o00_mix[] = { 1015 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN0, 5, 1, 0), 1016 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN0, 7, 1, 0), 1017 }; 1018 1019 static const struct snd_kcontrol_new mt8365_afe_o01_mix[] = { 1020 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN1, 6, 1, 0), 1021 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN1, 8, 1, 0), 1022 }; 1023 1024 static const struct snd_kcontrol_new mt8365_afe_o03_mix[] = { 1025 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN3, 5, 1, 0), 1026 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN3, 7, 1, 0), 1027 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN3, 0, 1, 0), 1028 SOC_DAPM_SINGLE_AUTODISABLE("I10 Switch", AFE_CONN3, 10, 1, 0), 1029 }; 1030 1031 static const struct snd_kcontrol_new mt8365_afe_o04_mix[] = { 1032 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN4, 6, 1, 0), 1033 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN4, 8, 1, 0), 1034 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN4, 1, 1, 0), 1035 SOC_DAPM_SINGLE_AUTODISABLE("I11 Switch", AFE_CONN4, 11, 1, 0), 1036 }; 1037 1038 static const struct snd_kcontrol_new mt8365_afe_o05_mix[] = { 1039 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN5, 0, 1, 0), 1040 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN5, 3, 1, 0), 1041 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN5, 5, 1, 0), 1042 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN5, 7, 1, 0), 1043 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN5, 9, 1, 0), 1044 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN5, 14, 1, 0), 1045 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN5, 16, 1, 0), 1046 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN5, 18, 1, 0), 1047 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN5, 20, 1, 0), 1048 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN5, 23, 1, 0), 1049 SOC_DAPM_SINGLE_AUTODISABLE("I10L Switch", AFE_CONN5, 10, 1, 0), 1050 }; 1051 1052 static const struct snd_kcontrol_new mt8365_afe_o06_mix[] = { 1053 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN6, 1, 1, 0), 1054 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN6, 4, 1, 0), 1055 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN6, 6, 1, 0), 1056 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN6, 8, 1, 0), 1057 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN6, 22, 1, 0), 1058 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN6, 15, 1, 0), 1059 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN6, 17, 1, 0), 1060 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN6, 19, 1, 0), 1061 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN6, 21, 1, 0), 1062 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN6, 24, 1, 0), 1063 SOC_DAPM_SINGLE_AUTODISABLE("I11L Switch", AFE_CONN6, 11, 1, 0), 1064 }; 1065 1066 static const struct snd_kcontrol_new mt8365_afe_o07_mix[] = { 1067 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN7, 5, 1, 0), 1068 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN7, 7, 1, 0), 1069 }; 1070 1071 static const struct snd_kcontrol_new mt8365_afe_o08_mix[] = { 1072 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN8, 6, 1, 0), 1073 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN8, 8, 1, 0), 1074 }; 1075 1076 static const struct snd_kcontrol_new mt8365_afe_o09_mix[] = { 1077 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN9, 0, 1, 0), 1078 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN9, 3, 1, 0), 1079 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN9, 9, 1, 0), 1080 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN9, 14, 1, 0), 1081 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN9, 16, 1, 0), 1082 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN9, 18, 1, 0), 1083 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN9, 20, 1, 0), 1084 }; 1085 1086 static const struct snd_kcontrol_new mt8365_afe_o10_mix[] = { 1087 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN10, 1, 1, 0), 1088 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN10, 4, 1, 0), 1089 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN10, 22, 1, 0), 1090 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN10, 15, 1, 0), 1091 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN10, 17, 1, 0), 1092 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN10, 19, 1, 0), 1093 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN10, 21, 1, 0), 1094 }; 1095 1096 static const struct snd_kcontrol_new mt8365_afe_o11_mix[] = { 1097 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN11, 0, 1, 0), 1098 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN11, 3, 1, 0), 1099 SOC_DAPM_SINGLE_AUTODISABLE("I09 Switch", AFE_CONN11, 9, 1, 0), 1100 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN11, 14, 1, 0), 1101 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN11, 16, 1, 0), 1102 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN11, 18, 1, 0), 1103 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN11, 20, 1, 0), 1104 }; 1105 1106 static const struct snd_kcontrol_new mt8365_afe_o12_mix[] = { 1107 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN12, 1, 1, 0), 1108 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN12, 4, 1, 0), 1109 SOC_DAPM_SINGLE_AUTODISABLE("I22 Switch", AFE_CONN12, 22, 1, 0), 1110 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN12, 15, 1, 0), 1111 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN12, 17, 1, 0), 1112 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN12, 19, 1, 0), 1113 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN12, 21, 1, 0), 1114 }; 1115 1116 static const struct snd_kcontrol_new mt8365_afe_o13_mix[] = { 1117 SOC_DAPM_SINGLE_AUTODISABLE("I00 Switch", AFE_CONN13, 0, 1, 0), 1118 }; 1119 1120 static const struct snd_kcontrol_new mt8365_afe_o14_mix[] = { 1121 SOC_DAPM_SINGLE_AUTODISABLE("I01 Switch", AFE_CONN14, 1, 1, 0), 1122 }; 1123 1124 static const struct snd_kcontrol_new mt8365_afe_o15_mix[] = { 1125 }; 1126 1127 static const struct snd_kcontrol_new mt8365_afe_o16_mix[] = { 1128 }; 1129 1130 static const struct snd_kcontrol_new mt8365_afe_o17_mix[] = { 1131 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN17, 3, 1, 0), 1132 SOC_DAPM_SINGLE_AUTODISABLE("I14 Switch", AFE_CONN17, 14, 1, 0), 1133 }; 1134 1135 static const struct snd_kcontrol_new mt8365_afe_o18_mix[] = { 1136 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN18, 4, 1, 0), 1137 SOC_DAPM_SINGLE_AUTODISABLE("I15 Switch", AFE_CONN18, 15, 1, 0), 1138 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN18, 23, 1, 0), 1139 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN18, 25, 1, 0), 1140 }; 1141 1142 static const struct snd_kcontrol_new mt8365_afe_o19_mix[] = { 1143 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN19, 4, 1, 0), 1144 SOC_DAPM_SINGLE_AUTODISABLE("I16 Switch", AFE_CONN19, 16, 1, 0), 1145 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN19, 23, 1, 0), 1146 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN19, 24, 1, 0), 1147 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN19, 25, 1, 0), 1148 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN19, 26, 1, 0), 1149 }; 1150 1151 static const struct snd_kcontrol_new mt8365_afe_o20_mix[] = { 1152 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN20, 17, 1, 0), 1153 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN20, 24, 1, 0), 1154 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN20, 26, 1, 0), 1155 }; 1156 1157 static const struct snd_kcontrol_new mt8365_afe_o21_mix[] = { 1158 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN21, 18, 1, 0), 1159 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN21, 23, 1, 0), 1160 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN21, 25, 1, 0), 1161 }; 1162 1163 static const struct snd_kcontrol_new mt8365_afe_o22_mix[] = { 1164 SOC_DAPM_SINGLE_AUTODISABLE("I19 Switch", AFE_CONN22, 19, 1, 0), 1165 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN22, 24, 1, 0), 1166 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN22, 26, 1, 0), 1167 }; 1168 1169 static const struct snd_kcontrol_new mt8365_afe_o23_mix[] = { 1170 SOC_DAPM_SINGLE_AUTODISABLE("I20 Switch", AFE_CONN23, 20, 1, 0), 1171 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN23, 23, 1, 0), 1172 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN23, 25, 1, 0), 1173 }; 1174 1175 static const struct snd_kcontrol_new mt8365_afe_o24_mix[] = { 1176 SOC_DAPM_SINGLE_AUTODISABLE("I21 Switch", AFE_CONN24, 21, 1, 0), 1177 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN24, 24, 1, 0), 1178 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN24, 26, 1, 0), 1179 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN24, 23, 1, 0), 1180 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN24, 25, 1, 0), 1181 }; 1182 1183 static const struct snd_kcontrol_new mt8365_afe_o25_mix[] = { 1184 SOC_DAPM_SINGLE_AUTODISABLE("I27 Switch", AFE_CONN25, 27, 1, 0), 1185 SOC_DAPM_SINGLE_AUTODISABLE("I23 Switch", AFE_CONN25, 23, 1, 0), 1186 SOC_DAPM_SINGLE_AUTODISABLE("I25 Switch", AFE_CONN25, 25, 1, 0), 1187 }; 1188 1189 static const struct snd_kcontrol_new mt8365_afe_o26_mix[] = { 1190 SOC_DAPM_SINGLE_AUTODISABLE("I28 Switch", AFE_CONN26, 28, 1, 0), 1191 SOC_DAPM_SINGLE_AUTODISABLE("I24 Switch", AFE_CONN26, 24, 1, 0), 1192 SOC_DAPM_SINGLE_AUTODISABLE("I26 Switch", AFE_CONN26, 26, 1, 0), 1193 }; 1194 1195 static const struct snd_kcontrol_new mt8365_afe_o27_mix[] = { 1196 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN27, 5, 1, 0), 1197 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN27, 7, 1, 0), 1198 }; 1199 1200 static const struct snd_kcontrol_new mt8365_afe_o28_mix[] = { 1201 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN28, 6, 1, 0), 1202 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN28, 8, 1, 0), 1203 }; 1204 1205 static const struct snd_kcontrol_new mt8365_afe_o29_mix[] = { 1206 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN29, 5, 1, 0), 1207 SOC_DAPM_SINGLE_AUTODISABLE("I07 Switch", AFE_CONN29, 7, 1, 0), 1208 }; 1209 1210 static const struct snd_kcontrol_new mt8365_afe_o30_mix[] = { 1211 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN30, 6, 1, 0), 1212 SOC_DAPM_SINGLE_AUTODISABLE("I08 Switch", AFE_CONN30, 8, 1, 0), 1213 }; 1214 1215 static const struct snd_kcontrol_new mt8365_afe_o31_mix[] = { 1216 SOC_DAPM_SINGLE_AUTODISABLE("I29 Switch", AFE_CONN31, 29, 1, 0), 1217 }; 1218 1219 static const struct snd_kcontrol_new mt8365_afe_o32_mix[] = { 1220 SOC_DAPM_SINGLE_AUTODISABLE("I30 Switch", AFE_CONN32, 30, 1, 0), 1221 }; 1222 1223 static const struct snd_kcontrol_new mt8365_afe_o33_mix[] = { 1224 SOC_DAPM_SINGLE_AUTODISABLE("I31 Switch", AFE_CONN33, 31, 1, 0), 1225 }; 1226 1227 static const struct snd_kcontrol_new mt8365_afe_o34_mix[] = { 1228 SOC_DAPM_SINGLE_AUTODISABLE("I32 Switch", AFE_CONN34_1, 0, 1, 0), 1229 }; 1230 1231 static const struct snd_kcontrol_new mt8365_afe_o35_mix[] = { 1232 SOC_DAPM_SINGLE_AUTODISABLE("I33 Switch", AFE_CONN35_1, 1, 1, 0), 1233 }; 1234 1235 static const struct snd_kcontrol_new mt8365_afe_o36_mix[] = { 1236 SOC_DAPM_SINGLE_AUTODISABLE("I34 Switch", AFE_CONN36_1, 2, 1, 0), 1237 }; 1238 1239 static const struct snd_kcontrol_new mtk_hw_gain1_in_ch1_mix[] = { 1240 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN13, 1241 0, 1, 0), 1242 }; 1243 1244 static const struct snd_kcontrol_new mtk_hw_gain1_in_ch2_mix[] = { 1245 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN14, 1246 1, 1, 0), 1247 }; 1248 1249 static int mt8365_afe_cm2_io_input_mux_get(struct snd_kcontrol *kcontrol, 1250 struct snd_ctl_elem_value *ucontrol) 1251 { 1252 ucontrol->value.integer.value[0] = mCM2Input; 1253 1254 return 0; 1255 } 1256 1257 static int mt8365_afe_cm2_io_input_mux_put(struct snd_kcontrol *kcontrol, 1258 struct snd_ctl_elem_value *ucontrol) 1259 { 1260 struct snd_soc_dapm_context *dapm = 1261 snd_soc_dapm_kcontrol_dapm(kcontrol); 1262 struct snd_soc_component *comp = snd_soc_dapm_to_component(dapm); 1263 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(comp); 1264 struct mt8365_afe_private *afe_priv = afe->platform_priv; 1265 int ret; 1266 1267 mCM2Input = ucontrol->value.enumerated.item[0]; 1268 1269 afe_priv->cm2_mux_input = mCM2Input; 1270 ret = snd_soc_dapm_put_enum_double(kcontrol, ucontrol); 1271 1272 return ret; 1273 } 1274 1275 static const char * const fmhwgain_text[] = { 1276 "OPEN", "FM_HW_GAIN_IO" 1277 }; 1278 1279 static const char * const ain_text[] = { 1280 "INT ADC", "EXT ADC", 1281 }; 1282 1283 static const char * const vul2_in_input_text[] = { 1284 "VUL2_IN_FROM_O17O18", "VUL2_IN_FROM_CM1", 1285 }; 1286 1287 static const char * const mt8365_afe_cm2_mux_text[] = { 1288 "OPEN", "FROM_GASRC1_OUT", "FROM_GASRC2_OUT", "FROM_TDM_ASRC_OUT", 1289 }; 1290 1291 static SOC_ENUM_SINGLE_VIRT_DECL(fmhwgain_enum, fmhwgain_text); 1292 static SOC_ENUM_SINGLE_DECL(ain_enum, AFE_ADDA_TOP_CON0, 0, ain_text); 1293 static SOC_ENUM_SINGLE_VIRT_DECL(vul2_in_input_enum, vul2_in_input_text); 1294 static SOC_ENUM_SINGLE_VIRT_DECL(mt8365_afe_cm2_mux_input_enum, 1295 mt8365_afe_cm2_mux_text); 1296 1297 static const struct snd_kcontrol_new fmhwgain_mux = 1298 SOC_DAPM_ENUM("FM HW Gain Source", fmhwgain_enum); 1299 1300 static const struct snd_kcontrol_new ain_mux = 1301 SOC_DAPM_ENUM("AIN Source", ain_enum); 1302 1303 static const struct snd_kcontrol_new vul2_in_input_mux = 1304 SOC_DAPM_ENUM("VUL2 Input", vul2_in_input_enum); 1305 1306 static const struct snd_kcontrol_new mt8365_afe_cm2_mux_input_mux = 1307 SOC_DAPM_ENUM_EXT("CM2_MUX Source", mt8365_afe_cm2_mux_input_enum, 1308 mt8365_afe_cm2_io_input_mux_get, 1309 mt8365_afe_cm2_io_input_mux_put); 1310 1311 static const struct snd_soc_dapm_widget mt8365_memif_widgets[] = { 1312 /* inter-connections */ 1313 SND_SOC_DAPM_MIXER("I00", SND_SOC_NOPM, 0, 0, NULL, 0), 1314 SND_SOC_DAPM_MIXER("I01", SND_SOC_NOPM, 0, 0, NULL, 0), 1315 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0), 1316 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0), 1317 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0), 1318 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0), 1319 SND_SOC_DAPM_MIXER("I07", SND_SOC_NOPM, 0, 0, NULL, 0), 1320 SND_SOC_DAPM_MIXER("I08", SND_SOC_NOPM, 0, 0, NULL, 0), 1321 SND_SOC_DAPM_MIXER("I05L", SND_SOC_NOPM, 0, 0, NULL, 0), 1322 SND_SOC_DAPM_MIXER("I06L", SND_SOC_NOPM, 0, 0, NULL, 0), 1323 SND_SOC_DAPM_MIXER("I07L", SND_SOC_NOPM, 0, 0, NULL, 0), 1324 SND_SOC_DAPM_MIXER("I08L", SND_SOC_NOPM, 0, 0, NULL, 0), 1325 SND_SOC_DAPM_MIXER("I09", SND_SOC_NOPM, 0, 0, NULL, 0), 1326 SND_SOC_DAPM_MIXER("I10", SND_SOC_NOPM, 0, 0, NULL, 0), 1327 SND_SOC_DAPM_MIXER("I11", SND_SOC_NOPM, 0, 0, NULL, 0), 1328 SND_SOC_DAPM_MIXER("I10L", SND_SOC_NOPM, 0, 0, NULL, 0), 1329 SND_SOC_DAPM_MIXER("I11L", SND_SOC_NOPM, 0, 0, NULL, 0), 1330 SND_SOC_DAPM_MIXER("I12", SND_SOC_NOPM, 0, 0, NULL, 0), 1331 SND_SOC_DAPM_MIXER("I13", SND_SOC_NOPM, 0, 0, NULL, 0), 1332 SND_SOC_DAPM_MIXER("I14", SND_SOC_NOPM, 0, 0, NULL, 0), 1333 SND_SOC_DAPM_MIXER("I15", SND_SOC_NOPM, 0, 0, NULL, 0), 1334 SND_SOC_DAPM_MIXER("I16", SND_SOC_NOPM, 0, 0, NULL, 0), 1335 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), 1336 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), 1337 SND_SOC_DAPM_MIXER("I19", SND_SOC_NOPM, 0, 0, NULL, 0), 1338 SND_SOC_DAPM_MIXER("I20", SND_SOC_NOPM, 0, 0, NULL, 0), 1339 SND_SOC_DAPM_MIXER("I21", SND_SOC_NOPM, 0, 0, NULL, 0), 1340 SND_SOC_DAPM_MIXER("I22", SND_SOC_NOPM, 0, 0, NULL, 0), 1341 SND_SOC_DAPM_MIXER("I23", SND_SOC_NOPM, 0, 0, NULL, 0), 1342 SND_SOC_DAPM_MIXER("I24", SND_SOC_NOPM, 0, 0, NULL, 0), 1343 SND_SOC_DAPM_MIXER("I25", SND_SOC_NOPM, 0, 0, NULL, 0), 1344 SND_SOC_DAPM_MIXER("I26", SND_SOC_NOPM, 0, 0, NULL, 0), 1345 SND_SOC_DAPM_MIXER("I27", SND_SOC_NOPM, 0, 0, NULL, 0), 1346 SND_SOC_DAPM_MIXER("I28", SND_SOC_NOPM, 0, 0, NULL, 0), 1347 SND_SOC_DAPM_MIXER("I29", SND_SOC_NOPM, 0, 0, NULL, 0), 1348 SND_SOC_DAPM_MIXER("I30", SND_SOC_NOPM, 0, 0, NULL, 0), 1349 SND_SOC_DAPM_MIXER("I31", SND_SOC_NOPM, 0, 0, NULL, 0), 1350 SND_SOC_DAPM_MIXER("I32", SND_SOC_NOPM, 0, 0, NULL, 0), 1351 SND_SOC_DAPM_MIXER("I33", SND_SOC_NOPM, 0, 0, NULL, 0), 1352 SND_SOC_DAPM_MIXER("I34", SND_SOC_NOPM, 0, 0, NULL, 0), 1353 SND_SOC_DAPM_MIXER("O00", SND_SOC_NOPM, 0, 0, 1354 mt8365_afe_o00_mix, ARRAY_SIZE(mt8365_afe_o00_mix)), 1355 SND_SOC_DAPM_MIXER("O01", SND_SOC_NOPM, 0, 0, 1356 mt8365_afe_o01_mix, ARRAY_SIZE(mt8365_afe_o01_mix)), 1357 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, 1358 mt8365_afe_o03_mix, ARRAY_SIZE(mt8365_afe_o03_mix)), 1359 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0, 1360 mt8365_afe_o04_mix, ARRAY_SIZE(mt8365_afe_o04_mix)), 1361 SND_SOC_DAPM_MIXER("O05", SND_SOC_NOPM, 0, 0, 1362 mt8365_afe_o05_mix, ARRAY_SIZE(mt8365_afe_o05_mix)), 1363 SND_SOC_DAPM_MIXER("O06", SND_SOC_NOPM, 0, 0, 1364 mt8365_afe_o06_mix, ARRAY_SIZE(mt8365_afe_o06_mix)), 1365 SND_SOC_DAPM_MIXER("O07", SND_SOC_NOPM, 0, 0, 1366 mt8365_afe_o07_mix, ARRAY_SIZE(mt8365_afe_o07_mix)), 1367 SND_SOC_DAPM_MIXER("O08", SND_SOC_NOPM, 0, 0, 1368 mt8365_afe_o08_mix, ARRAY_SIZE(mt8365_afe_o08_mix)), 1369 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0, 1370 mt8365_afe_o09_mix, ARRAY_SIZE(mt8365_afe_o09_mix)), 1371 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0, 1372 mt8365_afe_o10_mix, ARRAY_SIZE(mt8365_afe_o10_mix)), 1373 SND_SOC_DAPM_MIXER("O11", SND_SOC_NOPM, 0, 0, 1374 mt8365_afe_o11_mix, ARRAY_SIZE(mt8365_afe_o11_mix)), 1375 SND_SOC_DAPM_MIXER("O12", SND_SOC_NOPM, 0, 0, 1376 mt8365_afe_o12_mix, ARRAY_SIZE(mt8365_afe_o12_mix)), 1377 SND_SOC_DAPM_MIXER("O13", SND_SOC_NOPM, 0, 0, 1378 mt8365_afe_o13_mix, ARRAY_SIZE(mt8365_afe_o13_mix)), 1379 SND_SOC_DAPM_MIXER("O14", SND_SOC_NOPM, 0, 0, 1380 mt8365_afe_o14_mix, ARRAY_SIZE(mt8365_afe_o14_mix)), 1381 SND_SOC_DAPM_MIXER("O15", SND_SOC_NOPM, 0, 0, 1382 mt8365_afe_o15_mix, ARRAY_SIZE(mt8365_afe_o15_mix)), 1383 SND_SOC_DAPM_MIXER("O16", SND_SOC_NOPM, 0, 0, 1384 mt8365_afe_o16_mix, ARRAY_SIZE(mt8365_afe_o16_mix)), 1385 SND_SOC_DAPM_MIXER("O17", SND_SOC_NOPM, 0, 0, 1386 mt8365_afe_o17_mix, ARRAY_SIZE(mt8365_afe_o17_mix)), 1387 SND_SOC_DAPM_MIXER("O18", SND_SOC_NOPM, 0, 0, 1388 mt8365_afe_o18_mix, ARRAY_SIZE(mt8365_afe_o18_mix)), 1389 SND_SOC_DAPM_MIXER("O19", SND_SOC_NOPM, 0, 0, 1390 mt8365_afe_o19_mix, ARRAY_SIZE(mt8365_afe_o19_mix)), 1391 SND_SOC_DAPM_MIXER("O20", SND_SOC_NOPM, 0, 0, 1392 mt8365_afe_o20_mix, ARRAY_SIZE(mt8365_afe_o20_mix)), 1393 SND_SOC_DAPM_MIXER("O21", SND_SOC_NOPM, 0, 0, 1394 mt8365_afe_o21_mix, ARRAY_SIZE(mt8365_afe_o21_mix)), 1395 SND_SOC_DAPM_MIXER("O22", SND_SOC_NOPM, 0, 0, 1396 mt8365_afe_o22_mix, ARRAY_SIZE(mt8365_afe_o22_mix)), 1397 SND_SOC_DAPM_MIXER("O23", SND_SOC_NOPM, 0, 0, 1398 mt8365_afe_o23_mix, ARRAY_SIZE(mt8365_afe_o23_mix)), 1399 SND_SOC_DAPM_MIXER("O24", SND_SOC_NOPM, 0, 0, 1400 mt8365_afe_o24_mix, ARRAY_SIZE(mt8365_afe_o24_mix)), 1401 SND_SOC_DAPM_MIXER("O25", SND_SOC_NOPM, 0, 0, 1402 mt8365_afe_o25_mix, ARRAY_SIZE(mt8365_afe_o25_mix)), 1403 SND_SOC_DAPM_MIXER("O26", SND_SOC_NOPM, 0, 0, 1404 mt8365_afe_o26_mix, ARRAY_SIZE(mt8365_afe_o26_mix)), 1405 SND_SOC_DAPM_MIXER("O27", SND_SOC_NOPM, 0, 0, 1406 mt8365_afe_o27_mix, ARRAY_SIZE(mt8365_afe_o27_mix)), 1407 SND_SOC_DAPM_MIXER("O28", SND_SOC_NOPM, 0, 0, 1408 mt8365_afe_o28_mix, ARRAY_SIZE(mt8365_afe_o28_mix)), 1409 SND_SOC_DAPM_MIXER("O29", SND_SOC_NOPM, 0, 0, 1410 mt8365_afe_o29_mix, ARRAY_SIZE(mt8365_afe_o29_mix)), 1411 SND_SOC_DAPM_MIXER("O30", SND_SOC_NOPM, 0, 0, 1412 mt8365_afe_o30_mix, ARRAY_SIZE(mt8365_afe_o30_mix)), 1413 SND_SOC_DAPM_MIXER("O31", SND_SOC_NOPM, 0, 0, 1414 mt8365_afe_o31_mix, ARRAY_SIZE(mt8365_afe_o31_mix)), 1415 SND_SOC_DAPM_MIXER("O32", SND_SOC_NOPM, 0, 0, 1416 mt8365_afe_o32_mix, ARRAY_SIZE(mt8365_afe_o32_mix)), 1417 SND_SOC_DAPM_MIXER("O33", SND_SOC_NOPM, 0, 0, 1418 mt8365_afe_o33_mix, ARRAY_SIZE(mt8365_afe_o33_mix)), 1419 SND_SOC_DAPM_MIXER("O34", SND_SOC_NOPM, 0, 0, 1420 mt8365_afe_o34_mix, ARRAY_SIZE(mt8365_afe_o34_mix)), 1421 SND_SOC_DAPM_MIXER("O35", SND_SOC_NOPM, 0, 0, 1422 mt8365_afe_o35_mix, ARRAY_SIZE(mt8365_afe_o35_mix)), 1423 SND_SOC_DAPM_MIXER("O36", SND_SOC_NOPM, 0, 0, 1424 mt8365_afe_o36_mix, ARRAY_SIZE(mt8365_afe_o36_mix)), 1425 SND_SOC_DAPM_MIXER("CM2_Mux IO", SND_SOC_NOPM, 0, 0, NULL, 0), 1426 SND_SOC_DAPM_MIXER("CM1_IO", SND_SOC_NOPM, 0, 0, NULL, 0), 1427 SND_SOC_DAPM_MIXER("O17O18", SND_SOC_NOPM, 0, 0, NULL, 0), 1428 /* inter-connections */ 1429 SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH1", SND_SOC_NOPM, 0, 0, 1430 mtk_hw_gain1_in_ch1_mix, 1431 ARRAY_SIZE(mtk_hw_gain1_in_ch1_mix)), 1432 SND_SOC_DAPM_MIXER("HW_GAIN1_IN_CH2", SND_SOC_NOPM, 0, 0, 1433 mtk_hw_gain1_in_ch2_mix, 1434 ARRAY_SIZE(mtk_hw_gain1_in_ch2_mix)), 1435 1436 SND_SOC_DAPM_INPUT("DL Source"), 1437 1438 SND_SOC_DAPM_MUX("CM2_Mux_IO Input Mux", SND_SOC_NOPM, 0, 0, 1439 &mt8365_afe_cm2_mux_input_mux), 1440 1441 SND_SOC_DAPM_MUX("AIN Mux", SND_SOC_NOPM, 0, 0, &ain_mux), 1442 SND_SOC_DAPM_MUX("VUL2 Input Mux", SND_SOC_NOPM, 0, 0, 1443 &vul2_in_input_mux), 1444 1445 SND_SOC_DAPM_MUX("FM HW Gain Mux", SND_SOC_NOPM, 0, 0, &fmhwgain_mux), 1446 1447 SND_SOC_DAPM_INPUT("HW Gain 1 Out Endpoint"), 1448 SND_SOC_DAPM_OUTPUT("HW Gain 1 In Endpoint"), 1449 }; 1450 1451 static const struct snd_soc_dapm_route mt8365_memif_routes[] = { 1452 /* downlink */ 1453 {"I00", NULL, "2ND I2S Capture"}, 1454 {"I01", NULL, "2ND I2S Capture"}, 1455 {"I05", NULL, "DL1"}, 1456 {"I06", NULL, "DL1"}, 1457 {"I07", NULL, "DL2"}, 1458 {"I08", NULL, "DL2"}, 1459 1460 {"O03", "I05 Switch", "I05"}, 1461 {"O04", "I06 Switch", "I06"}, 1462 {"O00", "I05 Switch", "I05"}, 1463 {"O01", "I06 Switch", "I06"}, 1464 {"O07", "I05 Switch", "I05"}, 1465 {"O08", "I06 Switch", "I06"}, 1466 {"O27", "I05 Switch", "I05"}, 1467 {"O28", "I06 Switch", "I06"}, 1468 {"O29", "I05 Switch", "I05"}, 1469 {"O30", "I06 Switch", "I06"}, 1470 1471 {"O03", "I07 Switch", "I07"}, 1472 {"O04", "I08 Switch", "I08"}, 1473 {"O00", "I07 Switch", "I07"}, 1474 {"O01", "I08 Switch", "I08"}, 1475 {"O07", "I07 Switch", "I07"}, 1476 {"O08", "I08 Switch", "I08"}, 1477 1478 /* uplink */ 1479 {"AWB", NULL, "O05"}, 1480 {"AWB", NULL, "O06"}, 1481 {"VUL", NULL, "O09"}, 1482 {"VUL", NULL, "O10"}, 1483 {"VUL3", NULL, "O11"}, 1484 {"VUL3", NULL, "O12"}, 1485 1486 {"AIN Mux", "EXT ADC", "I2S Capture"}, 1487 {"I03", NULL, "AIN Mux"}, 1488 {"I04", NULL, "AIN Mux"}, 1489 1490 {"HW_GAIN1_IN_CH1", "CONNSYS_I2S_CH1", "Hostless FM DL"}, 1491 {"HW_GAIN1_IN_CH2", "CONNSYS_I2S_CH2", "Hostless FM DL"}, 1492 1493 {"HW Gain 1 In Endpoint", NULL, "HW Gain 1 In"}, 1494 {"HW Gain 1 Out", NULL, "HW Gain 1 Out Endpoint"}, 1495 {"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH1"}, 1496 {"HW Gain 1 In", NULL, "HW_GAIN1_IN_CH2"}, 1497 1498 {"FM HW Gain Mux", "FM_HW_GAIN_IO", "HW Gain 1 Out"}, 1499 {"Hostless FM UL", NULL, "FM HW Gain Mux"}, 1500 {"Hostless FM UL", NULL, "FM 2ND I2S Mux"}, 1501 1502 {"O05", "I05 Switch", "I05L"}, 1503 {"O06", "I06 Switch", "I06L"}, 1504 {"O05", "I07 Switch", "I07L"}, 1505 {"O06", "I08 Switch", "I08L"}, 1506 1507 {"O05", "I03 Switch", "I03"}, 1508 {"O06", "I04 Switch", "I04"}, 1509 {"O05", "I00 Switch", "I00"}, 1510 {"O06", "I01 Switch", "I01"}, 1511 {"O05", "I09 Switch", "I09"}, 1512 {"O06", "I22 Switch", "I22"}, 1513 {"O05", "I14 Switch", "I14"}, 1514 {"O06", "I15 Switch", "I15"}, 1515 {"O05", "I16 Switch", "I16"}, 1516 {"O06", "I17 Switch", "I17"}, 1517 {"O05", "I18 Switch", "I18"}, 1518 {"O06", "I19 Switch", "I19"}, 1519 {"O05", "I20 Switch", "I20"}, 1520 {"O06", "I21 Switch", "I21"}, 1521 {"O05", "I23 Switch", "I23"}, 1522 {"O06", "I24 Switch", "I24"}, 1523 1524 {"O09", "I03 Switch", "I03"}, 1525 {"O10", "I04 Switch", "I04"}, 1526 {"O09", "I00 Switch", "I00"}, 1527 {"O10", "I01 Switch", "I01"}, 1528 {"O09", "I09 Switch", "I09"}, 1529 {"O10", "I22 Switch", "I22"}, 1530 {"O09", "I14 Switch", "I14"}, 1531 {"O10", "I15 Switch", "I15"}, 1532 {"O09", "I16 Switch", "I16"}, 1533 {"O10", "I17 Switch", "I17"}, 1534 {"O09", "I18 Switch", "I18"}, 1535 {"O10", "I19 Switch", "I19"}, 1536 {"O09", "I20 Switch", "I20"}, 1537 {"O10", "I21 Switch", "I21"}, 1538 1539 {"O11", "I03 Switch", "I03"}, 1540 {"O12", "I04 Switch", "I04"}, 1541 {"O11", "I00 Switch", "I00"}, 1542 {"O12", "I01 Switch", "I01"}, 1543 {"O11", "I09 Switch", "I09"}, 1544 {"O12", "I22 Switch", "I22"}, 1545 {"O11", "I14 Switch", "I14"}, 1546 {"O12", "I15 Switch", "I15"}, 1547 {"O11", "I16 Switch", "I16"}, 1548 {"O12", "I17 Switch", "I17"}, 1549 {"O11", "I18 Switch", "I18"}, 1550 {"O12", "I19 Switch", "I19"}, 1551 {"O11", "I20 Switch", "I20"}, 1552 {"O12", "I21 Switch", "I21"}, 1553 1554 /* CM2_Mux*/ 1555 {"CM2_Mux IO", NULL, "CM2_Mux_IO Input Mux"}, 1556 1557 /* VUL2 */ 1558 {"VUL2", NULL, "VUL2 Input Mux"}, 1559 {"VUL2 Input Mux", "VUL2_IN_FROM_O17O18", "O17O18"}, 1560 {"VUL2 Input Mux", "VUL2_IN_FROM_CM1", "CM1_IO"}, 1561 1562 {"O17O18", NULL, "O17"}, 1563 {"O17O18", NULL, "O18"}, 1564 {"CM1_IO", NULL, "O17"}, 1565 {"CM1_IO", NULL, "O18"}, 1566 {"CM1_IO", NULL, "O19"}, 1567 {"CM1_IO", NULL, "O20"}, 1568 {"CM1_IO", NULL, "O21"}, 1569 {"CM1_IO", NULL, "O22"}, 1570 {"CM1_IO", NULL, "O23"}, 1571 {"CM1_IO", NULL, "O24"}, 1572 {"CM1_IO", NULL, "O25"}, 1573 {"CM1_IO", NULL, "O26"}, 1574 {"CM1_IO", NULL, "O31"}, 1575 {"CM1_IO", NULL, "O32"}, 1576 {"CM1_IO", NULL, "O33"}, 1577 {"CM1_IO", NULL, "O34"}, 1578 {"CM1_IO", NULL, "O35"}, 1579 {"CM1_IO", NULL, "O36"}, 1580 1581 {"O17", "I14 Switch", "I14"}, 1582 {"O18", "I15 Switch", "I15"}, 1583 {"O19", "I16 Switch", "I16"}, 1584 {"O20", "I17 Switch", "I17"}, 1585 {"O21", "I18 Switch", "I18"}, 1586 {"O22", "I19 Switch", "I19"}, 1587 {"O23", "I20 Switch", "I20"}, 1588 {"O24", "I21 Switch", "I21"}, 1589 {"O25", "I23 Switch", "I23"}, 1590 {"O26", "I24 Switch", "I24"}, 1591 {"O25", "I25 Switch", "I25"}, 1592 {"O26", "I26 Switch", "I26"}, 1593 1594 {"O17", "I03 Switch", "I03"}, 1595 {"O18", "I04 Switch", "I04"}, 1596 {"O18", "I23 Switch", "I23"}, 1597 {"O18", "I25 Switch", "I25"}, 1598 {"O19", "I04 Switch", "I04"}, 1599 {"O19", "I23 Switch", "I23"}, 1600 {"O19", "I24 Switch", "I24"}, 1601 {"O19", "I25 Switch", "I25"}, 1602 {"O19", "I26 Switch", "I26"}, 1603 {"O20", "I24 Switch", "I24"}, 1604 {"O20", "I26 Switch", "I26"}, 1605 {"O21", "I23 Switch", "I23"}, 1606 {"O21", "I25 Switch", "I25"}, 1607 {"O22", "I24 Switch", "I24"}, 1608 {"O22", "I26 Switch", "I26"}, 1609 1610 {"O23", "I23 Switch", "I23"}, 1611 {"O23", "I25 Switch", "I25"}, 1612 {"O24", "I24 Switch", "I24"}, 1613 {"O24", "I26 Switch", "I26"}, 1614 {"O24", "I23 Switch", "I23"}, 1615 {"O24", "I25 Switch", "I25"}, 1616 {"O13", "I00 Switch", "I00"}, 1617 {"O14", "I01 Switch", "I01"}, 1618 {"O03", "I10 Switch", "I10"}, 1619 {"O04", "I11 Switch", "I11"}, 1620 }; 1621 1622 static const struct mtk_base_memif_data memif_data[MT8365_AFE_MEMIF_NUM] = { 1623 { 1624 .name = "DL1", 1625 .id = MT8365_AFE_MEMIF_DL1, 1626 .reg_ofs_base = AFE_DL1_BASE, 1627 .reg_ofs_cur = AFE_DL1_CUR, 1628 .fs_reg = AFE_DAC_CON1, 1629 .fs_shift = 0, 1630 .fs_maskbit = 0xf, 1631 .mono_reg = AFE_DAC_CON1, 1632 .mono_shift = 21, 1633 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1634 .hd_shift = 16, 1635 .enable_reg = AFE_DAC_CON0, 1636 .enable_shift = 1, 1637 .msb_reg = -1, 1638 .msb_shift = -1, 1639 .agent_disable_reg = -1, 1640 .agent_disable_shift = -1, 1641 }, { 1642 .name = "DL2", 1643 .id = MT8365_AFE_MEMIF_DL2, 1644 .reg_ofs_base = AFE_DL2_BASE, 1645 .reg_ofs_cur = AFE_DL2_CUR, 1646 .fs_reg = AFE_DAC_CON1, 1647 .fs_shift = 4, 1648 .fs_maskbit = 0xf, 1649 .mono_reg = AFE_DAC_CON1, 1650 .mono_shift = 22, 1651 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1652 .hd_shift = 18, 1653 .enable_reg = AFE_DAC_CON0, 1654 .enable_shift = 2, 1655 .msb_reg = -1, 1656 .msb_shift = -1, 1657 .agent_disable_reg = -1, 1658 .agent_disable_shift = -1, 1659 }, { 1660 .name = "TDM OUT", 1661 .id = MT8365_AFE_MEMIF_TDM_OUT, 1662 .reg_ofs_base = AFE_HDMI_OUT_BASE, 1663 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 1664 .fs_reg = -1, 1665 .fs_shift = -1, 1666 .fs_maskbit = -1, 1667 .mono_reg = -1, 1668 .mono_shift = -1, 1669 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1670 .hd_shift = 28, 1671 .enable_reg = AFE_HDMI_OUT_CON0, 1672 .enable_shift = 0, 1673 .msb_reg = -1, 1674 .msb_shift = -1, 1675 .agent_disable_reg = -1, 1676 .agent_disable_shift = -1, 1677 }, { 1678 .name = "AWB", 1679 .id = MT8365_AFE_MEMIF_AWB, 1680 .reg_ofs_base = AFE_AWB_BASE, 1681 .reg_ofs_cur = AFE_AWB_CUR, 1682 .fs_reg = AFE_DAC_CON1, 1683 .fs_shift = 12, 1684 .fs_maskbit = 0xf, 1685 .mono_reg = AFE_DAC_CON1, 1686 .mono_shift = 24, 1687 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1688 .hd_shift = 20, 1689 .enable_reg = AFE_DAC_CON0, 1690 .enable_shift = 6, 1691 .msb_reg = AFE_MEMIF_MSB, 1692 .msb_shift = 17, 1693 .agent_disable_reg = -1, 1694 .agent_disable_shift = -1, 1695 }, { 1696 .name = "VUL", 1697 .id = MT8365_AFE_MEMIF_VUL, 1698 .reg_ofs_base = AFE_VUL_BASE, 1699 .reg_ofs_cur = AFE_VUL_CUR, 1700 .fs_reg = AFE_DAC_CON1, 1701 .fs_shift = 16, 1702 .fs_maskbit = 0xf, 1703 .mono_reg = AFE_DAC_CON1, 1704 .mono_shift = 27, 1705 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1706 .hd_shift = 22, 1707 .enable_reg = AFE_DAC_CON0, 1708 .enable_shift = 3, 1709 .msb_reg = AFE_MEMIF_MSB, 1710 .msb_shift = 20, 1711 .agent_disable_reg = -1, 1712 .agent_disable_shift = -1, 1713 }, { 1714 .name = "VUL2", 1715 .id = MT8365_AFE_MEMIF_VUL2, 1716 .reg_ofs_base = AFE_VUL_D2_BASE, 1717 .reg_ofs_cur = AFE_VUL_D2_CUR, 1718 .fs_reg = AFE_DAC_CON0, 1719 .fs_shift = 20, 1720 .fs_maskbit = 0xf, 1721 .mono_reg = -1, 1722 .mono_shift = -1, 1723 .hd_reg = AFE_MEMIF_PBUF_SIZE, 1724 .hd_shift = 14, 1725 .enable_reg = AFE_DAC_CON0, 1726 .enable_shift = 9, 1727 .msb_reg = AFE_MEMIF_MSB, 1728 .msb_shift = 21, 1729 .agent_disable_reg = -1, 1730 .agent_disable_shift = -1, 1731 }, { 1732 .name = "VUL3", 1733 .id = MT8365_AFE_MEMIF_VUL3, 1734 .reg_ofs_base = AFE_VUL3_BASE, 1735 .reg_ofs_cur = AFE_VUL3_CUR, 1736 .fs_reg = AFE_DAC_CON1, 1737 .fs_shift = 8, 1738 .fs_maskbit = 0xf, 1739 .mono_reg = AFE_DAC_CON0, 1740 .mono_shift = 13, 1741 .hd_reg = AFE_MEMIF_PBUF2_SIZE, 1742 .hd_shift = 10, 1743 .enable_reg = AFE_DAC_CON0, 1744 .enable_shift = 12, 1745 .msb_reg = AFE_MEMIF_MSB, 1746 .msb_shift = 27, 1747 .agent_disable_reg = -1, 1748 .agent_disable_shift = -1, 1749 }, { 1750 .name = "TDM IN", 1751 .id = MT8365_AFE_MEMIF_TDM_IN, 1752 .reg_ofs_base = AFE_HDMI_IN_2CH_BASE, 1753 .reg_ofs_cur = AFE_HDMI_IN_2CH_CUR, 1754 .fs_reg = -1, 1755 .fs_shift = -1, 1756 .fs_maskbit = -1, 1757 .mono_reg = AFE_HDMI_IN_2CH_CON0, 1758 .mono_shift = 1, 1759 .hd_reg = AFE_MEMIF_PBUF2_SIZE, 1760 .hd_shift = 8, 1761 .hd_align_mshift = 5, 1762 .enable_reg = AFE_HDMI_IN_2CH_CON0, 1763 .enable_shift = 0, 1764 .msb_reg = AFE_MEMIF_MSB, 1765 .msb_shift = 28, 1766 .agent_disable_reg = -1, 1767 .agent_disable_shift = -1, 1768 }, 1769 }; 1770 1771 static const struct mtk_base_irq_data irq_data[MT8365_AFE_IRQ_NUM] = { 1772 { 1773 .id = MT8365_AFE_IRQ1, 1774 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 1775 .irq_cnt_shift = 0, 1776 .irq_cnt_maskbit = 0x3ffff, 1777 .irq_en_reg = AFE_IRQ_MCU_CON, 1778 .irq_en_shift = 0, 1779 .irq_fs_reg = AFE_IRQ_MCU_CON, 1780 .irq_fs_shift = 4, 1781 .irq_fs_maskbit = 0xf, 1782 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1783 .irq_clr_shift = 0, 1784 }, { 1785 .id = MT8365_AFE_IRQ2, 1786 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 1787 .irq_cnt_shift = 0, 1788 .irq_cnt_maskbit = 0x3ffff, 1789 .irq_en_reg = AFE_IRQ_MCU_CON, 1790 .irq_en_shift = 1, 1791 .irq_fs_reg = AFE_IRQ_MCU_CON, 1792 .irq_fs_shift = 8, 1793 .irq_fs_maskbit = 0xf, 1794 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1795 .irq_clr_shift = 1, 1796 }, { 1797 .id = MT8365_AFE_IRQ3, 1798 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 1799 .irq_cnt_shift = 0, 1800 .irq_cnt_maskbit = 0x3ffff, 1801 .irq_en_reg = AFE_IRQ_MCU_CON, 1802 .irq_en_shift = 2, 1803 .irq_fs_reg = AFE_IRQ_MCU_CON, 1804 .irq_fs_shift = 16, 1805 .irq_fs_maskbit = 0xf, 1806 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1807 .irq_clr_shift = 2, 1808 }, { 1809 .id = MT8365_AFE_IRQ4, 1810 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 1811 .irq_cnt_shift = 0, 1812 .irq_cnt_maskbit = 0x3ffff, 1813 .irq_en_reg = AFE_IRQ_MCU_CON, 1814 .irq_en_shift = 3, 1815 .irq_fs_reg = AFE_IRQ_MCU_CON, 1816 .irq_fs_shift = 20, 1817 .irq_fs_maskbit = 0xf, 1818 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1819 .irq_clr_shift = 3, 1820 }, { 1821 .id = MT8365_AFE_IRQ5, 1822 .irq_cnt_reg = AFE_IRQ_MCU_CNT5, 1823 .irq_cnt_shift = 0, 1824 .irq_cnt_maskbit = 0x3ffff, 1825 .irq_en_reg = AFE_IRQ_MCU_CON2, 1826 .irq_en_shift = 3, 1827 .irq_fs_reg = -1, 1828 .irq_fs_shift = 0, 1829 .irq_fs_maskbit = 0x0, 1830 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1831 .irq_clr_shift = 4, 1832 }, { 1833 .id = MT8365_AFE_IRQ6, 1834 .irq_cnt_reg = -1, 1835 .irq_cnt_shift = 0, 1836 .irq_cnt_maskbit = 0x0, 1837 .irq_en_reg = AFE_IRQ_MCU_CON, 1838 .irq_en_shift = 13, 1839 .irq_fs_reg = -1, 1840 .irq_fs_shift = 0, 1841 .irq_fs_maskbit = 0x0, 1842 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1843 .irq_clr_shift = 5, 1844 }, { 1845 .id = MT8365_AFE_IRQ7, 1846 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 1847 .irq_cnt_shift = 0, 1848 .irq_cnt_maskbit = 0x3ffff, 1849 .irq_en_reg = AFE_IRQ_MCU_CON, 1850 .irq_en_shift = 14, 1851 .irq_fs_reg = AFE_IRQ_MCU_CON, 1852 .irq_fs_shift = 24, 1853 .irq_fs_maskbit = 0xf, 1854 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1855 .irq_clr_shift = 6, 1856 }, { 1857 .id = MT8365_AFE_IRQ8, 1858 .irq_cnt_reg = AFE_IRQ_MCU_CNT8, 1859 .irq_cnt_shift = 0, 1860 .irq_cnt_maskbit = 0x3ffff, 1861 .irq_en_reg = AFE_IRQ_MCU_CON, 1862 .irq_en_shift = 15, 1863 .irq_fs_reg = AFE_IRQ_MCU_CON, 1864 .irq_fs_shift = 28, 1865 .irq_fs_maskbit = 0xf, 1866 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1867 .irq_clr_shift = 7, 1868 }, { 1869 .id = MT8365_AFE_IRQ9, 1870 .irq_cnt_reg = -1, 1871 .irq_cnt_shift = 0, 1872 .irq_cnt_maskbit = 0x0, 1873 .irq_en_reg = AFE_IRQ_MCU_CON2, 1874 .irq_en_shift = 2, 1875 .irq_fs_reg = -1, 1876 .irq_fs_shift = 0, 1877 .irq_fs_maskbit = 0x0, 1878 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1879 .irq_clr_shift = 8, 1880 }, { 1881 .id = MT8365_AFE_IRQ10, 1882 .irq_cnt_reg = AFE_IRQ_MCU_CNT10, 1883 .irq_cnt_shift = 0, 1884 .irq_cnt_maskbit = 0x3ffff, 1885 .irq_en_reg = AFE_IRQ_MCU_CON2, 1886 .irq_en_shift = 4, 1887 .irq_fs_reg = -1, 1888 .irq_fs_shift = 0, 1889 .irq_fs_maskbit = 0x0, 1890 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1891 .irq_clr_shift = 9, 1892 }, 1893 }; 1894 1895 static int memif_specified_irqs[MT8365_AFE_MEMIF_NUM] = { 1896 [MT8365_AFE_MEMIF_DL1] = MT8365_AFE_IRQ1, 1897 [MT8365_AFE_MEMIF_DL2] = MT8365_AFE_IRQ2, 1898 [MT8365_AFE_MEMIF_TDM_OUT] = MT8365_AFE_IRQ5, 1899 [MT8365_AFE_MEMIF_AWB] = MT8365_AFE_IRQ3, 1900 [MT8365_AFE_MEMIF_VUL] = MT8365_AFE_IRQ4, 1901 [MT8365_AFE_MEMIF_VUL2] = MT8365_AFE_IRQ7, 1902 [MT8365_AFE_MEMIF_VUL3] = MT8365_AFE_IRQ8, 1903 [MT8365_AFE_MEMIF_TDM_IN] = MT8365_AFE_IRQ10, 1904 }; 1905 1906 static const struct regmap_config mt8365_afe_regmap_config = { 1907 .reg_bits = 32, 1908 .reg_stride = 4, 1909 .val_bits = 32, 1910 .max_register = MAX_REGISTER, 1911 .cache_type = REGCACHE_NONE, 1912 }; 1913 1914 static irqreturn_t mt8365_afe_irq_handler(int irq, void *dev_id) 1915 { 1916 struct mtk_base_afe *afe = dev_id; 1917 unsigned int reg_value; 1918 unsigned int mcu_irq_mask; 1919 int i, ret; 1920 1921 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, ®_value); 1922 if (ret) { 1923 dev_err_ratelimited(afe->dev, "%s irq status err\n", __func__); 1924 reg_value = AFE_IRQ_STATUS_BITS; 1925 goto err_irq; 1926 } 1927 1928 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_irq_mask); 1929 if (ret) { 1930 dev_err_ratelimited(afe->dev, "%s irq mcu_en err\n", __func__); 1931 reg_value = AFE_IRQ_STATUS_BITS; 1932 goto err_irq; 1933 } 1934 1935 /* only clr cpu irq */ 1936 reg_value &= mcu_irq_mask; 1937 1938 for (i = 0; i < MT8365_AFE_MEMIF_NUM; i++) { 1939 struct mtk_base_afe_memif *memif = &afe->memif[i]; 1940 struct mtk_base_afe_irq *mcu_irq; 1941 1942 if (memif->irq_usage < 0) 1943 continue; 1944 1945 mcu_irq = &afe->irqs[memif->irq_usage]; 1946 1947 if (!(reg_value & (1 << mcu_irq->irq_data->irq_clr_shift))) 1948 continue; 1949 1950 snd_pcm_period_elapsed(memif->substream); 1951 } 1952 1953 err_irq: 1954 /* clear irq */ 1955 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 1956 reg_value & AFE_IRQ_STATUS_BITS); 1957 1958 return IRQ_HANDLED; 1959 } 1960 1961 static int __maybe_unused mt8365_afe_runtime_suspend(struct device *dev) 1962 { 1963 return 0; 1964 } 1965 1966 static int mt8365_afe_runtime_resume(struct device *dev) 1967 { 1968 return 0; 1969 } 1970 1971 static int __maybe_unused mt8365_afe_suspend(struct device *dev) 1972 { 1973 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1974 struct regmap *regmap = afe->regmap; 1975 int i; 1976 1977 mt8365_afe_enable_main_clk(afe); 1978 1979 if (!afe->reg_back_up) 1980 afe->reg_back_up = 1981 devm_kcalloc(dev, afe->reg_back_up_list_num, 1982 sizeof(unsigned int), GFP_KERNEL); 1983 1984 for (i = 0; i < afe->reg_back_up_list_num; i++) 1985 regmap_read(regmap, afe->reg_back_up_list[i], 1986 &afe->reg_back_up[i]); 1987 1988 mt8365_afe_disable_main_clk(afe); 1989 1990 return 0; 1991 } 1992 1993 static int __maybe_unused mt8365_afe_resume(struct device *dev) 1994 { 1995 struct mtk_base_afe *afe = dev_get_drvdata(dev); 1996 struct regmap *regmap = afe->regmap; 1997 int i = 0; 1998 1999 if (!afe->reg_back_up) 2000 return 0; 2001 2002 mt8365_afe_enable_main_clk(afe); 2003 2004 for (i = 0; i < afe->reg_back_up_list_num; i++) 2005 regmap_write(regmap, afe->reg_back_up_list[i], 2006 afe->reg_back_up[i]); 2007 2008 mt8365_afe_disable_main_clk(afe); 2009 2010 return 0; 2011 } 2012 2013 static int __maybe_unused mt8365_afe_dev_runtime_suspend(struct device *dev) 2014 { 2015 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2016 2017 if (pm_runtime_status_suspended(dev) || afe->suspended) 2018 return 0; 2019 2020 mt8365_afe_suspend(dev); 2021 afe->suspended = true; 2022 return 0; 2023 } 2024 2025 static int __maybe_unused mt8365_afe_dev_runtime_resume(struct device *dev) 2026 { 2027 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2028 2029 if (pm_runtime_status_suspended(dev) || !afe->suspended) 2030 return 0; 2031 2032 mt8365_afe_resume(dev); 2033 afe->suspended = false; 2034 return 0; 2035 } 2036 2037 static int mt8365_afe_init_registers(struct mtk_base_afe *afe) 2038 { 2039 size_t i; 2040 2041 static struct { 2042 unsigned int reg; 2043 unsigned int mask; 2044 unsigned int val; 2045 } init_regs[] = { 2046 { AFE_CONN_24BIT, GENMASK(31, 0), GENMASK(31, 0) }, 2047 { AFE_CONN_24BIT_1, GENMASK(21, 0), GENMASK(21, 0) }, 2048 }; 2049 2050 mt8365_afe_enable_main_clk(afe); 2051 2052 for (i = 0; i < ARRAY_SIZE(init_regs); i++) 2053 regmap_update_bits(afe->regmap, init_regs[i].reg, 2054 init_regs[i].mask, init_regs[i].val); 2055 2056 mt8365_afe_disable_main_clk(afe); 2057 2058 return 0; 2059 } 2060 2061 static int mt8365_dai_memif_register(struct mtk_base_afe *afe) 2062 { 2063 struct mtk_base_afe_dai *dai; 2064 2065 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2066 if (!dai) 2067 return -ENOMEM; 2068 2069 list_add(&dai->list, &afe->sub_dais); 2070 2071 dai->dai_drivers = mt8365_memif_dai_driver; 2072 dai->num_dai_drivers = ARRAY_SIZE(mt8365_memif_dai_driver); 2073 2074 dai->dapm_widgets = mt8365_memif_widgets; 2075 dai->num_dapm_widgets = ARRAY_SIZE(mt8365_memif_widgets); 2076 dai->dapm_routes = mt8365_memif_routes; 2077 dai->num_dapm_routes = ARRAY_SIZE(mt8365_memif_routes); 2078 return 0; 2079 } 2080 2081 typedef int (*dai_register_cb)(struct mtk_base_afe *); 2082 static const dai_register_cb dai_register_cbs[] = { 2083 mt8365_dai_pcm_register, 2084 mt8365_dai_i2s_register, 2085 mt8365_dai_adda_register, 2086 mt8365_dai_dmic_register, 2087 mt8365_dai_memif_register, 2088 }; 2089 2090 static int mt8365_afe_pcm_dev_probe(struct platform_device *pdev) 2091 { 2092 struct mtk_base_afe *afe; 2093 struct mt8365_afe_private *afe_priv; 2094 struct device *dev; 2095 int ret, i, sel_irq; 2096 unsigned int irq_id; 2097 struct resource *res; 2098 2099 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 2100 if (!afe) 2101 return -ENOMEM; 2102 platform_set_drvdata(pdev, afe); 2103 2104 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 2105 GFP_KERNEL); 2106 if (!afe->platform_priv) 2107 return -ENOMEM; 2108 2109 afe_priv = afe->platform_priv; 2110 afe->dev = &pdev->dev; 2111 dev = afe->dev; 2112 2113 spin_lock_init(&afe_priv->afe_ctrl_lock); 2114 mutex_init(&afe_priv->afe_clk_mutex); 2115 2116 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2117 afe->base_addr = devm_ioremap_resource(&pdev->dev, res); 2118 if (IS_ERR(afe->base_addr)) 2119 return PTR_ERR(afe->base_addr); 2120 2121 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2122 if (res) { 2123 afe_priv->afe_sram_vir_addr = 2124 devm_ioremap_resource(&pdev->dev, res); 2125 if (!IS_ERR(afe_priv->afe_sram_vir_addr)) { 2126 afe_priv->afe_sram_phy_addr = res->start; 2127 afe_priv->afe_sram_size = resource_size(res); 2128 } 2129 } 2130 2131 /* initial audio related clock */ 2132 ret = mt8365_afe_init_audio_clk(afe); 2133 if (ret) 2134 return dev_err_probe(afe->dev, ret, "mt8365_afe_init_audio_clk fail\n"); 2135 2136 afe->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "top_audio_sel", 2137 afe->base_addr, 2138 &mt8365_afe_regmap_config); 2139 if (IS_ERR(afe->regmap)) 2140 return PTR_ERR(afe->regmap); 2141 2142 /* memif % irq initialize*/ 2143 afe->memif_size = MT8365_AFE_MEMIF_NUM; 2144 afe->memif = devm_kcalloc(afe->dev, afe->memif_size, 2145 sizeof(*afe->memif), GFP_KERNEL); 2146 if (!afe->memif) 2147 return -ENOMEM; 2148 2149 afe->irqs_size = MT8365_AFE_IRQ_NUM; 2150 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size, 2151 sizeof(*afe->irqs), GFP_KERNEL); 2152 if (!afe->irqs) 2153 return -ENOMEM; 2154 2155 for (i = 0; i < afe->irqs_size; i++) 2156 afe->irqs[i].irq_data = &irq_data[i]; 2157 2158 irq_id = platform_get_irq(pdev, 0); 2159 if (!irq_id) { 2160 dev_err_probe(afe->dev, irq_id, "np %s no irq\n", afe->dev->of_node->name); 2161 return -ENXIO; 2162 } 2163 ret = devm_request_irq(afe->dev, irq_id, mt8365_afe_irq_handler, 2164 0, "Afe_ISR_Handle", (void *)afe); 2165 if (ret) 2166 return dev_err_probe(afe->dev, ret, "could not request_irq\n"); 2167 2168 /* init sub_dais */ 2169 INIT_LIST_HEAD(&afe->sub_dais); 2170 2171 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 2172 ret = dai_register_cbs[i](afe); 2173 if (ret) { 2174 dev_warn(afe->dev, "dai register i %d fail, ret %d\n", 2175 i, ret); 2176 return ret; 2177 } 2178 } 2179 2180 /* init dai_driver and component_driver */ 2181 ret = mtk_afe_combine_sub_dai(afe); 2182 if (ret) { 2183 dev_warn(afe->dev, "mtk_afe_combine_sub_dai fail, ret %d\n", 2184 ret); 2185 return ret; 2186 } 2187 2188 for (i = 0; i < afe->memif_size; i++) { 2189 afe->memif[i].data = &memif_data[i]; 2190 sel_irq = memif_specified_irqs[i]; 2191 if (sel_irq >= 0) { 2192 afe->memif[i].irq_usage = sel_irq; 2193 afe->memif[i].const_irq = 1; 2194 afe->irqs[sel_irq].irq_occupyed = true; 2195 } else { 2196 afe->memif[i].irq_usage = -1; 2197 } 2198 } 2199 2200 afe->mtk_afe_hardware = &mt8365_afe_hardware; 2201 afe->memif_fs = mt8365_memif_fs; 2202 afe->irq_fs = mt8365_irq_fs; 2203 2204 ret = devm_pm_runtime_enable(&pdev->dev); 2205 if (ret) 2206 return ret; 2207 2208 pm_runtime_get_sync(&pdev->dev); 2209 afe->reg_back_up_list = mt8365_afe_backup_list; 2210 afe->reg_back_up_list_num = ARRAY_SIZE(mt8365_afe_backup_list); 2211 afe->runtime_resume = mt8365_afe_runtime_resume; 2212 afe->runtime_suspend = mt8365_afe_runtime_suspend; 2213 2214 /* open afe pdn for dapm read/write audio register */ 2215 mt8365_afe_enable_top_cg(afe, MT8365_TOP_CG_AFE); 2216 2217 /* Set 26m parent clk */ 2218 mt8365_afe_set_clk_parent(afe, 2219 afe_priv->clocks[MT8365_CLK_TOP_AUD_SEL], 2220 afe_priv->clocks[MT8365_CLK_CLK26M]); 2221 2222 ret = devm_snd_soc_register_component(&pdev->dev, 2223 &mtk_afe_pcm_platform, 2224 afe->dai_drivers, 2225 afe->num_dai_drivers); 2226 if (ret) { 2227 dev_warn(dev, "err_platform\n"); 2228 return ret; 2229 } 2230 2231 mt8365_afe_init_registers(afe); 2232 2233 return 0; 2234 } 2235 2236 static void mt8365_afe_pcm_dev_remove(struct platform_device *pdev) 2237 { 2238 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 2239 2240 mt8365_afe_disable_top_cg(afe, MT8365_TOP_CG_AFE); 2241 2242 pm_runtime_disable(&pdev->dev); 2243 if (!pm_runtime_status_suspended(&pdev->dev)) 2244 mt8365_afe_runtime_suspend(&pdev->dev); 2245 } 2246 2247 static const struct of_device_id mt8365_afe_pcm_dt_match[] = { 2248 { .compatible = "mediatek,mt8365-afe-pcm", }, 2249 { } 2250 }; 2251 MODULE_DEVICE_TABLE(of, mt8365_afe_pcm_dt_match); 2252 2253 static const struct dev_pm_ops mt8365_afe_pm_ops = { 2254 SET_RUNTIME_PM_OPS(mt8365_afe_dev_runtime_suspend, 2255 mt8365_afe_dev_runtime_resume, NULL) 2256 SET_SYSTEM_SLEEP_PM_OPS(mt8365_afe_suspend, 2257 mt8365_afe_resume) 2258 }; 2259 2260 static struct platform_driver mt8365_afe_pcm_driver = { 2261 .driver = { 2262 .name = "mt8365-afe-pcm", 2263 .of_match_table = mt8365_afe_pcm_dt_match, 2264 .pm = &mt8365_afe_pm_ops, 2265 }, 2266 .probe = mt8365_afe_pcm_dev_probe, 2267 .remove_new = mt8365_afe_pcm_dev_remove, 2268 }; 2269 2270 module_platform_driver(mt8365_afe_pcm_driver); 2271 2272 MODULE_DESCRIPTION("MediaTek ALSA SoC AFE platform driver"); 2273 MODULE_AUTHOR("Jia Zeng <jia.zeng@mediatek.com>"); 2274 MODULE_AUTHOR("Alexandre Mergnat <amergnat@baylibre.com>"); 2275 MODULE_LICENSE("GPL"); 2276