11de9a54aSTrevor Wu // SPDX-License-Identifier: GPL-2.0 21de9a54aSTrevor Wu /* 31de9a54aSTrevor Wu * MediaTek ALSA SoC Audio DAI eTDM Control 41de9a54aSTrevor Wu * 51de9a54aSTrevor Wu * Copyright (c) 2021 MediaTek Inc. 61de9a54aSTrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 71de9a54aSTrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 81de9a54aSTrevor Wu */ 91de9a54aSTrevor Wu 101de9a54aSTrevor Wu #include <linux/delay.h> 111de9a54aSTrevor Wu #include <linux/pm_runtime.h> 121de9a54aSTrevor Wu #include <linux/regmap.h> 131de9a54aSTrevor Wu #include <sound/pcm_params.h> 141de9a54aSTrevor Wu #include "mt8195-afe-clk.h" 151de9a54aSTrevor Wu #include "mt8195-afe-common.h" 161de9a54aSTrevor Wu #include "mt8195-reg.h" 171de9a54aSTrevor Wu 181de9a54aSTrevor Wu #define MT8195_ETDM_MAX_CHANNELS 24 191de9a54aSTrevor Wu #define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000 201de9a54aSTrevor Wu #define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START) 211de9a54aSTrevor Wu #define ENUM_TO_STR(x) #x 221de9a54aSTrevor Wu 231de9a54aSTrevor Wu enum { 241de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_I2S = 0, 251de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_LJ, 261de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_RJ, 271de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_EIAJ, 281de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_DSPA, 291de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_DSPB, 301de9a54aSTrevor Wu }; 311de9a54aSTrevor Wu 321de9a54aSTrevor Wu enum { 331de9a54aSTrevor Wu MTK_DAI_ETDM_DATA_ONE_PIN = 0, 341de9a54aSTrevor Wu MTK_DAI_ETDM_DATA_MULTI_PIN, 351de9a54aSTrevor Wu }; 361de9a54aSTrevor Wu 371de9a54aSTrevor Wu enum { 381de9a54aSTrevor Wu ETDM_IN, 391de9a54aSTrevor Wu ETDM_OUT, 401de9a54aSTrevor Wu }; 411de9a54aSTrevor Wu 421de9a54aSTrevor Wu enum { 431de9a54aSTrevor Wu ETDM_IN_FROM_PAD, 441de9a54aSTrevor Wu ETDM_IN_FROM_ETDM_OUT1, 451de9a54aSTrevor Wu ETDM_IN_FROM_ETDM_OUT2, 461de9a54aSTrevor Wu }; 471de9a54aSTrevor Wu 481de9a54aSTrevor Wu enum { 491de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_PAD, 501de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_ETDM_OUT1, 511de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_ETDM_OUT2, 521de9a54aSTrevor Wu }; 531de9a54aSTrevor Wu 541de9a54aSTrevor Wu enum { 551de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_PAD, 561de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_ETDM_IN1, 571de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_ETDM_IN2, 581de9a54aSTrevor Wu }; 591de9a54aSTrevor Wu 601de9a54aSTrevor Wu enum { 611de9a54aSTrevor Wu COWORK_ETDM_NONE = 0, 621de9a54aSTrevor Wu COWORK_ETDM_IN1_M = 2, 631de9a54aSTrevor Wu COWORK_ETDM_IN1_S = 3, 641de9a54aSTrevor Wu COWORK_ETDM_IN2_M = 4, 651de9a54aSTrevor Wu COWORK_ETDM_IN2_S = 5, 661de9a54aSTrevor Wu COWORK_ETDM_OUT1_M = 10, 671de9a54aSTrevor Wu COWORK_ETDM_OUT1_S = 11, 681de9a54aSTrevor Wu COWORK_ETDM_OUT2_M = 12, 691de9a54aSTrevor Wu COWORK_ETDM_OUT2_S = 13, 701de9a54aSTrevor Wu COWORK_ETDM_OUT3_M = 14, 711de9a54aSTrevor Wu COWORK_ETDM_OUT3_S = 15, 721de9a54aSTrevor Wu }; 731de9a54aSTrevor Wu 741de9a54aSTrevor Wu enum { 751de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A1A2SYS, 761de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A3SYS, 771de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A4SYS, 781de9a54aSTrevor Wu }; 791de9a54aSTrevor Wu 801de9a54aSTrevor Wu enum { 811de9a54aSTrevor Wu ETDM_SYNC_NONE, 821de9a54aSTrevor Wu ETDM_SYNC_FROM_IN1, 831de9a54aSTrevor Wu ETDM_SYNC_FROM_IN2, 841de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT1, 851de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT2, 861de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT3, 871de9a54aSTrevor Wu }; 881de9a54aSTrevor Wu 891de9a54aSTrevor Wu struct etdm_con_reg { 901de9a54aSTrevor Wu unsigned int con0; 911de9a54aSTrevor Wu unsigned int con1; 921de9a54aSTrevor Wu unsigned int con2; 931de9a54aSTrevor Wu unsigned int con3; 941de9a54aSTrevor Wu unsigned int con4; 951de9a54aSTrevor Wu unsigned int con5; 961de9a54aSTrevor Wu }; 971de9a54aSTrevor Wu 981de9a54aSTrevor Wu struct mtk_dai_etdm_rate { 991de9a54aSTrevor Wu unsigned int rate; 1001de9a54aSTrevor Wu unsigned int reg_value; 1011de9a54aSTrevor Wu }; 1021de9a54aSTrevor Wu 1031de9a54aSTrevor Wu struct mtk_dai_etdm_priv { 1041de9a54aSTrevor Wu unsigned int clock_mode; 1051de9a54aSTrevor Wu unsigned int data_mode; 1061de9a54aSTrevor Wu bool slave_mode; 1071de9a54aSTrevor Wu bool lrck_inv; 1081de9a54aSTrevor Wu bool bck_inv; 1091de9a54aSTrevor Wu unsigned int format; 1101de9a54aSTrevor Wu unsigned int slots; 1111de9a54aSTrevor Wu unsigned int lrck_width; 1121de9a54aSTrevor Wu unsigned int mclk_freq; 1131de9a54aSTrevor Wu unsigned int mclk_apll; 1141de9a54aSTrevor Wu unsigned int mclk_dir; 1151de9a54aSTrevor Wu int cowork_source_id; //dai id 1161de9a54aSTrevor Wu unsigned int cowork_slv_count; 1171de9a54aSTrevor Wu int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id 1181de9a54aSTrevor Wu bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS]; 1191de9a54aSTrevor Wu unsigned int en_ref_cnt; 1201de9a54aSTrevor Wu }; 1211de9a54aSTrevor Wu 1221de9a54aSTrevor Wu static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = { 1231de9a54aSTrevor Wu { .rate = 8000, .reg_value = 0, }, 1241de9a54aSTrevor Wu { .rate = 12000, .reg_value = 1, }, 1251de9a54aSTrevor Wu { .rate = 16000, .reg_value = 2, }, 1261de9a54aSTrevor Wu { .rate = 24000, .reg_value = 3, }, 1271de9a54aSTrevor Wu { .rate = 32000, .reg_value = 4, }, 1281de9a54aSTrevor Wu { .rate = 48000, .reg_value = 5, }, 1291de9a54aSTrevor Wu { .rate = 96000, .reg_value = 7, }, 1301de9a54aSTrevor Wu { .rate = 192000, .reg_value = 9, }, 1311de9a54aSTrevor Wu { .rate = 384000, .reg_value = 11, }, 1321de9a54aSTrevor Wu { .rate = 11025, .reg_value = 16, }, 1331de9a54aSTrevor Wu { .rate = 22050, .reg_value = 17, }, 1341de9a54aSTrevor Wu { .rate = 44100, .reg_value = 18, }, 1351de9a54aSTrevor Wu { .rate = 88200, .reg_value = 19, }, 1361de9a54aSTrevor Wu { .rate = 176400, .reg_value = 20, }, 1371de9a54aSTrevor Wu { .rate = 352800, .reg_value = 21, }, 1381de9a54aSTrevor Wu }; 1391de9a54aSTrevor Wu 1401de9a54aSTrevor Wu static int get_etdm_fs_timing(unsigned int rate) 1411de9a54aSTrevor Wu { 1421de9a54aSTrevor Wu int i; 1431de9a54aSTrevor Wu 1441de9a54aSTrevor Wu for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++) 1451de9a54aSTrevor Wu if (mt8195_etdm_rates[i].rate == rate) 1461de9a54aSTrevor Wu return mt8195_etdm_rates[i].reg_value; 1471de9a54aSTrevor Wu 1481de9a54aSTrevor Wu return -EINVAL; 1491de9a54aSTrevor Wu } 1501de9a54aSTrevor Wu 1511de9a54aSTrevor Wu static unsigned int get_etdm_ch_fixup(unsigned int channels) 1521de9a54aSTrevor Wu { 1531de9a54aSTrevor Wu if (channels > 16) 1541de9a54aSTrevor Wu return 24; 1551de9a54aSTrevor Wu else if (channels > 8) 1561de9a54aSTrevor Wu return 16; 1571de9a54aSTrevor Wu else if (channels > 4) 1581de9a54aSTrevor Wu return 8; 1591de9a54aSTrevor Wu else if (channels > 2) 1601de9a54aSTrevor Wu return 4; 1611de9a54aSTrevor Wu else 1621de9a54aSTrevor Wu return 2; 1631de9a54aSTrevor Wu } 1641de9a54aSTrevor Wu 1651de9a54aSTrevor Wu static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 1661de9a54aSTrevor Wu { 1671de9a54aSTrevor Wu switch (dai_id) { 1681de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1691de9a54aSTrevor Wu etdm_reg->con0 = ETDM_IN1_CON0; 1701de9a54aSTrevor Wu etdm_reg->con1 = ETDM_IN1_CON1; 1711de9a54aSTrevor Wu etdm_reg->con2 = ETDM_IN1_CON2; 1721de9a54aSTrevor Wu etdm_reg->con3 = ETDM_IN1_CON3; 1731de9a54aSTrevor Wu etdm_reg->con4 = ETDM_IN1_CON4; 1741de9a54aSTrevor Wu etdm_reg->con5 = ETDM_IN1_CON5; 1751de9a54aSTrevor Wu break; 1761de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1771de9a54aSTrevor Wu etdm_reg->con0 = ETDM_IN2_CON0; 1781de9a54aSTrevor Wu etdm_reg->con1 = ETDM_IN2_CON1; 1791de9a54aSTrevor Wu etdm_reg->con2 = ETDM_IN2_CON2; 1801de9a54aSTrevor Wu etdm_reg->con3 = ETDM_IN2_CON3; 1811de9a54aSTrevor Wu etdm_reg->con4 = ETDM_IN2_CON4; 1821de9a54aSTrevor Wu etdm_reg->con5 = ETDM_IN2_CON5; 1831de9a54aSTrevor Wu break; 1841de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1851de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT1_CON0; 1861de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT1_CON1; 1871de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT1_CON2; 1881de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT1_CON3; 1891de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT1_CON4; 1901de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT1_CON5; 1911de9a54aSTrevor Wu break; 1921de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1931de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT2_CON0; 1941de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT2_CON1; 1951de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT2_CON2; 1961de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT2_CON3; 1971de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT2_CON4; 1981de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT2_CON5; 1991de9a54aSTrevor Wu break; 2001de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 2011de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 2021de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT3_CON0; 2031de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT3_CON1; 2041de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT3_CON2; 2051de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT3_CON3; 2061de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT3_CON4; 2071de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT3_CON5; 2081de9a54aSTrevor Wu break; 2091de9a54aSTrevor Wu default: 2101de9a54aSTrevor Wu return -EINVAL; 2111de9a54aSTrevor Wu } 2121de9a54aSTrevor Wu return 0; 2131de9a54aSTrevor Wu } 2141de9a54aSTrevor Wu 2151de9a54aSTrevor Wu static int get_etdm_dir(unsigned int dai_id) 2161de9a54aSTrevor Wu { 2171de9a54aSTrevor Wu switch (dai_id) { 2181de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 2191de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 2201de9a54aSTrevor Wu return ETDM_IN; 2211de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 2221de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 2231de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 2241de9a54aSTrevor Wu return ETDM_OUT; 2251de9a54aSTrevor Wu default: 2261de9a54aSTrevor Wu return -EINVAL; 2271de9a54aSTrevor Wu } 2281de9a54aSTrevor Wu } 2291de9a54aSTrevor Wu 2301de9a54aSTrevor Wu static int get_etdm_wlen(unsigned int bitwidth) 2311de9a54aSTrevor Wu { 2321de9a54aSTrevor Wu return bitwidth <= 16 ? 16 : 32; 2331de9a54aSTrevor Wu } 2341de9a54aSTrevor Wu 2351de9a54aSTrevor Wu static int is_cowork_mode(struct snd_soc_dai *dai) 2361de9a54aSTrevor Wu { 2371de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2381de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2391de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2401de9a54aSTrevor Wu 2411de9a54aSTrevor Wu return (etdm_data->cowork_slv_count > 0 || 2421de9a54aSTrevor Wu etdm_data->cowork_source_id != COWORK_ETDM_NONE); 2431de9a54aSTrevor Wu } 2441de9a54aSTrevor Wu 2451de9a54aSTrevor Wu static int sync_to_dai_id(int source_sel) 2461de9a54aSTrevor Wu { 2471de9a54aSTrevor Wu switch (source_sel) { 2481de9a54aSTrevor Wu case ETDM_SYNC_FROM_IN1: 2491de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM1_IN; 2501de9a54aSTrevor Wu case ETDM_SYNC_FROM_IN2: 2511de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM2_IN; 2521de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT1: 2531de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM1_OUT; 2541de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT2: 2551de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM2_OUT; 2561de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT3: 2571de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM3_OUT; 2581de9a54aSTrevor Wu default: 2591de9a54aSTrevor Wu return 0; 2601de9a54aSTrevor Wu } 2611de9a54aSTrevor Wu } 2621de9a54aSTrevor Wu 2631de9a54aSTrevor Wu static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 2641de9a54aSTrevor Wu { 2651de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2661de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2671de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2681de9a54aSTrevor Wu int dai_id = etdm_data->cowork_source_id; 2691de9a54aSTrevor Wu 2701de9a54aSTrevor Wu if (dai_id == COWORK_ETDM_NONE) 2711de9a54aSTrevor Wu dai_id = dai->id; 2721de9a54aSTrevor Wu 2731de9a54aSTrevor Wu return dai_id; 2741de9a54aSTrevor Wu } 2751de9a54aSTrevor Wu 2761de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 2771de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 2781de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 2791de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 2801de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 2811de9a54aSTrevor Wu }; 2821de9a54aSTrevor Wu 2831de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 2841de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 2851de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 2861de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 2871de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 2881de9a54aSTrevor Wu }; 2891de9a54aSTrevor Wu 2901de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 2911de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 2921de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 2931de9a54aSTrevor Wu }; 2941de9a54aSTrevor Wu 2951de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 2961de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 2971de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 2981de9a54aSTrevor Wu }; 2991de9a54aSTrevor Wu 3001de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 3011de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 3021de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 3031de9a54aSTrevor Wu }; 3041de9a54aSTrevor Wu 3051de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 3061de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 3071de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 3081de9a54aSTrevor Wu }; 3091de9a54aSTrevor Wu 3101de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 3111de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 3121de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 3131de9a54aSTrevor Wu }; 3141de9a54aSTrevor Wu 3151de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 3161de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 3171de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 3181de9a54aSTrevor Wu }; 3191de9a54aSTrevor Wu 3201de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 3211de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 3221de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 3231de9a54aSTrevor Wu }; 3241de9a54aSTrevor Wu 3251de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 3261de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 3271de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 3281de9a54aSTrevor Wu }; 3291de9a54aSTrevor Wu 3301de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 3311de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 3321de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 3331de9a54aSTrevor Wu }; 3341de9a54aSTrevor Wu 3351de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 3361de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 3371de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 3381de9a54aSTrevor Wu }; 3391de9a54aSTrevor Wu 3401de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 3411de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 3421de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 3431de9a54aSTrevor Wu }; 3441de9a54aSTrevor Wu 3451de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 3461de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 3471de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 3481de9a54aSTrevor Wu }; 3491de9a54aSTrevor Wu 3501de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 3511de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 3521de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 3531de9a54aSTrevor Wu }; 3541de9a54aSTrevor Wu 3551de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 3561de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 3571de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 3581de9a54aSTrevor Wu }; 3591de9a54aSTrevor Wu 3601de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = { 3611de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0), 3621de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0), 3631de9a54aSTrevor Wu }; 3641de9a54aSTrevor Wu 3651de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = { 3661de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0), 3671de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0), 3681de9a54aSTrevor Wu }; 3691de9a54aSTrevor Wu 3701de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = { 3711de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0), 3721de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0), 3731de9a54aSTrevor Wu }; 3741de9a54aSTrevor Wu 3751de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = { 3761de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0), 3771de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0), 3781de9a54aSTrevor Wu }; 3791de9a54aSTrevor Wu 3801de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = { 3811de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0), 3821de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0), 3831de9a54aSTrevor Wu }; 3841de9a54aSTrevor Wu 3851de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = { 3861de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0), 3871de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0), 3881de9a54aSTrevor Wu }; 3891de9a54aSTrevor Wu 3901de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = { 3911de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0), 3921de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0), 3931de9a54aSTrevor Wu }; 3941de9a54aSTrevor Wu 3951de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = { 3961de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0), 3971de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0), 3981de9a54aSTrevor Wu }; 3991de9a54aSTrevor Wu 4001de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 4011de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 4021de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 4031de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 4041de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 4051de9a54aSTrevor Wu }; 4061de9a54aSTrevor Wu 4071de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 4081de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 4091de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 4101de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 4111de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 4121de9a54aSTrevor Wu }; 4131de9a54aSTrevor Wu 4141de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 4151de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 4161de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 4171de9a54aSTrevor Wu }; 4181de9a54aSTrevor Wu 4191de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 4201de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 4211de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 4221de9a54aSTrevor Wu }; 4231de9a54aSTrevor Wu 4241de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 4251de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 4261de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 4271de9a54aSTrevor Wu }; 4281de9a54aSTrevor Wu 4291de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 4301de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 4311de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 4321de9a54aSTrevor Wu }; 4331de9a54aSTrevor Wu 4341de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 4351de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 4361de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 4371de9a54aSTrevor Wu }; 4381de9a54aSTrevor Wu 4391de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 4401de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 4411de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 4421de9a54aSTrevor Wu }; 4431de9a54aSTrevor Wu 4441de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 4451de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 4461de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 4471de9a54aSTrevor Wu }; 4481de9a54aSTrevor Wu 4491de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 4501de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 4511de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 4521de9a54aSTrevor Wu }; 4531de9a54aSTrevor Wu 4541de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 4551de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 4561de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 4571de9a54aSTrevor Wu }; 4581de9a54aSTrevor Wu 4591de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 4601de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 4611de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 4621de9a54aSTrevor Wu }; 4631de9a54aSTrevor Wu 4641de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 4651de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 4661de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 4671de9a54aSTrevor Wu }; 4681de9a54aSTrevor Wu 4691de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 4701de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 4711de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 4721de9a54aSTrevor Wu }; 4731de9a54aSTrevor Wu 4741de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 4751de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 4761de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 4771de9a54aSTrevor Wu }; 4781de9a54aSTrevor Wu 4791de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 4801de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 4811de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 4821de9a54aSTrevor Wu }; 4831de9a54aSTrevor Wu 4841de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = { 4851de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0), 4861de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0), 4871de9a54aSTrevor Wu }; 4881de9a54aSTrevor Wu 4891de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = { 4901de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0), 4911de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0), 4921de9a54aSTrevor Wu }; 4931de9a54aSTrevor Wu 4941de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = { 4951de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0), 4961de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0), 4971de9a54aSTrevor Wu }; 4981de9a54aSTrevor Wu 4991de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = { 5001de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0), 5011de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0), 5021de9a54aSTrevor Wu }; 5031de9a54aSTrevor Wu 5041de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = { 5051de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0), 5061de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0), 5071de9a54aSTrevor Wu }; 5081de9a54aSTrevor Wu 5091de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = { 5101de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0), 5111de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0), 5121de9a54aSTrevor Wu }; 5131de9a54aSTrevor Wu 5141de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = { 5151de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0), 5161de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0), 5171de9a54aSTrevor Wu }; 5181de9a54aSTrevor Wu 5191de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = { 5201de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0), 5211de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0), 5221de9a54aSTrevor Wu }; 5231de9a54aSTrevor Wu 5241de9a54aSTrevor Wu static const char * const mt8195_etdm_clk_src_sel_text[] = { 5251de9a54aSTrevor Wu "26m", 5261de9a54aSTrevor Wu "a1sys_a2sys", 5271de9a54aSTrevor Wu "a3sys", 5281de9a54aSTrevor Wu "a4sys", 5291de9a54aSTrevor Wu }; 5301de9a54aSTrevor Wu 5311de9a54aSTrevor Wu static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 5321de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_text); 5331de9a54aSTrevor Wu 5341de9a54aSTrevor Wu static const char * const hdmitx_dptx_mux_map[] = { 5351de9a54aSTrevor Wu "Disconnect", "Connect", 5361de9a54aSTrevor Wu }; 5371de9a54aSTrevor Wu 5381de9a54aSTrevor Wu static int hdmitx_dptx_mux_map_value[] = { 5391de9a54aSTrevor Wu 0, 1, 5401de9a54aSTrevor Wu }; 5411de9a54aSTrevor Wu 5421de9a54aSTrevor Wu /* HDMI_OUT_MUX */ 5431de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 5441de9a54aSTrevor Wu SND_SOC_NOPM, 5451de9a54aSTrevor Wu 0, 5461de9a54aSTrevor Wu 1, 5471de9a54aSTrevor Wu hdmitx_dptx_mux_map, 5481de9a54aSTrevor Wu hdmitx_dptx_mux_map_value); 5491de9a54aSTrevor Wu 5501de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_out_mux_control = 5511de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 5521de9a54aSTrevor Wu 5531de9a54aSTrevor Wu /* DPTX_OUT_MUX */ 5541de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 5551de9a54aSTrevor Wu SND_SOC_NOPM, 5561de9a54aSTrevor Wu 0, 5571de9a54aSTrevor Wu 1, 5581de9a54aSTrevor Wu hdmitx_dptx_mux_map, 5591de9a54aSTrevor Wu hdmitx_dptx_mux_map_value); 5601de9a54aSTrevor Wu 5611de9a54aSTrevor Wu static const struct snd_kcontrol_new dptx_out_mux_control = 5621de9a54aSTrevor Wu SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 5631de9a54aSTrevor Wu 5641de9a54aSTrevor Wu /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 5651de9a54aSTrevor Wu static const char *const afe_conn_hdmi_mux_map[] = { 5661de9a54aSTrevor Wu "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 5671de9a54aSTrevor Wu }; 5681de9a54aSTrevor Wu 5691de9a54aSTrevor Wu static int afe_conn_hdmi_mux_map_value[] = { 5701de9a54aSTrevor Wu 0, 1, 2, 3, 4, 5, 6, 7, 5711de9a54aSTrevor Wu }; 5721de9a54aSTrevor Wu 5731de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 5741de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 5751de9a54aSTrevor Wu 0, 5761de9a54aSTrevor Wu 0xf, 5771de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 5781de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 5791de9a54aSTrevor Wu 5801de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch0_mux_control = 5811de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 5821de9a54aSTrevor Wu 5831de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 5841de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 5851de9a54aSTrevor Wu 4, 5861de9a54aSTrevor Wu 0xf, 5871de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 5881de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 5891de9a54aSTrevor Wu 5901de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch1_mux_control = 5911de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 5921de9a54aSTrevor Wu 5931de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 5941de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 5951de9a54aSTrevor Wu 8, 5961de9a54aSTrevor Wu 0xf, 5971de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 5981de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 5991de9a54aSTrevor Wu 6001de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch2_mux_control = 6011de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 6021de9a54aSTrevor Wu 6031de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 6041de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 6051de9a54aSTrevor Wu 12, 6061de9a54aSTrevor Wu 0xf, 6071de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 6081de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 6091de9a54aSTrevor Wu 6101de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch3_mux_control = 6111de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 6121de9a54aSTrevor Wu 6131de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 6141de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 6151de9a54aSTrevor Wu 16, 6161de9a54aSTrevor Wu 0xf, 6171de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 6181de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 6191de9a54aSTrevor Wu 6201de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch4_mux_control = 6211de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 6221de9a54aSTrevor Wu 6231de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 6241de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 6251de9a54aSTrevor Wu 20, 6261de9a54aSTrevor Wu 0xf, 6271de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 6281de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 6291de9a54aSTrevor Wu 6301de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch5_mux_control = 6311de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 6321de9a54aSTrevor Wu 6331de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 6341de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 6351de9a54aSTrevor Wu 24, 6361de9a54aSTrevor Wu 0xf, 6371de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 6381de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 6391de9a54aSTrevor Wu 6401de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch6_mux_control = 6411de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 6421de9a54aSTrevor Wu 6431de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 6441de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 6451de9a54aSTrevor Wu 28, 6461de9a54aSTrevor Wu 0xf, 6471de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 6481de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 6491de9a54aSTrevor Wu 6501de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch7_mux_control = 6511de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 6521de9a54aSTrevor Wu 6531de9a54aSTrevor Wu static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 6541de9a54aSTrevor Wu struct snd_ctl_elem_value *ucontrol) 6551de9a54aSTrevor Wu { 6561de9a54aSTrevor Wu struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 6571de9a54aSTrevor Wu struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 6581de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 6591de9a54aSTrevor Wu unsigned int source = ucontrol->value.enumerated.item[0]; 6601de9a54aSTrevor Wu unsigned int val; 6611de9a54aSTrevor Wu unsigned int mask; 6621de9a54aSTrevor Wu unsigned int reg; 6631de9a54aSTrevor Wu 6641de9a54aSTrevor Wu if (source >= e->items) 6651de9a54aSTrevor Wu return -EINVAL; 6661de9a54aSTrevor Wu 6671de9a54aSTrevor Wu reg = 0; 6681de9a54aSTrevor Wu if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 6691de9a54aSTrevor Wu reg = ETDM_OUT1_CON4; 6701de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 6711de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 6721de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 6731de9a54aSTrevor Wu reg = ETDM_OUT2_CON4; 6741de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 6751de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 6761de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 6771de9a54aSTrevor Wu reg = ETDM_OUT3_CON4; 6781de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 6791de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 6801de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 6811de9a54aSTrevor Wu reg = ETDM_IN1_CON2; 6821de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 6831de9a54aSTrevor Wu val = ETDM_IN_CON2_CLOCK(source); 6841de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 6851de9a54aSTrevor Wu reg = ETDM_IN2_CON2; 6861de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 6871de9a54aSTrevor Wu val = ETDM_IN_CON2_CLOCK(source); 6881de9a54aSTrevor Wu } 6891de9a54aSTrevor Wu 6901de9a54aSTrevor Wu if (reg) 6911de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 6921de9a54aSTrevor Wu 6931de9a54aSTrevor Wu return 0; 6941de9a54aSTrevor Wu } 6951de9a54aSTrevor Wu 6961de9a54aSTrevor Wu static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 6971de9a54aSTrevor Wu struct snd_ctl_elem_value *ucontrol) 6981de9a54aSTrevor Wu { 6991de9a54aSTrevor Wu struct snd_soc_component *component = 7001de9a54aSTrevor Wu snd_soc_kcontrol_component(kcontrol); 7011de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 7021de9a54aSTrevor Wu unsigned int value = 0; 7031de9a54aSTrevor Wu unsigned int reg = 0; 7041de9a54aSTrevor Wu unsigned int mask = 0; 7051de9a54aSTrevor Wu unsigned int shift = 0; 7061de9a54aSTrevor Wu 7071de9a54aSTrevor Wu if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 7081de9a54aSTrevor Wu reg = ETDM_OUT1_CON4; 7091de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 7101de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 7111de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 7121de9a54aSTrevor Wu reg = ETDM_OUT2_CON4; 7131de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 7141de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 7151de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 7161de9a54aSTrevor Wu reg = ETDM_OUT3_CON4; 7171de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 7181de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 7191de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 7201de9a54aSTrevor Wu reg = ETDM_IN1_CON2; 7211de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 7221de9a54aSTrevor Wu shift = ETDM_IN_CON2_CLOCK_SHIFT; 7231de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 7241de9a54aSTrevor Wu reg = ETDM_IN2_CON2; 7251de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 7261de9a54aSTrevor Wu shift = ETDM_IN_CON2_CLOCK_SHIFT; 7271de9a54aSTrevor Wu } 7281de9a54aSTrevor Wu 7291de9a54aSTrevor Wu if (reg) 7301de9a54aSTrevor Wu regmap_read(afe->regmap, reg, &value); 7311de9a54aSTrevor Wu 7321de9a54aSTrevor Wu value &= mask; 7331de9a54aSTrevor Wu value >>= shift; 7341de9a54aSTrevor Wu ucontrol->value.enumerated.item[0] = value; 7351de9a54aSTrevor Wu return 0; 7361de9a54aSTrevor Wu } 7371de9a54aSTrevor Wu 7381de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 7391de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", 7401de9a54aSTrevor Wu etdmout_clk_src_enum, 7411de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 7421de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 7431de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", 7441de9a54aSTrevor Wu etdmout_clk_src_enum, 7451de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 7461de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 7471de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", 7481de9a54aSTrevor Wu etdmout_clk_src_enum, 7491de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 7501de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 7511de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_IN1_Clock_Source", 7521de9a54aSTrevor Wu etdmout_clk_src_enum, 7531de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 7541de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 7551de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_IN2_Clock_Source", 7561de9a54aSTrevor Wu etdmout_clk_src_enum, 7571de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 7581de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 7591de9a54aSTrevor Wu }; 7601de9a54aSTrevor Wu 7611de9a54aSTrevor Wu static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 7621de9a54aSTrevor Wu /* eTDM_IN2 */ 7631de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 7641de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 7651de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 7661de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 7671de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 7681de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 7691de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 7701de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 7711de9a54aSTrevor Wu 7721de9a54aSTrevor Wu /* eTDM_IN1 */ 7731de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 7741de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 7751de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 7761de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 7771de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 7781de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 7791de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 7801de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 7811de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 7821de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 7831de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 7841de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 7851de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 7861de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 7871de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 7881de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 7891de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0), 7901de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0), 7911de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0), 7921de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0), 7931de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0), 7941de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0), 7951de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0), 7961de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0), 7971de9a54aSTrevor Wu 7981de9a54aSTrevor Wu /* eTDM_OUT2 */ 7991de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 8001de9a54aSTrevor Wu mtk_dai_etdm_o048_mix, 8011de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 8021de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 8031de9a54aSTrevor Wu mtk_dai_etdm_o049_mix, 8041de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 8051de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 8061de9a54aSTrevor Wu mtk_dai_etdm_o050_mix, 8071de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 8081de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 8091de9a54aSTrevor Wu mtk_dai_etdm_o051_mix, 8101de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 8111de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 8121de9a54aSTrevor Wu mtk_dai_etdm_o052_mix, 8131de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 8141de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 8151de9a54aSTrevor Wu mtk_dai_etdm_o053_mix, 8161de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 8171de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 8181de9a54aSTrevor Wu mtk_dai_etdm_o054_mix, 8191de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 8201de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 8211de9a54aSTrevor Wu mtk_dai_etdm_o055_mix, 8221de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 8231de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 8241de9a54aSTrevor Wu mtk_dai_etdm_o056_mix, 8251de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 8261de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 8271de9a54aSTrevor Wu mtk_dai_etdm_o057_mix, 8281de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 8291de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 8301de9a54aSTrevor Wu mtk_dai_etdm_o058_mix, 8311de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 8321de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 8331de9a54aSTrevor Wu mtk_dai_etdm_o059_mix, 8341de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 8351de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 8361de9a54aSTrevor Wu mtk_dai_etdm_o060_mix, 8371de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 8381de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 8391de9a54aSTrevor Wu mtk_dai_etdm_o061_mix, 8401de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 8411de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 8421de9a54aSTrevor Wu mtk_dai_etdm_o062_mix, 8431de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 8441de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 8451de9a54aSTrevor Wu mtk_dai_etdm_o063_mix, 8461de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 8471de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0, 8481de9a54aSTrevor Wu mtk_dai_etdm_o064_mix, 8491de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o064_mix)), 8501de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0, 8511de9a54aSTrevor Wu mtk_dai_etdm_o065_mix, 8521de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o065_mix)), 8531de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0, 8541de9a54aSTrevor Wu mtk_dai_etdm_o066_mix, 8551de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o066_mix)), 8561de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0, 8571de9a54aSTrevor Wu mtk_dai_etdm_o067_mix, 8581de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o067_mix)), 8591de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0, 8601de9a54aSTrevor Wu mtk_dai_etdm_o068_mix, 8611de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o068_mix)), 8621de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0, 8631de9a54aSTrevor Wu mtk_dai_etdm_o069_mix, 8641de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o069_mix)), 8651de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0, 8661de9a54aSTrevor Wu mtk_dai_etdm_o070_mix, 8671de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o070_mix)), 8681de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0, 8691de9a54aSTrevor Wu mtk_dai_etdm_o071_mix, 8701de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o071_mix)), 8711de9a54aSTrevor Wu 8721de9a54aSTrevor Wu /* eTDM_OUT1 */ 8731de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 8741de9a54aSTrevor Wu mtk_dai_etdm_o072_mix, 8751de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 8761de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 8771de9a54aSTrevor Wu mtk_dai_etdm_o073_mix, 8781de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 8791de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 8801de9a54aSTrevor Wu mtk_dai_etdm_o074_mix, 8811de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 8821de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 8831de9a54aSTrevor Wu mtk_dai_etdm_o075_mix, 8841de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 8851de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 8861de9a54aSTrevor Wu mtk_dai_etdm_o076_mix, 8871de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 8881de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 8891de9a54aSTrevor Wu mtk_dai_etdm_o077_mix, 8901de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 8911de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 8921de9a54aSTrevor Wu mtk_dai_etdm_o078_mix, 8931de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 8941de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 8951de9a54aSTrevor Wu mtk_dai_etdm_o079_mix, 8961de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 8971de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 8981de9a54aSTrevor Wu mtk_dai_etdm_o080_mix, 8991de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 9001de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 9011de9a54aSTrevor Wu mtk_dai_etdm_o081_mix, 9021de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 9031de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 9041de9a54aSTrevor Wu mtk_dai_etdm_o082_mix, 9051de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 9061de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 9071de9a54aSTrevor Wu mtk_dai_etdm_o083_mix, 9081de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 9091de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 9101de9a54aSTrevor Wu mtk_dai_etdm_o084_mix, 9111de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 9121de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 9131de9a54aSTrevor Wu mtk_dai_etdm_o085_mix, 9141de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 9151de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 9161de9a54aSTrevor Wu mtk_dai_etdm_o086_mix, 9171de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 9181de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 9191de9a54aSTrevor Wu mtk_dai_etdm_o087_mix, 9201de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 9211de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0, 9221de9a54aSTrevor Wu mtk_dai_etdm_o088_mix, 9231de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o088_mix)), 9241de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0, 9251de9a54aSTrevor Wu mtk_dai_etdm_o089_mix, 9261de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o089_mix)), 9271de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0, 9281de9a54aSTrevor Wu mtk_dai_etdm_o090_mix, 9291de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o090_mix)), 9301de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0, 9311de9a54aSTrevor Wu mtk_dai_etdm_o091_mix, 9321de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o091_mix)), 9331de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0, 9341de9a54aSTrevor Wu mtk_dai_etdm_o092_mix, 9351de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o092_mix)), 9361de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0, 9371de9a54aSTrevor Wu mtk_dai_etdm_o093_mix, 9381de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o093_mix)), 9391de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0, 9401de9a54aSTrevor Wu mtk_dai_etdm_o094_mix, 9411de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o094_mix)), 9421de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0, 9431de9a54aSTrevor Wu mtk_dai_etdm_o095_mix, 9441de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o095_mix)), 9451de9a54aSTrevor Wu 9461de9a54aSTrevor Wu /* eTDM_OUT3 */ 9471de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 9481de9a54aSTrevor Wu &hdmi_out_mux_control), 9491de9a54aSTrevor Wu SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 9501de9a54aSTrevor Wu &dptx_out_mux_control), 9511de9a54aSTrevor Wu 9521de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 9531de9a54aSTrevor Wu &hdmi_ch0_mux_control), 9541de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 9551de9a54aSTrevor Wu &hdmi_ch1_mux_control), 9561de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 9571de9a54aSTrevor Wu &hdmi_ch2_mux_control), 9581de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 9591de9a54aSTrevor Wu &hdmi_ch3_mux_control), 9601de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 9611de9a54aSTrevor Wu &hdmi_ch4_mux_control), 9621de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 9631de9a54aSTrevor Wu &hdmi_ch5_mux_control), 9641de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 9651de9a54aSTrevor Wu &hdmi_ch6_mux_control), 9661de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 9671de9a54aSTrevor Wu &hdmi_ch7_mux_control), 9681de9a54aSTrevor Wu 9691de9a54aSTrevor Wu SND_SOC_DAPM_INPUT("ETDM_INPUT"), 9701de9a54aSTrevor Wu SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 9711de9a54aSTrevor Wu }; 9721de9a54aSTrevor Wu 9731de9a54aSTrevor Wu static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 9741de9a54aSTrevor Wu {"I012", NULL, "ETDM2 Capture"}, 9751de9a54aSTrevor Wu {"I013", NULL, "ETDM2 Capture"}, 9761de9a54aSTrevor Wu {"I014", NULL, "ETDM2 Capture"}, 9771de9a54aSTrevor Wu {"I015", NULL, "ETDM2 Capture"}, 9781de9a54aSTrevor Wu {"I016", NULL, "ETDM2 Capture"}, 9791de9a54aSTrevor Wu {"I017", NULL, "ETDM2 Capture"}, 9801de9a54aSTrevor Wu {"I018", NULL, "ETDM2 Capture"}, 9811de9a54aSTrevor Wu {"I019", NULL, "ETDM2 Capture"}, 9821de9a54aSTrevor Wu 9831de9a54aSTrevor Wu {"I072", NULL, "ETDM1 Capture"}, 9841de9a54aSTrevor Wu {"I073", NULL, "ETDM1 Capture"}, 9851de9a54aSTrevor Wu {"I074", NULL, "ETDM1 Capture"}, 9861de9a54aSTrevor Wu {"I075", NULL, "ETDM1 Capture"}, 9871de9a54aSTrevor Wu {"I076", NULL, "ETDM1 Capture"}, 9881de9a54aSTrevor Wu {"I077", NULL, "ETDM1 Capture"}, 9891de9a54aSTrevor Wu {"I078", NULL, "ETDM1 Capture"}, 9901de9a54aSTrevor Wu {"I079", NULL, "ETDM1 Capture"}, 9911de9a54aSTrevor Wu {"I080", NULL, "ETDM1 Capture"}, 9921de9a54aSTrevor Wu {"I081", NULL, "ETDM1 Capture"}, 9931de9a54aSTrevor Wu {"I082", NULL, "ETDM1 Capture"}, 9941de9a54aSTrevor Wu {"I083", NULL, "ETDM1 Capture"}, 9951de9a54aSTrevor Wu {"I084", NULL, "ETDM1 Capture"}, 9961de9a54aSTrevor Wu {"I085", NULL, "ETDM1 Capture"}, 9971de9a54aSTrevor Wu {"I086", NULL, "ETDM1 Capture"}, 9981de9a54aSTrevor Wu {"I087", NULL, "ETDM1 Capture"}, 9991de9a54aSTrevor Wu {"I088", NULL, "ETDM1 Capture"}, 10001de9a54aSTrevor Wu {"I089", NULL, "ETDM1 Capture"}, 10011de9a54aSTrevor Wu {"I090", NULL, "ETDM1 Capture"}, 10021de9a54aSTrevor Wu {"I091", NULL, "ETDM1 Capture"}, 10031de9a54aSTrevor Wu {"I092", NULL, "ETDM1 Capture"}, 10041de9a54aSTrevor Wu {"I093", NULL, "ETDM1 Capture"}, 10051de9a54aSTrevor Wu {"I094", NULL, "ETDM1 Capture"}, 10061de9a54aSTrevor Wu {"I095", NULL, "ETDM1 Capture"}, 10071de9a54aSTrevor Wu 10081de9a54aSTrevor Wu {"UL8", NULL, "ETDM1 Capture"}, 10091de9a54aSTrevor Wu {"UL3", NULL, "ETDM2 Capture"}, 10101de9a54aSTrevor Wu 10111de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O048"}, 10121de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O049"}, 10131de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O050"}, 10141de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O051"}, 10151de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O052"}, 10161de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O053"}, 10171de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O054"}, 10181de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O055"}, 10191de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O056"}, 10201de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O057"}, 10211de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O058"}, 10221de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O059"}, 10231de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O060"}, 10241de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O061"}, 10251de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O062"}, 10261de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O063"}, 10271de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O064"}, 10281de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O065"}, 10291de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O066"}, 10301de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O067"}, 10311de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O068"}, 10321de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O069"}, 10331de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O070"}, 10341de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O071"}, 10351de9a54aSTrevor Wu 10361de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O072"}, 10371de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O073"}, 10381de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O074"}, 10391de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O075"}, 10401de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O076"}, 10411de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O077"}, 10421de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O078"}, 10431de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O079"}, 10441de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O080"}, 10451de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O081"}, 10461de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O082"}, 10471de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O083"}, 10481de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O084"}, 10491de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O085"}, 10501de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O086"}, 10511de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O087"}, 10521de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O088"}, 10531de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O089"}, 10541de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O090"}, 10551de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O091"}, 10561de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O092"}, 10571de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O093"}, 10581de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O094"}, 10591de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O095"}, 10601de9a54aSTrevor Wu 10611de9a54aSTrevor Wu {"O048", "I020 Switch", "I020"}, 10621de9a54aSTrevor Wu {"O049", "I021 Switch", "I021"}, 10631de9a54aSTrevor Wu 10641de9a54aSTrevor Wu {"O048", "I022 Switch", "I022"}, 10651de9a54aSTrevor Wu {"O049", "I023 Switch", "I023"}, 10661de9a54aSTrevor Wu {"O050", "I024 Switch", "I024"}, 10671de9a54aSTrevor Wu {"O051", "I025 Switch", "I025"}, 10681de9a54aSTrevor Wu {"O052", "I026 Switch", "I026"}, 10691de9a54aSTrevor Wu {"O053", "I027 Switch", "I027"}, 10701de9a54aSTrevor Wu {"O054", "I028 Switch", "I028"}, 10711de9a54aSTrevor Wu {"O055", "I029 Switch", "I029"}, 10721de9a54aSTrevor Wu {"O056", "I030 Switch", "I030"}, 10731de9a54aSTrevor Wu {"O057", "I031 Switch", "I031"}, 10741de9a54aSTrevor Wu {"O058", "I032 Switch", "I032"}, 10751de9a54aSTrevor Wu {"O059", "I033 Switch", "I033"}, 10761de9a54aSTrevor Wu {"O060", "I034 Switch", "I034"}, 10771de9a54aSTrevor Wu {"O061", "I035 Switch", "I035"}, 10781de9a54aSTrevor Wu {"O062", "I036 Switch", "I036"}, 10791de9a54aSTrevor Wu {"O063", "I037 Switch", "I037"}, 10801de9a54aSTrevor Wu {"O064", "I038 Switch", "I038"}, 10811de9a54aSTrevor Wu {"O065", "I039 Switch", "I039"}, 10821de9a54aSTrevor Wu {"O066", "I040 Switch", "I040"}, 10831de9a54aSTrevor Wu {"O067", "I041 Switch", "I041"}, 10841de9a54aSTrevor Wu {"O068", "I042 Switch", "I042"}, 10851de9a54aSTrevor Wu {"O069", "I043 Switch", "I043"}, 10861de9a54aSTrevor Wu {"O070", "I044 Switch", "I044"}, 10871de9a54aSTrevor Wu {"O071", "I045 Switch", "I045"}, 10881de9a54aSTrevor Wu 10891de9a54aSTrevor Wu {"O048", "I046 Switch", "I046"}, 10901de9a54aSTrevor Wu {"O049", "I047 Switch", "I047"}, 10911de9a54aSTrevor Wu {"O050", "I048 Switch", "I048"}, 10921de9a54aSTrevor Wu {"O051", "I049 Switch", "I049"}, 10931de9a54aSTrevor Wu {"O052", "I050 Switch", "I050"}, 10941de9a54aSTrevor Wu {"O053", "I051 Switch", "I051"}, 10951de9a54aSTrevor Wu {"O054", "I052 Switch", "I052"}, 10961de9a54aSTrevor Wu {"O055", "I053 Switch", "I053"}, 10971de9a54aSTrevor Wu {"O056", "I054 Switch", "I054"}, 10981de9a54aSTrevor Wu {"O057", "I055 Switch", "I055"}, 10991de9a54aSTrevor Wu {"O058", "I056 Switch", "I056"}, 11001de9a54aSTrevor Wu {"O059", "I057 Switch", "I057"}, 11011de9a54aSTrevor Wu {"O060", "I058 Switch", "I058"}, 11021de9a54aSTrevor Wu {"O061", "I059 Switch", "I059"}, 11031de9a54aSTrevor Wu {"O062", "I060 Switch", "I060"}, 11041de9a54aSTrevor Wu {"O063", "I061 Switch", "I061"}, 11051de9a54aSTrevor Wu {"O064", "I062 Switch", "I062"}, 11061de9a54aSTrevor Wu {"O065", "I063 Switch", "I063"}, 11071de9a54aSTrevor Wu {"O066", "I064 Switch", "I064"}, 11081de9a54aSTrevor Wu {"O067", "I065 Switch", "I065"}, 11091de9a54aSTrevor Wu {"O068", "I066 Switch", "I066"}, 11101de9a54aSTrevor Wu {"O069", "I067 Switch", "I067"}, 11111de9a54aSTrevor Wu {"O070", "I068 Switch", "I068"}, 11121de9a54aSTrevor Wu {"O071", "I069 Switch", "I069"}, 11131de9a54aSTrevor Wu 11141de9a54aSTrevor Wu {"O048", "I070 Switch", "I070"}, 11151de9a54aSTrevor Wu {"O049", "I071 Switch", "I071"}, 11161de9a54aSTrevor Wu 11171de9a54aSTrevor Wu {"O072", "I020 Switch", "I020"}, 11181de9a54aSTrevor Wu {"O073", "I021 Switch", "I021"}, 11191de9a54aSTrevor Wu 11201de9a54aSTrevor Wu {"O072", "I022 Switch", "I022"}, 11211de9a54aSTrevor Wu {"O073", "I023 Switch", "I023"}, 11221de9a54aSTrevor Wu {"O074", "I024 Switch", "I024"}, 11231de9a54aSTrevor Wu {"O075", "I025 Switch", "I025"}, 11241de9a54aSTrevor Wu {"O076", "I026 Switch", "I026"}, 11251de9a54aSTrevor Wu {"O077", "I027 Switch", "I027"}, 11261de9a54aSTrevor Wu {"O078", "I028 Switch", "I028"}, 11271de9a54aSTrevor Wu {"O079", "I029 Switch", "I029"}, 11281de9a54aSTrevor Wu {"O080", "I030 Switch", "I030"}, 11291de9a54aSTrevor Wu {"O081", "I031 Switch", "I031"}, 11301de9a54aSTrevor Wu {"O082", "I032 Switch", "I032"}, 11311de9a54aSTrevor Wu {"O083", "I033 Switch", "I033"}, 11321de9a54aSTrevor Wu {"O084", "I034 Switch", "I034"}, 11331de9a54aSTrevor Wu {"O085", "I035 Switch", "I035"}, 11341de9a54aSTrevor Wu {"O086", "I036 Switch", "I036"}, 11351de9a54aSTrevor Wu {"O087", "I037 Switch", "I037"}, 11361de9a54aSTrevor Wu {"O088", "I038 Switch", "I038"}, 11371de9a54aSTrevor Wu {"O089", "I039 Switch", "I039"}, 11381de9a54aSTrevor Wu {"O090", "I040 Switch", "I040"}, 11391de9a54aSTrevor Wu {"O091", "I041 Switch", "I041"}, 11401de9a54aSTrevor Wu {"O092", "I042 Switch", "I042"}, 11411de9a54aSTrevor Wu {"O093", "I043 Switch", "I043"}, 11421de9a54aSTrevor Wu {"O094", "I044 Switch", "I044"}, 11431de9a54aSTrevor Wu {"O095", "I045 Switch", "I045"}, 11441de9a54aSTrevor Wu 11451de9a54aSTrevor Wu {"O072", "I046 Switch", "I046"}, 11461de9a54aSTrevor Wu {"O073", "I047 Switch", "I047"}, 11471de9a54aSTrevor Wu {"O074", "I048 Switch", "I048"}, 11481de9a54aSTrevor Wu {"O075", "I049 Switch", "I049"}, 11491de9a54aSTrevor Wu {"O076", "I050 Switch", "I050"}, 11501de9a54aSTrevor Wu {"O077", "I051 Switch", "I051"}, 11511de9a54aSTrevor Wu {"O078", "I052 Switch", "I052"}, 11521de9a54aSTrevor Wu {"O079", "I053 Switch", "I053"}, 11531de9a54aSTrevor Wu {"O080", "I054 Switch", "I054"}, 11541de9a54aSTrevor Wu {"O081", "I055 Switch", "I055"}, 11551de9a54aSTrevor Wu {"O082", "I056 Switch", "I056"}, 11561de9a54aSTrevor Wu {"O083", "I057 Switch", "I057"}, 11571de9a54aSTrevor Wu {"O084", "I058 Switch", "I058"}, 11581de9a54aSTrevor Wu {"O085", "I059 Switch", "I059"}, 11591de9a54aSTrevor Wu {"O086", "I060 Switch", "I060"}, 11601de9a54aSTrevor Wu {"O087", "I061 Switch", "I061"}, 11611de9a54aSTrevor Wu {"O088", "I062 Switch", "I062"}, 11621de9a54aSTrevor Wu {"O089", "I063 Switch", "I063"}, 11631de9a54aSTrevor Wu {"O090", "I064 Switch", "I064"}, 11641de9a54aSTrevor Wu {"O091", "I065 Switch", "I065"}, 11651de9a54aSTrevor Wu {"O092", "I066 Switch", "I066"}, 11661de9a54aSTrevor Wu {"O093", "I067 Switch", "I067"}, 11671de9a54aSTrevor Wu {"O094", "I068 Switch", "I068"}, 11681de9a54aSTrevor Wu {"O095", "I069 Switch", "I069"}, 11691de9a54aSTrevor Wu 11701de9a54aSTrevor Wu {"O072", "I070 Switch", "I070"}, 11711de9a54aSTrevor Wu {"O073", "I071 Switch", "I071"}, 11721de9a54aSTrevor Wu 11731de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH0", "DL10"}, 11741de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH1", "DL10"}, 11751de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH2", "DL10"}, 11761de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH3", "DL10"}, 11771de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH4", "DL10"}, 11781de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH5", "DL10"}, 11791de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH6", "DL10"}, 11801de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH7", "DL10"}, 11811de9a54aSTrevor Wu 11821de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH0", "DL10"}, 11831de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH1", "DL10"}, 11841de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH2", "DL10"}, 11851de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH3", "DL10"}, 11861de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH4", "DL10"}, 11871de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH5", "DL10"}, 11881de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH6", "DL10"}, 11891de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH7", "DL10"}, 11901de9a54aSTrevor Wu 11911de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH0", "DL10"}, 11921de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH1", "DL10"}, 11931de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH2", "DL10"}, 11941de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH3", "DL10"}, 11951de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH4", "DL10"}, 11961de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH5", "DL10"}, 11971de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH6", "DL10"}, 11981de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH7", "DL10"}, 11991de9a54aSTrevor Wu 12001de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH0", "DL10"}, 12011de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH1", "DL10"}, 12021de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH2", "DL10"}, 12031de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH3", "DL10"}, 12041de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH4", "DL10"}, 12051de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH5", "DL10"}, 12061de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH6", "DL10"}, 12071de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH7", "DL10"}, 12081de9a54aSTrevor Wu 12091de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH0", "DL10"}, 12101de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH1", "DL10"}, 12111de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH2", "DL10"}, 12121de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH3", "DL10"}, 12131de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH4", "DL10"}, 12141de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH5", "DL10"}, 12151de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH6", "DL10"}, 12161de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH7", "DL10"}, 12171de9a54aSTrevor Wu 12181de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH0", "DL10"}, 12191de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH1", "DL10"}, 12201de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH2", "DL10"}, 12211de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH3", "DL10"}, 12221de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH4", "DL10"}, 12231de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH5", "DL10"}, 12241de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH6", "DL10"}, 12251de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH7", "DL10"}, 12261de9a54aSTrevor Wu 12271de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH0", "DL10"}, 12281de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH1", "DL10"}, 12291de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH2", "DL10"}, 12301de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH3", "DL10"}, 12311de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH4", "DL10"}, 12321de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH5", "DL10"}, 12331de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH6", "DL10"}, 12341de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH7", "DL10"}, 12351de9a54aSTrevor Wu 12361de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH0", "DL10"}, 12371de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH1", "DL10"}, 12381de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH2", "DL10"}, 12391de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH3", "DL10"}, 12401de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH4", "DL10"}, 12411de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH5", "DL10"}, 12421de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH6", "DL10"}, 12431de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH7", "DL10"}, 12441de9a54aSTrevor Wu 12451de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 12461de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 12471de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 12481de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 12491de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 12501de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 12511de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 12521de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 12531de9a54aSTrevor Wu 12541de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 12551de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 12561de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 12571de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 12581de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 12591de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 12601de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 12611de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 12621de9a54aSTrevor Wu 12631de9a54aSTrevor Wu {"ETDM3 Playback", NULL, "HDMI_OUT_MUX"}, 12641de9a54aSTrevor Wu {"DPTX Playback", NULL, "DPTX_OUT_MUX"}, 12651de9a54aSTrevor Wu 12661de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "DPTX Playback"}, 12671de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM1 Playback"}, 12681de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM2 Playback"}, 12691de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM3 Playback"}, 12701de9a54aSTrevor Wu {"ETDM1 Capture", NULL, "ETDM_INPUT"}, 12711de9a54aSTrevor Wu {"ETDM2 Capture", NULL, "ETDM_INPUT"}, 12721de9a54aSTrevor Wu }; 12731de9a54aSTrevor Wu 12741de9a54aSTrevor Wu static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 12751de9a54aSTrevor Wu { 12761de9a54aSTrevor Wu int ret = 0; 12771de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 12781de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 12791de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 12801de9a54aSTrevor Wu unsigned long flags; 12811de9a54aSTrevor Wu 12821de9a54aSTrevor Wu spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 12831de9a54aSTrevor Wu etdm_data->en_ref_cnt++; 12841de9a54aSTrevor Wu if (etdm_data->en_ref_cnt == 1) { 12851de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 12861de9a54aSTrevor Wu if (ret < 0) 12871de9a54aSTrevor Wu goto out; 12881de9a54aSTrevor Wu 12891de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, 12901de9a54aSTrevor Wu ETDM_CON0_EN, ETDM_CON0_EN); 12911de9a54aSTrevor Wu } 12921de9a54aSTrevor Wu out: 12931de9a54aSTrevor Wu spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 12941de9a54aSTrevor Wu return ret; 12951de9a54aSTrevor Wu } 12961de9a54aSTrevor Wu 12971de9a54aSTrevor Wu static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 12981de9a54aSTrevor Wu { 12991de9a54aSTrevor Wu int ret = 0; 13001de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 13011de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 13021de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 13031de9a54aSTrevor Wu unsigned long flags; 13041de9a54aSTrevor Wu 13051de9a54aSTrevor Wu spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 13061de9a54aSTrevor Wu if (etdm_data->en_ref_cnt > 0) { 13071de9a54aSTrevor Wu etdm_data->en_ref_cnt--; 13081de9a54aSTrevor Wu if (etdm_data->en_ref_cnt == 0) { 13091de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 13101de9a54aSTrevor Wu if (ret < 0) 13111de9a54aSTrevor Wu goto out; 13121de9a54aSTrevor Wu 13131de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, 13141de9a54aSTrevor Wu ETDM_CON0_EN, 0); 13151de9a54aSTrevor Wu } 13161de9a54aSTrevor Wu } 13171de9a54aSTrevor Wu out: 13181de9a54aSTrevor Wu spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 13191de9a54aSTrevor Wu return 0; 13201de9a54aSTrevor Wu } 13211de9a54aSTrevor Wu 13221de9a54aSTrevor Wu static int etdm_cowork_slv_sel(int id, int slave_mode) 13231de9a54aSTrevor Wu { 13241de9a54aSTrevor Wu if (slave_mode) { 13251de9a54aSTrevor Wu switch (id) { 13261de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 13271de9a54aSTrevor Wu return COWORK_ETDM_IN1_S; 13281de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 13291de9a54aSTrevor Wu return COWORK_ETDM_IN2_S; 13301de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 13311de9a54aSTrevor Wu return COWORK_ETDM_OUT1_S; 13321de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 13331de9a54aSTrevor Wu return COWORK_ETDM_OUT2_S; 13341de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 13351de9a54aSTrevor Wu return COWORK_ETDM_OUT3_S; 13361de9a54aSTrevor Wu default: 13371de9a54aSTrevor Wu return -EINVAL; 13381de9a54aSTrevor Wu } 13391de9a54aSTrevor Wu } else { 13401de9a54aSTrevor Wu switch (id) { 13411de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 13421de9a54aSTrevor Wu return COWORK_ETDM_IN1_M; 13431de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 13441de9a54aSTrevor Wu return COWORK_ETDM_IN2_M; 13451de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 13461de9a54aSTrevor Wu return COWORK_ETDM_OUT1_M; 13471de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 13481de9a54aSTrevor Wu return COWORK_ETDM_OUT2_M; 13491de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 13501de9a54aSTrevor Wu return COWORK_ETDM_OUT3_M; 13511de9a54aSTrevor Wu default: 13521de9a54aSTrevor Wu return -EINVAL; 13531de9a54aSTrevor Wu } 13541de9a54aSTrevor Wu } 13551de9a54aSTrevor Wu } 13561de9a54aSTrevor Wu 13571de9a54aSTrevor Wu static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 13581de9a54aSTrevor Wu { 13591de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 13601de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 13611de9a54aSTrevor Wu unsigned int reg = 0; 13621de9a54aSTrevor Wu unsigned int mask; 13631de9a54aSTrevor Wu unsigned int val; 13641de9a54aSTrevor Wu int cowork_source_sel; 13651de9a54aSTrevor Wu 13661de9a54aSTrevor Wu if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 13671de9a54aSTrevor Wu return 0; 13681de9a54aSTrevor Wu 13691de9a54aSTrevor Wu cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 13701de9a54aSTrevor Wu etdm_data->slave_mode); 13711de9a54aSTrevor Wu if (cowork_source_sel < 0) 13721de9a54aSTrevor Wu return cowork_source_sel; 13731de9a54aSTrevor Wu 13741de9a54aSTrevor Wu switch (dai_id) { 13751de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 13761de9a54aSTrevor Wu reg = ETDM_COWORK_CON1; 13771de9a54aSTrevor Wu mask = ETDM_IN1_SLAVE_SEL_MASK; 13781de9a54aSTrevor Wu val = ETDM_IN1_SLAVE_SEL(cowork_source_sel); 13791de9a54aSTrevor Wu break; 13801de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 13811de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 13821de9a54aSTrevor Wu mask = ETDM_IN2_SLAVE_SEL_MASK; 13831de9a54aSTrevor Wu val = ETDM_IN2_SLAVE_SEL(cowork_source_sel); 13841de9a54aSTrevor Wu break; 13851de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 13861de9a54aSTrevor Wu reg = ETDM_COWORK_CON0; 13871de9a54aSTrevor Wu mask = ETDM_OUT1_SLAVE_SEL_MASK; 13881de9a54aSTrevor Wu val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel); 13891de9a54aSTrevor Wu break; 13901de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 13911de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 13921de9a54aSTrevor Wu mask = ETDM_OUT2_SLAVE_SEL_MASK; 13931de9a54aSTrevor Wu val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel); 13941de9a54aSTrevor Wu break; 13951de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 13961de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 13971de9a54aSTrevor Wu mask = ETDM_OUT3_SLAVE_SEL_MASK; 13981de9a54aSTrevor Wu val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel); 13991de9a54aSTrevor Wu break; 14001de9a54aSTrevor Wu default: 14011de9a54aSTrevor Wu return 0; 14021de9a54aSTrevor Wu } 14031de9a54aSTrevor Wu 14041de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 14051de9a54aSTrevor Wu 14061de9a54aSTrevor Wu return 0; 14071de9a54aSTrevor Wu } 14081de9a54aSTrevor Wu 14091de9a54aSTrevor Wu static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 14101de9a54aSTrevor Wu { 14111de9a54aSTrevor Wu int cg_id = -1; 14121de9a54aSTrevor Wu 14131de9a54aSTrevor Wu switch (dai_id) { 14141de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 14151de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_HDMI_OUT; 14161de9a54aSTrevor Wu break; 14171de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 14181de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_TDM_IN; 14191de9a54aSTrevor Wu break; 14201de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 14211de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_I2SIN; 14221de9a54aSTrevor Wu break; 14231de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 14241de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_TDM_OUT; 14251de9a54aSTrevor Wu break; 14261de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 14271de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_I2S_OUT; 14281de9a54aSTrevor Wu break; 14291de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 14301de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_HDMI_OUT; 14311de9a54aSTrevor Wu break; 14321de9a54aSTrevor Wu default: 14331de9a54aSTrevor Wu break; 14341de9a54aSTrevor Wu } 14351de9a54aSTrevor Wu 14361de9a54aSTrevor Wu return cg_id; 14371de9a54aSTrevor Wu } 14381de9a54aSTrevor Wu 14391de9a54aSTrevor Wu static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 14401de9a54aSTrevor Wu { 14411de9a54aSTrevor Wu int clk_id = -1; 14421de9a54aSTrevor Wu 14431de9a54aSTrevor Wu switch (dai_id) { 14441de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 14451de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_DPTX_M_SEL; 14461de9a54aSTrevor Wu break; 14471de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 14481de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SI1_M_SEL; 14491de9a54aSTrevor Wu break; 14501de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 14511de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SI2_M_SEL; 14521de9a54aSTrevor Wu break; 14531de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 14541de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SO1_M_SEL; 14551de9a54aSTrevor Wu break; 14561de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 14571de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SO2_M_SEL; 14581de9a54aSTrevor Wu break; 14591de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 14601de9a54aSTrevor Wu default: 14611de9a54aSTrevor Wu break; 14621de9a54aSTrevor Wu } 14631de9a54aSTrevor Wu 14641de9a54aSTrevor Wu return clk_id; 14651de9a54aSTrevor Wu } 14661de9a54aSTrevor Wu 14671de9a54aSTrevor Wu static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 14681de9a54aSTrevor Wu { 14691de9a54aSTrevor Wu int clk_id = -1; 14701de9a54aSTrevor Wu 14711de9a54aSTrevor Wu switch (dai_id) { 14721de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 14731de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV9; 14741de9a54aSTrevor Wu break; 14751de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 14761de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV0; 14771de9a54aSTrevor Wu break; 14781de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 14791de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV1; 14801de9a54aSTrevor Wu break; 14811de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 14821de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV2; 14831de9a54aSTrevor Wu break; 14841de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 14851de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV3; 14861de9a54aSTrevor Wu break; 14871de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 14881de9a54aSTrevor Wu default: 14891de9a54aSTrevor Wu break; 14901de9a54aSTrevor Wu } 14911de9a54aSTrevor Wu 14921de9a54aSTrevor Wu return clk_id; 14931de9a54aSTrevor Wu } 14941de9a54aSTrevor Wu 14951de9a54aSTrevor Wu static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 14961de9a54aSTrevor Wu { 14971de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 14981de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 14991de9a54aSTrevor Wu 15001de9a54aSTrevor Wu if (clkdiv_id < 0) 15011de9a54aSTrevor Wu return -EINVAL; 15021de9a54aSTrevor Wu 15031de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 15041de9a54aSTrevor Wu 15051de9a54aSTrevor Wu return 0; 15061de9a54aSTrevor Wu } 15071de9a54aSTrevor Wu 15081de9a54aSTrevor Wu static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 15091de9a54aSTrevor Wu { 15101de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 15111de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 15121de9a54aSTrevor Wu 15131de9a54aSTrevor Wu if (clkdiv_id < 0) 15141de9a54aSTrevor Wu return -EINVAL; 15151de9a54aSTrevor Wu 15161de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 15171de9a54aSTrevor Wu 15181de9a54aSTrevor Wu return 0; 15191de9a54aSTrevor Wu } 15201de9a54aSTrevor Wu 15211de9a54aSTrevor Wu /* dai ops */ 15221de9a54aSTrevor Wu static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 15231de9a54aSTrevor Wu struct snd_soc_dai *dai) 15241de9a54aSTrevor Wu { 15251de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 15261de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 15271de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 15281de9a54aSTrevor Wu int cg_id; 15291de9a54aSTrevor Wu int mst_dai_id; 15301de9a54aSTrevor Wu int slv_dai_id; 15311de9a54aSTrevor Wu int i; 15321de9a54aSTrevor Wu 15331de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 15341de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 15351de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 15361de9a54aSTrevor Wu 15371de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 15381de9a54aSTrevor Wu if (cg_id >= 0) 15391de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 15401de9a54aSTrevor Wu 15411de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 15421de9a54aSTrevor Wu 15431de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 15441de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 15451de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 15461de9a54aSTrevor Wu if (cg_id >= 0) 15471de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, 15481de9a54aSTrevor Wu afe_priv->clk[cg_id]); 15491de9a54aSTrevor Wu } 15501de9a54aSTrevor Wu } else { 15511de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 15521de9a54aSTrevor Wu 15531de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 15541de9a54aSTrevor Wu if (cg_id >= 0) 15551de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 15561de9a54aSTrevor Wu } 15571de9a54aSTrevor Wu 15581de9a54aSTrevor Wu return 0; 15591de9a54aSTrevor Wu } 15601de9a54aSTrevor Wu 15611de9a54aSTrevor Wu static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 15621de9a54aSTrevor Wu struct snd_soc_dai *dai) 15631de9a54aSTrevor Wu { 15641de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 15651de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 15661de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 15671de9a54aSTrevor Wu int cg_id; 15681de9a54aSTrevor Wu int mst_dai_id; 15691de9a54aSTrevor Wu int slv_dai_id; 15701de9a54aSTrevor Wu int i; 15711de9a54aSTrevor Wu 15721de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 15731de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 15741de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 15751de9a54aSTrevor Wu if (cg_id >= 0) 15761de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 15771de9a54aSTrevor Wu 15781de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 15791de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 15801de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 15811de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 15821de9a54aSTrevor Wu if (cg_id >= 0) 15831de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, 15841de9a54aSTrevor Wu afe_priv->clk[cg_id]); 15851de9a54aSTrevor Wu } 15861de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 15871de9a54aSTrevor Wu } else { 15881de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 15891de9a54aSTrevor Wu if (cg_id >= 0) 15901de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 15911de9a54aSTrevor Wu 15921de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, dai->id); 15931de9a54aSTrevor Wu } 15941de9a54aSTrevor Wu } 15951de9a54aSTrevor Wu 15961de9a54aSTrevor Wu static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 15971de9a54aSTrevor Wu int dai_id, unsigned int rate) 15981de9a54aSTrevor Wu { 15991de9a54aSTrevor Wu unsigned int mode = 0; 16001de9a54aSTrevor Wu unsigned int reg = 0; 16011de9a54aSTrevor Wu unsigned int val = 0; 16021de9a54aSTrevor Wu unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 16031de9a54aSTrevor Wu 16041de9a54aSTrevor Wu if (rate != 0) 16051de9a54aSTrevor Wu mode = mt8195_afe_fs_timing(rate); 16061de9a54aSTrevor Wu 16071de9a54aSTrevor Wu switch (dai_id) { 16081de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 16091de9a54aSTrevor Wu reg = ETDM_IN1_AFIFO_CON; 16101de9a54aSTrevor Wu if (rate == 0) 16111de9a54aSTrevor Wu mode = MT8195_ETDM_IN1_1X_EN; 16121de9a54aSTrevor Wu break; 16131de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 16141de9a54aSTrevor Wu reg = ETDM_IN2_AFIFO_CON; 16151de9a54aSTrevor Wu if (rate == 0) 16161de9a54aSTrevor Wu mode = MT8195_ETDM_IN2_1X_EN; 16171de9a54aSTrevor Wu break; 16181de9a54aSTrevor Wu default: 16191de9a54aSTrevor Wu return -EINVAL; 16201de9a54aSTrevor Wu } 16211de9a54aSTrevor Wu 16221de9a54aSTrevor Wu val = (mode | ETDM_IN_USE_AFIFO); 16231de9a54aSTrevor Wu 16241de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 16251de9a54aSTrevor Wu return 0; 16261de9a54aSTrevor Wu } 16271de9a54aSTrevor Wu 16281de9a54aSTrevor Wu static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 16291de9a54aSTrevor Wu unsigned int rate, 16301de9a54aSTrevor Wu unsigned int channels, 16311de9a54aSTrevor Wu int dai_id) 16321de9a54aSTrevor Wu { 16331de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 16341de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 16351de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 16361de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 16371de9a54aSTrevor Wu unsigned int data_mode = etdm_data->data_mode; 16381de9a54aSTrevor Wu unsigned int lrck_width = etdm_data->lrck_width; 16391de9a54aSTrevor Wu unsigned int val = 0; 16401de9a54aSTrevor Wu unsigned int mask = 0; 16411de9a54aSTrevor Wu int i; 16421de9a54aSTrevor Wu int ret; 16431de9a54aSTrevor Wu 16441de9a54aSTrevor Wu dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 16451de9a54aSTrevor Wu __func__, rate, channels, dai_id); 16461de9a54aSTrevor Wu 16471de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 16481de9a54aSTrevor Wu if (ret < 0) 16491de9a54aSTrevor Wu return ret; 16501de9a54aSTrevor Wu 16511de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 16521de9a54aSTrevor Wu slave_mode = true; 16531de9a54aSTrevor Wu 16541de9a54aSTrevor Wu /* afifo */ 16551de9a54aSTrevor Wu if (slave_mode) 16561de9a54aSTrevor Wu mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 16571de9a54aSTrevor Wu else 16581de9a54aSTrevor Wu mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 16591de9a54aSTrevor Wu 16601de9a54aSTrevor Wu /* con1 */ 16611de9a54aSTrevor Wu if (lrck_width > 0) { 16621de9a54aSTrevor Wu mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 16631de9a54aSTrevor Wu ETDM_IN_CON1_LRCK_WIDTH_MASK); 16641de9a54aSTrevor Wu val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width); 16651de9a54aSTrevor Wu } 16661de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 16671de9a54aSTrevor Wu 16681de9a54aSTrevor Wu mask = 0; 16691de9a54aSTrevor Wu val = 0; 16701de9a54aSTrevor Wu 16711de9a54aSTrevor Wu /* con2 */ 16721de9a54aSTrevor Wu if (!slave_mode) { 16731de9a54aSTrevor Wu mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 16741de9a54aSTrevor Wu if (rate == 352800 || rate == 384000) 16751de9a54aSTrevor Wu val |= ETDM_IN_CON2_UPDATE_GAP(4); 16761de9a54aSTrevor Wu else 16771de9a54aSTrevor Wu val |= ETDM_IN_CON2_UPDATE_GAP(3); 16781de9a54aSTrevor Wu } 16791de9a54aSTrevor Wu mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 16801de9a54aSTrevor Wu ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 16811de9a54aSTrevor Wu if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 16821de9a54aSTrevor Wu val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 16831de9a54aSTrevor Wu ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels); 16841de9a54aSTrevor Wu } 16851de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 16861de9a54aSTrevor Wu 16871de9a54aSTrevor Wu mask = 0; 16881de9a54aSTrevor Wu val = 0; 16891de9a54aSTrevor Wu 16901de9a54aSTrevor Wu /* con3 */ 16911de9a54aSTrevor Wu mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 16921de9a54aSTrevor Wu for (i = 0; i < channels; i += 2) { 16931de9a54aSTrevor Wu if (etdm_data->in_disable_ch[i] && 16941de9a54aSTrevor Wu etdm_data->in_disable_ch[i + 1]) 16951de9a54aSTrevor Wu val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 16961de9a54aSTrevor Wu } 16971de9a54aSTrevor Wu if (!slave_mode) { 16981de9a54aSTrevor Wu mask |= ETDM_IN_CON3_FS_MASK; 16991de9a54aSTrevor Wu val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate)); 17001de9a54aSTrevor Wu } 17011de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 17021de9a54aSTrevor Wu 17031de9a54aSTrevor Wu mask = 0; 17041de9a54aSTrevor Wu val = 0; 17051de9a54aSTrevor Wu 17061de9a54aSTrevor Wu /* con4 */ 17071de9a54aSTrevor Wu mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 17081de9a54aSTrevor Wu ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 17091de9a54aSTrevor Wu if (slave_mode) { 17101de9a54aSTrevor Wu if (etdm_data->lrck_inv) 17111de9a54aSTrevor Wu val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 17121de9a54aSTrevor Wu if (etdm_data->bck_inv) 17131de9a54aSTrevor Wu val |= ETDM_IN_CON4_SLAVE_BCK_INV; 17141de9a54aSTrevor Wu } else { 17151de9a54aSTrevor Wu if (etdm_data->lrck_inv) 17161de9a54aSTrevor Wu val |= ETDM_IN_CON4_MASTER_LRCK_INV; 17171de9a54aSTrevor Wu if (etdm_data->bck_inv) 17181de9a54aSTrevor Wu val |= ETDM_IN_CON4_MASTER_BCK_INV; 17191de9a54aSTrevor Wu } 17201de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 17211de9a54aSTrevor Wu 17221de9a54aSTrevor Wu mask = 0; 17231de9a54aSTrevor Wu val = 0; 17241de9a54aSTrevor Wu 17251de9a54aSTrevor Wu /* con5 */ 17261de9a54aSTrevor Wu mask |= ETDM_IN_CON5_LR_SWAP_MASK; 17271de9a54aSTrevor Wu mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 17281de9a54aSTrevor Wu for (i = 0; i < channels; i += 2) { 17291de9a54aSTrevor Wu if (etdm_data->in_disable_ch[i] && 17301de9a54aSTrevor Wu !etdm_data->in_disable_ch[i + 1]) { 17311de9a54aSTrevor Wu if (i == (channels - 2)) 17321de9a54aSTrevor Wu val |= ETDM_IN_CON5_LR_SWAP(15); 17331de9a54aSTrevor Wu else 17341de9a54aSTrevor Wu val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 17351de9a54aSTrevor Wu val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 17361de9a54aSTrevor Wu } else if (!etdm_data->in_disable_ch[i] && 17371de9a54aSTrevor Wu etdm_data->in_disable_ch[i + 1]) { 17381de9a54aSTrevor Wu val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 17391de9a54aSTrevor Wu } 17401de9a54aSTrevor Wu } 17411de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 17421de9a54aSTrevor Wu return 0; 17431de9a54aSTrevor Wu } 17441de9a54aSTrevor Wu 17451de9a54aSTrevor Wu static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 17461de9a54aSTrevor Wu unsigned int rate, 17471de9a54aSTrevor Wu unsigned int channels, 17481de9a54aSTrevor Wu int dai_id) 17491de9a54aSTrevor Wu { 17501de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 17511de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 17521de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 17531de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 17541de9a54aSTrevor Wu unsigned int lrck_width = etdm_data->lrck_width; 17551de9a54aSTrevor Wu unsigned int val = 0; 17561de9a54aSTrevor Wu unsigned int mask = 0; 17571de9a54aSTrevor Wu int ret; 17581de9a54aSTrevor Wu int fs = 0; 17591de9a54aSTrevor Wu 17601de9a54aSTrevor Wu dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 17611de9a54aSTrevor Wu __func__, rate, channels, dai_id); 17621de9a54aSTrevor Wu 17631de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 17641de9a54aSTrevor Wu if (ret < 0) 17651de9a54aSTrevor Wu return ret; 17661de9a54aSTrevor Wu 17671de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 17681de9a54aSTrevor Wu slave_mode = true; 17691de9a54aSTrevor Wu 17701de9a54aSTrevor Wu /* con0 */ 17711de9a54aSTrevor Wu mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 17721de9a54aSTrevor Wu val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS); 17731de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 17741de9a54aSTrevor Wu 17751de9a54aSTrevor Wu mask = 0; 17761de9a54aSTrevor Wu val = 0; 17771de9a54aSTrevor Wu 17781de9a54aSTrevor Wu /* con1 */ 17791de9a54aSTrevor Wu if (lrck_width > 0) { 17801de9a54aSTrevor Wu mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 17811de9a54aSTrevor Wu ETDM_OUT_CON1_LRCK_WIDTH_MASK); 17821de9a54aSTrevor Wu val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width); 17831de9a54aSTrevor Wu } 17841de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 17851de9a54aSTrevor Wu 17861de9a54aSTrevor Wu mask = 0; 17871de9a54aSTrevor Wu val = 0; 17881de9a54aSTrevor Wu 17891de9a54aSTrevor Wu if (slave_mode) { 17901de9a54aSTrevor Wu /* con2 */ 17911de9a54aSTrevor Wu mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 17921de9a54aSTrevor Wu ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 17931de9a54aSTrevor Wu val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 17941de9a54aSTrevor Wu ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 17951de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con2, 17961de9a54aSTrevor Wu mask, val); 17971de9a54aSTrevor Wu mask = 0; 17981de9a54aSTrevor Wu val = 0; 17991de9a54aSTrevor Wu } else { 18001de9a54aSTrevor Wu /* con4 */ 18011de9a54aSTrevor Wu mask |= ETDM_OUT_CON4_FS_MASK; 18021de9a54aSTrevor Wu val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate)); 18031de9a54aSTrevor Wu } 18041de9a54aSTrevor Wu 18051de9a54aSTrevor Wu mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 18061de9a54aSTrevor Wu if (dai_id == MT8195_AFE_IO_ETDM1_OUT) 18071de9a54aSTrevor Wu fs = MT8195_ETDM_OUT1_1X_EN; 18081de9a54aSTrevor Wu else if (dai_id == MT8195_AFE_IO_ETDM2_OUT) 18091de9a54aSTrevor Wu fs = MT8195_ETDM_OUT2_1X_EN; 18101de9a54aSTrevor Wu 18111de9a54aSTrevor Wu val |= ETDM_OUT_CON4_RELATCH_EN(fs); 18121de9a54aSTrevor Wu 18131de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 18141de9a54aSTrevor Wu 18151de9a54aSTrevor Wu mask = 0; 18161de9a54aSTrevor Wu val = 0; 18171de9a54aSTrevor Wu 18181de9a54aSTrevor Wu /* con5 */ 18191de9a54aSTrevor Wu mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 18201de9a54aSTrevor Wu ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 18211de9a54aSTrevor Wu if (slave_mode) { 18221de9a54aSTrevor Wu if (etdm_data->lrck_inv) 18231de9a54aSTrevor Wu val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 18241de9a54aSTrevor Wu if (etdm_data->bck_inv) 18251de9a54aSTrevor Wu val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 18261de9a54aSTrevor Wu } else { 18271de9a54aSTrevor Wu if (etdm_data->lrck_inv) 18281de9a54aSTrevor Wu val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 18291de9a54aSTrevor Wu if (etdm_data->bck_inv) 18301de9a54aSTrevor Wu val |= ETDM_OUT_CON5_MASTER_BCK_INV; 18311de9a54aSTrevor Wu } 18321de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 18331de9a54aSTrevor Wu 18341de9a54aSTrevor Wu return 0; 18351de9a54aSTrevor Wu } 18361de9a54aSTrevor Wu 18371de9a54aSTrevor Wu static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 18381de9a54aSTrevor Wu { 18391de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 18401de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 18411de9a54aSTrevor Wu int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 18421de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 18431de9a54aSTrevor Wu int apll; 18441de9a54aSTrevor Wu int apll_clk_id; 18451de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 18461de9a54aSTrevor Wu unsigned int val = 0; 18471de9a54aSTrevor Wu unsigned int mask = 0; 18481de9a54aSTrevor Wu int ret = 0; 18491de9a54aSTrevor Wu 18501de9a54aSTrevor Wu if (clk_id < 0 || clkdiv_id < 0) 18511de9a54aSTrevor Wu return 0; 18521de9a54aSTrevor Wu 18531de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 18541de9a54aSTrevor Wu if (ret < 0) 18551de9a54aSTrevor Wu return ret; 18561de9a54aSTrevor Wu 18571de9a54aSTrevor Wu mask |= ETDM_CON1_MCLK_OUTPUT; 18581de9a54aSTrevor Wu if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 18591de9a54aSTrevor Wu val |= ETDM_CON1_MCLK_OUTPUT; 18601de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 18611de9a54aSTrevor Wu 18621de9a54aSTrevor Wu if (etdm_data->mclk_freq) { 18631de9a54aSTrevor Wu apll = etdm_data->mclk_apll; 18641de9a54aSTrevor Wu apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 18651de9a54aSTrevor Wu if (apll_clk_id < 0) 18661de9a54aSTrevor Wu return apll_clk_id; 18671de9a54aSTrevor Wu 18681de9a54aSTrevor Wu /* select apll */ 18691de9a54aSTrevor Wu ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 18701de9a54aSTrevor Wu afe_priv->clk[apll_clk_id]); 18711de9a54aSTrevor Wu if (ret) 18721de9a54aSTrevor Wu return ret; 18731de9a54aSTrevor Wu 18741de9a54aSTrevor Wu /* set rate */ 18751de9a54aSTrevor Wu ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 18761de9a54aSTrevor Wu etdm_data->mclk_freq); 18771de9a54aSTrevor Wu } else { 18781de9a54aSTrevor Wu if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 18791de9a54aSTrevor Wu dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 18801de9a54aSTrevor Wu } 18811de9a54aSTrevor Wu return ret; 18821de9a54aSTrevor Wu } 18831de9a54aSTrevor Wu 18841de9a54aSTrevor Wu static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 18851de9a54aSTrevor Wu unsigned int rate, 18861de9a54aSTrevor Wu unsigned int channels, 18871de9a54aSTrevor Wu unsigned int bit_width, 18881de9a54aSTrevor Wu int dai_id) 18891de9a54aSTrevor Wu { 18901de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 18911de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 18921de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 18931de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 18941de9a54aSTrevor Wu unsigned int etdm_channels; 18951de9a54aSTrevor Wu unsigned int val = 0; 18961de9a54aSTrevor Wu unsigned int mask = 0; 18971de9a54aSTrevor Wu unsigned int bck; 18981de9a54aSTrevor Wu unsigned int wlen = get_etdm_wlen(bit_width); 18991de9a54aSTrevor Wu int ret; 19001de9a54aSTrevor Wu 19011de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 19021de9a54aSTrevor Wu if (ret < 0) 19031de9a54aSTrevor Wu return ret; 19041de9a54aSTrevor Wu 19051de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 19061de9a54aSTrevor Wu slave_mode = true; 19071de9a54aSTrevor Wu 19081de9a54aSTrevor Wu dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 19091de9a54aSTrevor Wu __func__, etdm_data->format, etdm_data->data_mode, 19101de9a54aSTrevor Wu etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 19111de9a54aSTrevor Wu etdm_data->clock_mode, etdm_data->slave_mode); 191211a08e05SColin Ian King dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 19131de9a54aSTrevor Wu __func__, rate, channels, bit_width, dai_id); 19141de9a54aSTrevor Wu 19151de9a54aSTrevor Wu etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 19161de9a54aSTrevor Wu get_etdm_ch_fixup(channels) : 2; 19171de9a54aSTrevor Wu 19181de9a54aSTrevor Wu bck = rate * etdm_channels * wlen; 19191de9a54aSTrevor Wu if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) { 19201de9a54aSTrevor Wu dev_info(afe->dev, "%s bck rate %u not support\n", 19211de9a54aSTrevor Wu __func__, bck); 19221de9a54aSTrevor Wu return -EINVAL; 19231de9a54aSTrevor Wu } 19241de9a54aSTrevor Wu 19251de9a54aSTrevor Wu /* con0 */ 19261de9a54aSTrevor Wu mask |= ETDM_CON0_BIT_LEN_MASK; 19271de9a54aSTrevor Wu val |= ETDM_CON0_BIT_LEN(bit_width); 19281de9a54aSTrevor Wu mask |= ETDM_CON0_WORD_LEN_MASK; 19291de9a54aSTrevor Wu val |= ETDM_CON0_WORD_LEN(wlen); 19301de9a54aSTrevor Wu mask |= ETDM_CON0_FORMAT_MASK; 19311de9a54aSTrevor Wu val |= ETDM_CON0_FORMAT(etdm_data->format); 19321de9a54aSTrevor Wu mask |= ETDM_CON0_CH_NUM_MASK; 19331de9a54aSTrevor Wu val |= ETDM_CON0_CH_NUM(etdm_channels); 19341de9a54aSTrevor Wu 19351de9a54aSTrevor Wu mask |= ETDM_CON0_SLAVE_MODE; 19361de9a54aSTrevor Wu if (slave_mode) { 19371de9a54aSTrevor Wu if (dai_id == MT8195_AFE_IO_ETDM1_OUT && 19381de9a54aSTrevor Wu etdm_data->cowork_source_id == COWORK_ETDM_NONE) { 19391de9a54aSTrevor Wu dev_info(afe->dev, "%s id %d only support master mode\n", 19401de9a54aSTrevor Wu __func__, dai_id); 19411de9a54aSTrevor Wu return -EINVAL; 19421de9a54aSTrevor Wu } 19431de9a54aSTrevor Wu val |= ETDM_CON0_SLAVE_MODE; 19441de9a54aSTrevor Wu } 19451de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 19461de9a54aSTrevor Wu 19471de9a54aSTrevor Wu if (get_etdm_dir(dai_id) == ETDM_IN) 19481de9a54aSTrevor Wu mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 19491de9a54aSTrevor Wu else 19501de9a54aSTrevor Wu mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 19511de9a54aSTrevor Wu 19521de9a54aSTrevor Wu return 0; 19531de9a54aSTrevor Wu } 19541de9a54aSTrevor Wu 19551de9a54aSTrevor Wu static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 19561de9a54aSTrevor Wu struct snd_pcm_hw_params *params, 19571de9a54aSTrevor Wu struct snd_soc_dai *dai) 19581de9a54aSTrevor Wu { 19591de9a54aSTrevor Wu int ret = 0; 19601de9a54aSTrevor Wu unsigned int rate = params_rate(params); 19611de9a54aSTrevor Wu unsigned int bit_width = params_width(params); 19621de9a54aSTrevor Wu unsigned int channels = params_channels(params); 19631de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 19641de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 19651de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 19661de9a54aSTrevor Wu int mst_dai_id; 19671de9a54aSTrevor Wu int slv_dai_id; 19681de9a54aSTrevor Wu int i; 19691de9a54aSTrevor Wu 19701de9a54aSTrevor Wu dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 19711de9a54aSTrevor Wu __func__, snd_pcm_stream_str(substream), 19721de9a54aSTrevor Wu params_period_size(params), params_periods(params)); 19731de9a54aSTrevor Wu 19741de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 19751de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 19761de9a54aSTrevor Wu 19771de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 19781de9a54aSTrevor Wu if (ret) 19791de9a54aSTrevor Wu return ret; 19801de9a54aSTrevor Wu 19811de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 19821de9a54aSTrevor Wu bit_width, mst_dai_id); 19831de9a54aSTrevor Wu if (ret) 19841de9a54aSTrevor Wu return ret; 19851de9a54aSTrevor Wu 19861de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 19871de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 19881de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 19891de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 19901de9a54aSTrevor Wu bit_width, slv_dai_id); 19911de9a54aSTrevor Wu if (ret) 19921de9a54aSTrevor Wu return ret; 19931de9a54aSTrevor Wu 19941de9a54aSTrevor Wu ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id); 19951de9a54aSTrevor Wu if (ret) 19961de9a54aSTrevor Wu return ret; 19971de9a54aSTrevor Wu } 19981de9a54aSTrevor Wu } else { 19991de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 20001de9a54aSTrevor Wu if (ret) 20011de9a54aSTrevor Wu return ret; 20021de9a54aSTrevor Wu 20031de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 20041de9a54aSTrevor Wu bit_width, dai->id); 20051de9a54aSTrevor Wu } 20061de9a54aSTrevor Wu 20071de9a54aSTrevor Wu return ret; 20081de9a54aSTrevor Wu } 20091de9a54aSTrevor Wu 20101de9a54aSTrevor Wu static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, 20111de9a54aSTrevor Wu struct snd_soc_dai *dai) 20121de9a54aSTrevor Wu { 20131de9a54aSTrevor Wu int ret = 0; 20141de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 20151de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 20161de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 20171de9a54aSTrevor Wu int mst_dai_id; 20181de9a54aSTrevor Wu int slv_dai_id; 20191de9a54aSTrevor Wu int i; 20201de9a54aSTrevor Wu 20211de9a54aSTrevor Wu dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 20221de9a54aSTrevor Wu switch (cmd) { 20231de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_START: 20241de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_RESUME: 20251de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 20261de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 20271de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 20281de9a54aSTrevor Wu 20291de9a54aSTrevor Wu //open master first 20301de9a54aSTrevor Wu ret |= mt8195_afe_enable_etdm(afe, mst_dai_id); 20311de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 20321de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 20331de9a54aSTrevor Wu ret |= mt8195_afe_enable_etdm(afe, slv_dai_id); 20341de9a54aSTrevor Wu } 20351de9a54aSTrevor Wu } else { 20361de9a54aSTrevor Wu ret = mt8195_afe_enable_etdm(afe, dai->id); 20371de9a54aSTrevor Wu } 20381de9a54aSTrevor Wu break; 20391de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_STOP: 20401de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_SUSPEND: 20411de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 20421de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 20431de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 20441de9a54aSTrevor Wu 20451de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 20461de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 20471de9a54aSTrevor Wu ret |= mt8195_afe_disable_etdm(afe, slv_dai_id); 20481de9a54aSTrevor Wu } 20491de9a54aSTrevor Wu // close master at last 20501de9a54aSTrevor Wu ret |= mt8195_afe_disable_etdm(afe, mst_dai_id); 20511de9a54aSTrevor Wu } else { 20521de9a54aSTrevor Wu ret = mt8195_afe_disable_etdm(afe, dai->id); 20531de9a54aSTrevor Wu } 20541de9a54aSTrevor Wu break; 20551de9a54aSTrevor Wu default: 20561de9a54aSTrevor Wu break; 20571de9a54aSTrevor Wu } 20581de9a54aSTrevor Wu return ret; 20591de9a54aSTrevor Wu } 20601de9a54aSTrevor Wu 20611de9a54aSTrevor Wu static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 20621de9a54aSTrevor Wu { 20631de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 20641de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 20651de9a54aSTrevor Wu int apll; 20661de9a54aSTrevor Wu int apll_rate; 20671de9a54aSTrevor Wu 20681de9a54aSTrevor Wu if (freq == 0) { 20691de9a54aSTrevor Wu etdm_data->mclk_freq = freq; 20701de9a54aSTrevor Wu return 0; 20711de9a54aSTrevor Wu } 20721de9a54aSTrevor Wu 20731de9a54aSTrevor Wu apll = mt8195_afe_get_default_mclk_source_by_rate(freq); 20741de9a54aSTrevor Wu apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); 20751de9a54aSTrevor Wu 20761de9a54aSTrevor Wu if (freq > apll_rate) { 20771de9a54aSTrevor Wu dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 20781de9a54aSTrevor Wu return -EINVAL; 20791de9a54aSTrevor Wu } 20801de9a54aSTrevor Wu 20811de9a54aSTrevor Wu if (apll_rate % freq != 0) { 20821de9a54aSTrevor Wu dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 20831de9a54aSTrevor Wu return -EINVAL; 20841de9a54aSTrevor Wu } 20851de9a54aSTrevor Wu 20861de9a54aSTrevor Wu etdm_data->mclk_apll = apll; 20871de9a54aSTrevor Wu etdm_data->mclk_freq = freq; 20881de9a54aSTrevor Wu 20891de9a54aSTrevor Wu return 0; 20901de9a54aSTrevor Wu } 20911de9a54aSTrevor Wu 20921de9a54aSTrevor Wu static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 20931de9a54aSTrevor Wu int clk_id, unsigned int freq, int dir) 20941de9a54aSTrevor Wu { 20951de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 20961de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2097*d67bbddaSColin Ian King struct mtk_dai_etdm_priv *etdm_data; 20981de9a54aSTrevor Wu int dai_id; 20991de9a54aSTrevor Wu 21001de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 21011de9a54aSTrevor Wu __func__, dai->id, freq, dir); 21021de9a54aSTrevor Wu if (is_cowork_mode(dai)) 21031de9a54aSTrevor Wu dai_id = get_etdm_cowork_master_id(dai); 21041de9a54aSTrevor Wu else 21051de9a54aSTrevor Wu dai_id = dai->id; 21061de9a54aSTrevor Wu 21071de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[dai_id]; 21081de9a54aSTrevor Wu etdm_data->mclk_dir = dir; 21091de9a54aSTrevor Wu return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 21101de9a54aSTrevor Wu } 21111de9a54aSTrevor Wu 21121de9a54aSTrevor Wu static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 21131de9a54aSTrevor Wu unsigned int tx_mask, unsigned int rx_mask, 21141de9a54aSTrevor Wu int slots, int slot_width) 21151de9a54aSTrevor Wu { 21161de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 21171de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 21181de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 21191de9a54aSTrevor Wu 21201de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d slot_width %d\n", 21211de9a54aSTrevor Wu __func__, dai->id, slot_width); 21221de9a54aSTrevor Wu 21231de9a54aSTrevor Wu etdm_data->slots = slots; 21241de9a54aSTrevor Wu etdm_data->lrck_width = slot_width; 21251de9a54aSTrevor Wu return 0; 21261de9a54aSTrevor Wu } 21271de9a54aSTrevor Wu 21281de9a54aSTrevor Wu static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 21291de9a54aSTrevor Wu { 21301de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 21311de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 21321de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 21331de9a54aSTrevor Wu 21341de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 21351de9a54aSTrevor Wu case SND_SOC_DAIFMT_I2S: 21361de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 21371de9a54aSTrevor Wu break; 21381de9a54aSTrevor Wu case SND_SOC_DAIFMT_LEFT_J: 21391de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 21401de9a54aSTrevor Wu break; 21411de9a54aSTrevor Wu case SND_SOC_DAIFMT_RIGHT_J: 21421de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 21431de9a54aSTrevor Wu break; 21441de9a54aSTrevor Wu case SND_SOC_DAIFMT_DSP_A: 21451de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 21461de9a54aSTrevor Wu break; 21471de9a54aSTrevor Wu case SND_SOC_DAIFMT_DSP_B: 21481de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 21491de9a54aSTrevor Wu break; 21501de9a54aSTrevor Wu default: 21511de9a54aSTrevor Wu return -EINVAL; 21521de9a54aSTrevor Wu } 21531de9a54aSTrevor Wu 21541de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 21551de9a54aSTrevor Wu case SND_SOC_DAIFMT_NB_NF: 21561de9a54aSTrevor Wu etdm_data->bck_inv = false; 21571de9a54aSTrevor Wu etdm_data->lrck_inv = false; 21581de9a54aSTrevor Wu break; 21591de9a54aSTrevor Wu case SND_SOC_DAIFMT_NB_IF: 21601de9a54aSTrevor Wu etdm_data->bck_inv = false; 21611de9a54aSTrevor Wu etdm_data->lrck_inv = true; 21621de9a54aSTrevor Wu break; 21631de9a54aSTrevor Wu case SND_SOC_DAIFMT_IB_NF: 21641de9a54aSTrevor Wu etdm_data->bck_inv = true; 21651de9a54aSTrevor Wu etdm_data->lrck_inv = false; 21661de9a54aSTrevor Wu break; 21671de9a54aSTrevor Wu case SND_SOC_DAIFMT_IB_IF: 21681de9a54aSTrevor Wu etdm_data->bck_inv = true; 21691de9a54aSTrevor Wu etdm_data->lrck_inv = true; 21701de9a54aSTrevor Wu break; 21711de9a54aSTrevor Wu default: 21721de9a54aSTrevor Wu return -EINVAL; 21731de9a54aSTrevor Wu } 21741de9a54aSTrevor Wu 21751de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 21761de9a54aSTrevor Wu case SND_SOC_DAIFMT_CBM_CFM: 21771de9a54aSTrevor Wu etdm_data->slave_mode = true; 21781de9a54aSTrevor Wu break; 21791de9a54aSTrevor Wu case SND_SOC_DAIFMT_CBS_CFS: 21801de9a54aSTrevor Wu etdm_data->slave_mode = false; 21811de9a54aSTrevor Wu break; 21821de9a54aSTrevor Wu default: 21831de9a54aSTrevor Wu return -EINVAL; 21841de9a54aSTrevor Wu } 21851de9a54aSTrevor Wu 21861de9a54aSTrevor Wu return 0; 21871de9a54aSTrevor Wu } 21881de9a54aSTrevor Wu 21891de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 21901de9a54aSTrevor Wu struct snd_soc_dai *dai) 21911de9a54aSTrevor Wu { 21921de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 21931de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 21941de9a54aSTrevor Wu int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 21951de9a54aSTrevor Wu 21961de9a54aSTrevor Wu if (cg_id >= 0) 21971de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 21981de9a54aSTrevor Wu 21991de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 22001de9a54aSTrevor Wu 22011de9a54aSTrevor Wu return 0; 22021de9a54aSTrevor Wu } 22031de9a54aSTrevor Wu 22041de9a54aSTrevor Wu static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 22051de9a54aSTrevor Wu struct snd_soc_dai *dai) 22061de9a54aSTrevor Wu { 22071de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 22081de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 22091de9a54aSTrevor Wu int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 22101de9a54aSTrevor Wu 22111de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, dai->id); 22121de9a54aSTrevor Wu 22131de9a54aSTrevor Wu if (cg_id >= 0) 22141de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 22151de9a54aSTrevor Wu } 22161de9a54aSTrevor Wu 22171de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 22181de9a54aSTrevor Wu { 22191de9a54aSTrevor Wu switch (channel) { 22201de9a54aSTrevor Wu case 1 ... 2: 22211de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_2CH; 22221de9a54aSTrevor Wu case 3 ... 4: 22231de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_4CH; 22241de9a54aSTrevor Wu case 5 ... 6: 22251de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_6CH; 22261de9a54aSTrevor Wu case 7 ... 8: 22271de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_8CH; 22281de9a54aSTrevor Wu default: 22291de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_2CH; 22301de9a54aSTrevor Wu } 22311de9a54aSTrevor Wu } 22321de9a54aSTrevor Wu 22331de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 22341de9a54aSTrevor Wu { 22351de9a54aSTrevor Wu return (ch > 2) ? 22361de9a54aSTrevor Wu AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 22371de9a54aSTrevor Wu } 22381de9a54aSTrevor Wu 22391de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 22401de9a54aSTrevor Wu { 22411de9a54aSTrevor Wu return snd_pcm_format_physical_width(format) <= 16 ? 22421de9a54aSTrevor Wu AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 22431de9a54aSTrevor Wu } 22441de9a54aSTrevor Wu 22451de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 22461de9a54aSTrevor Wu struct snd_pcm_hw_params *params, 22471de9a54aSTrevor Wu struct snd_soc_dai *dai) 22481de9a54aSTrevor Wu { 22491de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 22501de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 22511de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 22521de9a54aSTrevor Wu unsigned int rate = params_rate(params); 22531de9a54aSTrevor Wu unsigned int channels = params_channels(params); 22541de9a54aSTrevor Wu snd_pcm_format_t format = params_format(params); 22551de9a54aSTrevor Wu int width = snd_pcm_format_physical_width(format); 22561de9a54aSTrevor Wu int ret = 0; 22571de9a54aSTrevor Wu 22581de9a54aSTrevor Wu /* dptx configure */ 22591de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) { 22601de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 22611de9a54aSTrevor Wu AFE_DPTX_CON_CH_EN_MASK, 22621de9a54aSTrevor Wu mtk_dai_get_dptx_ch_en(channels)); 22631de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 22641de9a54aSTrevor Wu AFE_DPTX_CON_CH_NUM_MASK, 22651de9a54aSTrevor Wu mtk_dai_get_dptx_ch(channels)); 22661de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 22671de9a54aSTrevor Wu AFE_DPTX_CON_16BIT_MASK, 22681de9a54aSTrevor Wu mtk_dai_get_dptx_wlen(format)); 22691de9a54aSTrevor Wu 22701de9a54aSTrevor Wu if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 22711de9a54aSTrevor Wu etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 22721de9a54aSTrevor Wu channels = 8; 22731de9a54aSTrevor Wu } else { 22741de9a54aSTrevor Wu channels = 2; 22751de9a54aSTrevor Wu } 22761de9a54aSTrevor Wu } else { 22771de9a54aSTrevor Wu etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 22781de9a54aSTrevor Wu } 22791de9a54aSTrevor Wu 22801de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 22811de9a54aSTrevor Wu if (ret) 22821de9a54aSTrevor Wu return ret; 22831de9a54aSTrevor Wu 22841de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 22851de9a54aSTrevor Wu 22861de9a54aSTrevor Wu return ret; 22871de9a54aSTrevor Wu } 22881de9a54aSTrevor Wu 22891de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream, 22901de9a54aSTrevor Wu int cmd, 22911de9a54aSTrevor Wu struct snd_soc_dai *dai) 22921de9a54aSTrevor Wu { 22931de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 22941de9a54aSTrevor Wu int ret = 0; 22951de9a54aSTrevor Wu 22961de9a54aSTrevor Wu dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 22971de9a54aSTrevor Wu 22981de9a54aSTrevor Wu switch (cmd) { 22991de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_START: 23001de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_RESUME: 23011de9a54aSTrevor Wu /* enable dptx interface */ 23021de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) 23031de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 23041de9a54aSTrevor Wu AFE_DPTX_CON_ON_MASK, 23051de9a54aSTrevor Wu AFE_DPTX_CON_ON); 23061de9a54aSTrevor Wu 23071de9a54aSTrevor Wu /* enable etdm_out3 */ 23081de9a54aSTrevor Wu ret = mt8195_afe_enable_etdm(afe, dai->id); 23091de9a54aSTrevor Wu break; 23101de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_STOP: 23111de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_SUSPEND: 23121de9a54aSTrevor Wu /* disable etdm_out3 */ 23131de9a54aSTrevor Wu ret = mt8195_afe_disable_etdm(afe, dai->id); 23141de9a54aSTrevor Wu 23151de9a54aSTrevor Wu /* disable dptx interface */ 23161de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) 23171de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 23181de9a54aSTrevor Wu AFE_DPTX_CON_ON_MASK, 0); 23191de9a54aSTrevor Wu break; 23201de9a54aSTrevor Wu default: 23211de9a54aSTrevor Wu return -EINVAL; 23221de9a54aSTrevor Wu } 23231de9a54aSTrevor Wu 23241de9a54aSTrevor Wu return ret; 23251de9a54aSTrevor Wu } 23261de9a54aSTrevor Wu 23271de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 23281de9a54aSTrevor Wu int clk_id, 23291de9a54aSTrevor Wu unsigned int freq, 23301de9a54aSTrevor Wu int dir) 23311de9a54aSTrevor Wu { 23321de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 23331de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 23341de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 23351de9a54aSTrevor Wu 23361de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 23371de9a54aSTrevor Wu __func__, dai->id, freq, dir); 23381de9a54aSTrevor Wu 23391de9a54aSTrevor Wu etdm_data->mclk_dir = dir; 23401de9a54aSTrevor Wu return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 23411de9a54aSTrevor Wu } 23421de9a54aSTrevor Wu 23431de9a54aSTrevor Wu static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 23441de9a54aSTrevor Wu .startup = mtk_dai_etdm_startup, 23451de9a54aSTrevor Wu .shutdown = mtk_dai_etdm_shutdown, 23461de9a54aSTrevor Wu .hw_params = mtk_dai_etdm_hw_params, 23471de9a54aSTrevor Wu .trigger = mtk_dai_etdm_trigger, 23481de9a54aSTrevor Wu .set_sysclk = mtk_dai_etdm_set_sysclk, 23491de9a54aSTrevor Wu .set_fmt = mtk_dai_etdm_set_fmt, 23501de9a54aSTrevor Wu .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 23511de9a54aSTrevor Wu }; 23521de9a54aSTrevor Wu 23531de9a54aSTrevor Wu static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 23541de9a54aSTrevor Wu .startup = mtk_dai_hdmitx_dptx_startup, 23551de9a54aSTrevor Wu .shutdown = mtk_dai_hdmitx_dptx_shutdown, 23561de9a54aSTrevor Wu .hw_params = mtk_dai_hdmitx_dptx_hw_params, 23571de9a54aSTrevor Wu .trigger = mtk_dai_hdmitx_dptx_trigger, 23581de9a54aSTrevor Wu .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 23591de9a54aSTrevor Wu .set_fmt = mtk_dai_etdm_set_fmt, 23601de9a54aSTrevor Wu }; 23611de9a54aSTrevor Wu 23621de9a54aSTrevor Wu /* dai driver */ 23631de9a54aSTrevor Wu #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) 23641de9a54aSTrevor Wu 23651de9a54aSTrevor Wu #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 23661de9a54aSTrevor Wu SNDRV_PCM_FMTBIT_S24_LE |\ 23671de9a54aSTrevor Wu SNDRV_PCM_FMTBIT_S32_LE) 23681de9a54aSTrevor Wu 23691de9a54aSTrevor Wu static int mtk_dai_etdm_probe(struct snd_soc_dai *dai) 23701de9a54aSTrevor Wu { 23711de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 23721de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 23731de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 23741de9a54aSTrevor Wu 23751de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id); 23761de9a54aSTrevor Wu 23771de9a54aSTrevor Wu if (etdm_data->mclk_freq) { 23781de9a54aSTrevor Wu dev_dbg(afe->dev, "MCLK always on, rate %d\n", 23791de9a54aSTrevor Wu etdm_data->mclk_freq); 23801de9a54aSTrevor Wu pm_runtime_get_sync(afe->dev); 23811de9a54aSTrevor Wu mtk_dai_etdm_mclk_configure(afe, dai->id); 23821de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 23831de9a54aSTrevor Wu pm_runtime_put_sync(afe->dev); 23841de9a54aSTrevor Wu } 23851de9a54aSTrevor Wu return 0; 23861de9a54aSTrevor Wu } 23871de9a54aSTrevor Wu 23881de9a54aSTrevor Wu static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 23891de9a54aSTrevor Wu { 23901de9a54aSTrevor Wu .name = "DPTX", 23911de9a54aSTrevor Wu .id = MT8195_AFE_IO_DPTX, 23921de9a54aSTrevor Wu .playback = { 23931de9a54aSTrevor Wu .stream_name = "DPTX Playback", 23941de9a54aSTrevor Wu .channels_min = 1, 23951de9a54aSTrevor Wu .channels_max = 8, 23961de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 23971de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 23981de9a54aSTrevor Wu }, 23991de9a54aSTrevor Wu .ops = &mtk_dai_hdmitx_dptx_ops, 24001de9a54aSTrevor Wu }, 24011de9a54aSTrevor Wu { 24021de9a54aSTrevor Wu .name = "ETDM1_IN", 24031de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM1_IN, 24041de9a54aSTrevor Wu .capture = { 24051de9a54aSTrevor Wu .stream_name = "ETDM1 Capture", 24061de9a54aSTrevor Wu .channels_min = 1, 24071de9a54aSTrevor Wu .channels_max = 24, 24081de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 24091de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 24101de9a54aSTrevor Wu }, 24111de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 24121de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 24131de9a54aSTrevor Wu }, 24141de9a54aSTrevor Wu { 24151de9a54aSTrevor Wu .name = "ETDM2_IN", 24161de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM2_IN, 24171de9a54aSTrevor Wu .capture = { 24181de9a54aSTrevor Wu .stream_name = "ETDM2 Capture", 24191de9a54aSTrevor Wu .channels_min = 1, 24201de9a54aSTrevor Wu .channels_max = 16, 24211de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 24221de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 24231de9a54aSTrevor Wu }, 24241de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 24251de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 24261de9a54aSTrevor Wu }, 24271de9a54aSTrevor Wu { 24281de9a54aSTrevor Wu .name = "ETDM1_OUT", 24291de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM1_OUT, 24301de9a54aSTrevor Wu .playback = { 24311de9a54aSTrevor Wu .stream_name = "ETDM1 Playback", 24321de9a54aSTrevor Wu .channels_min = 1, 24331de9a54aSTrevor Wu .channels_max = 24, 24341de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 24351de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 24361de9a54aSTrevor Wu }, 24371de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 24381de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 24391de9a54aSTrevor Wu }, 24401de9a54aSTrevor Wu { 24411de9a54aSTrevor Wu .name = "ETDM2_OUT", 24421de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM2_OUT, 24431de9a54aSTrevor Wu .playback = { 24441de9a54aSTrevor Wu .stream_name = "ETDM2 Playback", 24451de9a54aSTrevor Wu .channels_min = 1, 24461de9a54aSTrevor Wu .channels_max = 24, 24471de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 24481de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 24491de9a54aSTrevor Wu }, 24501de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 24511de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 24521de9a54aSTrevor Wu }, 24531de9a54aSTrevor Wu { 24541de9a54aSTrevor Wu .name = "ETDM3_OUT", 24551de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM3_OUT, 24561de9a54aSTrevor Wu .playback = { 24571de9a54aSTrevor Wu .stream_name = "ETDM3 Playback", 24581de9a54aSTrevor Wu .channels_min = 1, 24591de9a54aSTrevor Wu .channels_max = 8, 24601de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 24611de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 24621de9a54aSTrevor Wu }, 24631de9a54aSTrevor Wu .ops = &mtk_dai_hdmitx_dptx_ops, 24641de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 24651de9a54aSTrevor Wu }, 24661de9a54aSTrevor Wu }; 24671de9a54aSTrevor Wu 24681de9a54aSTrevor Wu static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe) 24691de9a54aSTrevor Wu { 24701de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 24711de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data; 24721de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_data; 24731de9a54aSTrevor Wu int i; 24741de9a54aSTrevor Wu int mst_dai_id; 24751de9a54aSTrevor Wu 24761de9a54aSTrevor Wu for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 24771de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[i]; 24781de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 24791de9a54aSTrevor Wu mst_dai_id = etdm_data->cowork_source_id; 24801de9a54aSTrevor Wu mst_data = afe_priv->dai_priv[mst_dai_id]; 24811de9a54aSTrevor Wu if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 24821de9a54aSTrevor Wu dev_info(afe->dev, "%s [%d] wrong sync source\n" 24831de9a54aSTrevor Wu , __func__, i); 24841de9a54aSTrevor Wu mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 24851de9a54aSTrevor Wu mst_data->cowork_slv_count++; 24861de9a54aSTrevor Wu } 24871de9a54aSTrevor Wu } 24881de9a54aSTrevor Wu } 24891de9a54aSTrevor Wu 24901de9a54aSTrevor Wu static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe) 24911de9a54aSTrevor Wu { 24921de9a54aSTrevor Wu const struct device_node *of_node = afe->dev->of_node; 24931de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 24941de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data; 24951de9a54aSTrevor Wu int i, j; 24961de9a54aSTrevor Wu char prop[48]; 24971de9a54aSTrevor Wu u8 disable_chn[MT8195_ETDM_MAX_CHANNELS]; 24981de9a54aSTrevor Wu int max_chn = MT8195_ETDM_MAX_CHANNELS; 24991de9a54aSTrevor Wu u32 sel; 25001de9a54aSTrevor Wu int ret; 25011de9a54aSTrevor Wu int dai_id; 25021de9a54aSTrevor Wu unsigned int sync_id; 25031de9a54aSTrevor Wu struct { 25041de9a54aSTrevor Wu const char *name; 25051de9a54aSTrevor Wu const unsigned int sync_id; 25061de9a54aSTrevor Wu } of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = { 25071de9a54aSTrevor Wu {"etdm-in1", ETDM_SYNC_FROM_IN1}, 25081de9a54aSTrevor Wu {"etdm-in2", ETDM_SYNC_FROM_IN2}, 25091de9a54aSTrevor Wu {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 25101de9a54aSTrevor Wu {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 25111de9a54aSTrevor Wu {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 25121de9a54aSTrevor Wu }; 25131de9a54aSTrevor Wu 25141de9a54aSTrevor Wu for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) { 25151de9a54aSTrevor Wu dai_id = ETDM_TO_DAI_ID(i); 25161de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[dai_id]; 25171de9a54aSTrevor Wu 25181de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 25191de9a54aSTrevor Wu "mediatek,%s-mclk-always-on-rate", 25201de9a54aSTrevor Wu of_afe_etdms[i].name); 25211de9a54aSTrevor Wu if (ret < 0) { 25221de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 25231de9a54aSTrevor Wu __func__, ret); 25241de9a54aSTrevor Wu return; 25251de9a54aSTrevor Wu } 25261de9a54aSTrevor Wu ret = of_property_read_u32(of_node, prop, &sel); 25271de9a54aSTrevor Wu if (ret == 0) { 25281de9a54aSTrevor Wu etdm_data->mclk_dir = SND_SOC_CLOCK_OUT; 25291de9a54aSTrevor Wu if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id)) 25301de9a54aSTrevor Wu dev_info(afe->dev, "%s unsupported mclk %uHz\n", 25311de9a54aSTrevor Wu __func__, sel); 25321de9a54aSTrevor Wu } 25331de9a54aSTrevor Wu 25341de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 25351de9a54aSTrevor Wu "mediatek,%s-multi-pin-mode", 25361de9a54aSTrevor Wu of_afe_etdms[i].name); 25371de9a54aSTrevor Wu if (ret < 0) { 25381de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 25391de9a54aSTrevor Wu __func__, ret); 25401de9a54aSTrevor Wu return; 25411de9a54aSTrevor Wu } 25421de9a54aSTrevor Wu etdm_data->data_mode = of_property_read_bool(of_node, prop); 25431de9a54aSTrevor Wu 25441de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 25451de9a54aSTrevor Wu "mediatek,%s-cowork-source", 25461de9a54aSTrevor Wu of_afe_etdms[i].name); 25471de9a54aSTrevor Wu if (ret < 0) { 25481de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 25491de9a54aSTrevor Wu __func__, ret); 25501de9a54aSTrevor Wu return; 25511de9a54aSTrevor Wu } 25521de9a54aSTrevor Wu ret = of_property_read_u32(of_node, prop, &sel); 25531de9a54aSTrevor Wu if (ret == 0) { 25541de9a54aSTrevor Wu if (sel >= MT8195_AFE_IO_ETDM_NUM) { 25551de9a54aSTrevor Wu dev_info(afe->dev, "%s invalid id=%d\n", 25561de9a54aSTrevor Wu __func__, sel); 25571de9a54aSTrevor Wu etdm_data->cowork_source_id = COWORK_ETDM_NONE; 25581de9a54aSTrevor Wu } else { 25591de9a54aSTrevor Wu sync_id = of_afe_etdms[sel].sync_id; 25601de9a54aSTrevor Wu etdm_data->cowork_source_id = 25611de9a54aSTrevor Wu sync_to_dai_id(sync_id); 25621de9a54aSTrevor Wu } 25631de9a54aSTrevor Wu } else { 25641de9a54aSTrevor Wu etdm_data->cowork_source_id = COWORK_ETDM_NONE; 25651de9a54aSTrevor Wu } 25661de9a54aSTrevor Wu } 25671de9a54aSTrevor Wu 25681de9a54aSTrevor Wu /* etdm in only */ 25691de9a54aSTrevor Wu for (i = 0; i < 2; i++) { 25701de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 25711de9a54aSTrevor Wu "mediatek,%s-chn-disabled", 25721de9a54aSTrevor Wu of_afe_etdms[i].name); 25731de9a54aSTrevor Wu if (ret < 0) { 25741de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 25751de9a54aSTrevor Wu __func__, ret); 25761de9a54aSTrevor Wu return; 25771de9a54aSTrevor Wu } 25781de9a54aSTrevor Wu ret = of_property_read_variable_u8_array(of_node, prop, 25791de9a54aSTrevor Wu disable_chn, 25801de9a54aSTrevor Wu 1, max_chn); 25811de9a54aSTrevor Wu if (ret < 0) 25821de9a54aSTrevor Wu continue; 25831de9a54aSTrevor Wu 25841de9a54aSTrevor Wu for (j = 0; j < ret; j++) { 25851de9a54aSTrevor Wu if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS) 25861de9a54aSTrevor Wu dev_info(afe->dev, "%s [%d] invalid chn %u\n", 25871de9a54aSTrevor Wu __func__, j, disable_chn[j]); 25881de9a54aSTrevor Wu else 25891de9a54aSTrevor Wu etdm_data->in_disable_ch[disable_chn[j]] = true; 25901de9a54aSTrevor Wu } 25911de9a54aSTrevor Wu } 25921de9a54aSTrevor Wu mt8195_etdm_update_sync_info(afe); 25931de9a54aSTrevor Wu } 25941de9a54aSTrevor Wu 25951de9a54aSTrevor Wu static int init_etdm_priv_data(struct mtk_base_afe *afe) 25961de9a54aSTrevor Wu { 25971de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 25981de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_priv; 25991de9a54aSTrevor Wu int i; 26001de9a54aSTrevor Wu 26011de9a54aSTrevor Wu for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 26021de9a54aSTrevor Wu etdm_priv = devm_kzalloc(afe->dev, 26031de9a54aSTrevor Wu sizeof(struct mtk_dai_etdm_priv), 26041de9a54aSTrevor Wu GFP_KERNEL); 26051de9a54aSTrevor Wu if (!etdm_priv) 26061de9a54aSTrevor Wu return -ENOMEM; 26071de9a54aSTrevor Wu 26081de9a54aSTrevor Wu afe_priv->dai_priv[i] = etdm_priv; 26091de9a54aSTrevor Wu } 26101de9a54aSTrevor Wu 26111de9a54aSTrevor Wu afe_priv->dai_priv[MT8195_AFE_IO_DPTX] = 26121de9a54aSTrevor Wu afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT]; 26131de9a54aSTrevor Wu 26141de9a54aSTrevor Wu mt8195_dai_etdm_parse_of(afe); 26151de9a54aSTrevor Wu return 0; 26161de9a54aSTrevor Wu } 26171de9a54aSTrevor Wu 26181de9a54aSTrevor Wu int mt8195_dai_etdm_register(struct mtk_base_afe *afe) 26191de9a54aSTrevor Wu { 26201de9a54aSTrevor Wu struct mtk_base_afe_dai *dai; 26211de9a54aSTrevor Wu 26221de9a54aSTrevor Wu dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 26231de9a54aSTrevor Wu if (!dai) 26241de9a54aSTrevor Wu return -ENOMEM; 26251de9a54aSTrevor Wu 26261de9a54aSTrevor Wu list_add(&dai->list, &afe->sub_dais); 26271de9a54aSTrevor Wu 26281de9a54aSTrevor Wu dai->dai_drivers = mtk_dai_etdm_driver; 26291de9a54aSTrevor Wu dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 26301de9a54aSTrevor Wu 26311de9a54aSTrevor Wu dai->dapm_widgets = mtk_dai_etdm_widgets; 26321de9a54aSTrevor Wu dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 26331de9a54aSTrevor Wu dai->dapm_routes = mtk_dai_etdm_routes; 26341de9a54aSTrevor Wu dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 26351de9a54aSTrevor Wu dai->controls = mtk_dai_etdm_controls; 26361de9a54aSTrevor Wu dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 26371de9a54aSTrevor Wu 26381de9a54aSTrevor Wu return init_etdm_priv_data(afe); 26391de9a54aSTrevor Wu } 2640