1*1de9a54aSTrevor Wu // SPDX-License-Identifier: GPL-2.0 2*1de9a54aSTrevor Wu /* 3*1de9a54aSTrevor Wu * MediaTek ALSA SoC Audio DAI eTDM Control 4*1de9a54aSTrevor Wu * 5*1de9a54aSTrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*1de9a54aSTrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*1de9a54aSTrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*1de9a54aSTrevor Wu */ 9*1de9a54aSTrevor Wu 10*1de9a54aSTrevor Wu #include <linux/delay.h> 11*1de9a54aSTrevor Wu #include <linux/pm_runtime.h> 12*1de9a54aSTrevor Wu #include <linux/regmap.h> 13*1de9a54aSTrevor Wu #include <sound/pcm_params.h> 14*1de9a54aSTrevor Wu #include "mt8195-afe-clk.h" 15*1de9a54aSTrevor Wu #include "mt8195-afe-common.h" 16*1de9a54aSTrevor Wu #include "mt8195-reg.h" 17*1de9a54aSTrevor Wu 18*1de9a54aSTrevor Wu #define MT8195_ETDM_MAX_CHANNELS 24 19*1de9a54aSTrevor Wu #define MT8195_ETDM_NORMAL_MAX_BCK_RATE 24576000 20*1de9a54aSTrevor Wu #define ETDM_TO_DAI_ID(x) ((x) + MT8195_AFE_IO_ETDM_START) 21*1de9a54aSTrevor Wu #define ENUM_TO_STR(x) #x 22*1de9a54aSTrevor Wu 23*1de9a54aSTrevor Wu enum { 24*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_I2S = 0, 25*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_LJ, 26*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_RJ, 27*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_EIAJ, 28*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_DSPA, 29*1de9a54aSTrevor Wu MTK_DAI_ETDM_FORMAT_DSPB, 30*1de9a54aSTrevor Wu }; 31*1de9a54aSTrevor Wu 32*1de9a54aSTrevor Wu enum { 33*1de9a54aSTrevor Wu MTK_DAI_ETDM_DATA_ONE_PIN = 0, 34*1de9a54aSTrevor Wu MTK_DAI_ETDM_DATA_MULTI_PIN, 35*1de9a54aSTrevor Wu }; 36*1de9a54aSTrevor Wu 37*1de9a54aSTrevor Wu enum { 38*1de9a54aSTrevor Wu ETDM_IN, 39*1de9a54aSTrevor Wu ETDM_OUT, 40*1de9a54aSTrevor Wu }; 41*1de9a54aSTrevor Wu 42*1de9a54aSTrevor Wu enum { 43*1de9a54aSTrevor Wu ETDM_IN_FROM_PAD, 44*1de9a54aSTrevor Wu ETDM_IN_FROM_ETDM_OUT1, 45*1de9a54aSTrevor Wu ETDM_IN_FROM_ETDM_OUT2, 46*1de9a54aSTrevor Wu }; 47*1de9a54aSTrevor Wu 48*1de9a54aSTrevor Wu enum { 49*1de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_PAD, 50*1de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_ETDM_OUT1, 51*1de9a54aSTrevor Wu ETDM_IN_SLAVE_FROM_ETDM_OUT2, 52*1de9a54aSTrevor Wu }; 53*1de9a54aSTrevor Wu 54*1de9a54aSTrevor Wu enum { 55*1de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_PAD, 56*1de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_ETDM_IN1, 57*1de9a54aSTrevor Wu ETDM_OUT_SLAVE_FROM_ETDM_IN2, 58*1de9a54aSTrevor Wu }; 59*1de9a54aSTrevor Wu 60*1de9a54aSTrevor Wu enum { 61*1de9a54aSTrevor Wu COWORK_ETDM_NONE = 0, 62*1de9a54aSTrevor Wu COWORK_ETDM_IN1_M = 2, 63*1de9a54aSTrevor Wu COWORK_ETDM_IN1_S = 3, 64*1de9a54aSTrevor Wu COWORK_ETDM_IN2_M = 4, 65*1de9a54aSTrevor Wu COWORK_ETDM_IN2_S = 5, 66*1de9a54aSTrevor Wu COWORK_ETDM_OUT1_M = 10, 67*1de9a54aSTrevor Wu COWORK_ETDM_OUT1_S = 11, 68*1de9a54aSTrevor Wu COWORK_ETDM_OUT2_M = 12, 69*1de9a54aSTrevor Wu COWORK_ETDM_OUT2_S = 13, 70*1de9a54aSTrevor Wu COWORK_ETDM_OUT3_M = 14, 71*1de9a54aSTrevor Wu COWORK_ETDM_OUT3_S = 15, 72*1de9a54aSTrevor Wu }; 73*1de9a54aSTrevor Wu 74*1de9a54aSTrevor Wu enum { 75*1de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A1A2SYS, 76*1de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A3SYS, 77*1de9a54aSTrevor Wu ETDM_RELATCH_TIMING_A4SYS, 78*1de9a54aSTrevor Wu }; 79*1de9a54aSTrevor Wu 80*1de9a54aSTrevor Wu enum { 81*1de9a54aSTrevor Wu ETDM_SYNC_NONE, 82*1de9a54aSTrevor Wu ETDM_SYNC_FROM_IN1, 83*1de9a54aSTrevor Wu ETDM_SYNC_FROM_IN2, 84*1de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT1, 85*1de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT2, 86*1de9a54aSTrevor Wu ETDM_SYNC_FROM_OUT3, 87*1de9a54aSTrevor Wu }; 88*1de9a54aSTrevor Wu 89*1de9a54aSTrevor Wu struct etdm_con_reg { 90*1de9a54aSTrevor Wu unsigned int con0; 91*1de9a54aSTrevor Wu unsigned int con1; 92*1de9a54aSTrevor Wu unsigned int con2; 93*1de9a54aSTrevor Wu unsigned int con3; 94*1de9a54aSTrevor Wu unsigned int con4; 95*1de9a54aSTrevor Wu unsigned int con5; 96*1de9a54aSTrevor Wu }; 97*1de9a54aSTrevor Wu 98*1de9a54aSTrevor Wu struct mtk_dai_etdm_rate { 99*1de9a54aSTrevor Wu unsigned int rate; 100*1de9a54aSTrevor Wu unsigned int reg_value; 101*1de9a54aSTrevor Wu }; 102*1de9a54aSTrevor Wu 103*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv { 104*1de9a54aSTrevor Wu unsigned int clock_mode; 105*1de9a54aSTrevor Wu unsigned int data_mode; 106*1de9a54aSTrevor Wu bool slave_mode; 107*1de9a54aSTrevor Wu bool lrck_inv; 108*1de9a54aSTrevor Wu bool bck_inv; 109*1de9a54aSTrevor Wu unsigned int format; 110*1de9a54aSTrevor Wu unsigned int slots; 111*1de9a54aSTrevor Wu unsigned int lrck_width; 112*1de9a54aSTrevor Wu unsigned int mclk_freq; 113*1de9a54aSTrevor Wu unsigned int mclk_apll; 114*1de9a54aSTrevor Wu unsigned int mclk_dir; 115*1de9a54aSTrevor Wu int cowork_source_id; //dai id 116*1de9a54aSTrevor Wu unsigned int cowork_slv_count; 117*1de9a54aSTrevor Wu int cowork_slv_id[MT8195_AFE_IO_ETDM_NUM - 1]; //dai_id 118*1de9a54aSTrevor Wu bool in_disable_ch[MT8195_ETDM_MAX_CHANNELS]; 119*1de9a54aSTrevor Wu unsigned int en_ref_cnt; 120*1de9a54aSTrevor Wu }; 121*1de9a54aSTrevor Wu 122*1de9a54aSTrevor Wu static const struct mtk_dai_etdm_rate mt8195_etdm_rates[] = { 123*1de9a54aSTrevor Wu { .rate = 8000, .reg_value = 0, }, 124*1de9a54aSTrevor Wu { .rate = 12000, .reg_value = 1, }, 125*1de9a54aSTrevor Wu { .rate = 16000, .reg_value = 2, }, 126*1de9a54aSTrevor Wu { .rate = 24000, .reg_value = 3, }, 127*1de9a54aSTrevor Wu { .rate = 32000, .reg_value = 4, }, 128*1de9a54aSTrevor Wu { .rate = 48000, .reg_value = 5, }, 129*1de9a54aSTrevor Wu { .rate = 96000, .reg_value = 7, }, 130*1de9a54aSTrevor Wu { .rate = 192000, .reg_value = 9, }, 131*1de9a54aSTrevor Wu { .rate = 384000, .reg_value = 11, }, 132*1de9a54aSTrevor Wu { .rate = 11025, .reg_value = 16, }, 133*1de9a54aSTrevor Wu { .rate = 22050, .reg_value = 17, }, 134*1de9a54aSTrevor Wu { .rate = 44100, .reg_value = 18, }, 135*1de9a54aSTrevor Wu { .rate = 88200, .reg_value = 19, }, 136*1de9a54aSTrevor Wu { .rate = 176400, .reg_value = 20, }, 137*1de9a54aSTrevor Wu { .rate = 352800, .reg_value = 21, }, 138*1de9a54aSTrevor Wu }; 139*1de9a54aSTrevor Wu 140*1de9a54aSTrevor Wu static int get_etdm_fs_timing(unsigned int rate) 141*1de9a54aSTrevor Wu { 142*1de9a54aSTrevor Wu int i; 143*1de9a54aSTrevor Wu 144*1de9a54aSTrevor Wu for (i = 0; i < ARRAY_SIZE(mt8195_etdm_rates); i++) 145*1de9a54aSTrevor Wu if (mt8195_etdm_rates[i].rate == rate) 146*1de9a54aSTrevor Wu return mt8195_etdm_rates[i].reg_value; 147*1de9a54aSTrevor Wu 148*1de9a54aSTrevor Wu return -EINVAL; 149*1de9a54aSTrevor Wu } 150*1de9a54aSTrevor Wu 151*1de9a54aSTrevor Wu static unsigned int get_etdm_ch_fixup(unsigned int channels) 152*1de9a54aSTrevor Wu { 153*1de9a54aSTrevor Wu if (channels > 16) 154*1de9a54aSTrevor Wu return 24; 155*1de9a54aSTrevor Wu else if (channels > 8) 156*1de9a54aSTrevor Wu return 16; 157*1de9a54aSTrevor Wu else if (channels > 4) 158*1de9a54aSTrevor Wu return 8; 159*1de9a54aSTrevor Wu else if (channels > 2) 160*1de9a54aSTrevor Wu return 4; 161*1de9a54aSTrevor Wu else 162*1de9a54aSTrevor Wu return 2; 163*1de9a54aSTrevor Wu } 164*1de9a54aSTrevor Wu 165*1de9a54aSTrevor Wu static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 166*1de9a54aSTrevor Wu { 167*1de9a54aSTrevor Wu switch (dai_id) { 168*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 169*1de9a54aSTrevor Wu etdm_reg->con0 = ETDM_IN1_CON0; 170*1de9a54aSTrevor Wu etdm_reg->con1 = ETDM_IN1_CON1; 171*1de9a54aSTrevor Wu etdm_reg->con2 = ETDM_IN1_CON2; 172*1de9a54aSTrevor Wu etdm_reg->con3 = ETDM_IN1_CON3; 173*1de9a54aSTrevor Wu etdm_reg->con4 = ETDM_IN1_CON4; 174*1de9a54aSTrevor Wu etdm_reg->con5 = ETDM_IN1_CON5; 175*1de9a54aSTrevor Wu break; 176*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 177*1de9a54aSTrevor Wu etdm_reg->con0 = ETDM_IN2_CON0; 178*1de9a54aSTrevor Wu etdm_reg->con1 = ETDM_IN2_CON1; 179*1de9a54aSTrevor Wu etdm_reg->con2 = ETDM_IN2_CON2; 180*1de9a54aSTrevor Wu etdm_reg->con3 = ETDM_IN2_CON3; 181*1de9a54aSTrevor Wu etdm_reg->con4 = ETDM_IN2_CON4; 182*1de9a54aSTrevor Wu etdm_reg->con5 = ETDM_IN2_CON5; 183*1de9a54aSTrevor Wu break; 184*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 185*1de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT1_CON0; 186*1de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT1_CON1; 187*1de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT1_CON2; 188*1de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT1_CON3; 189*1de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT1_CON4; 190*1de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT1_CON5; 191*1de9a54aSTrevor Wu break; 192*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 193*1de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT2_CON0; 194*1de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT2_CON1; 195*1de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT2_CON2; 196*1de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT2_CON3; 197*1de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT2_CON4; 198*1de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT2_CON5; 199*1de9a54aSTrevor Wu break; 200*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 201*1de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 202*1de9a54aSTrevor Wu etdm_reg->con0 = ETDM_OUT3_CON0; 203*1de9a54aSTrevor Wu etdm_reg->con1 = ETDM_OUT3_CON1; 204*1de9a54aSTrevor Wu etdm_reg->con2 = ETDM_OUT3_CON2; 205*1de9a54aSTrevor Wu etdm_reg->con3 = ETDM_OUT3_CON3; 206*1de9a54aSTrevor Wu etdm_reg->con4 = ETDM_OUT3_CON4; 207*1de9a54aSTrevor Wu etdm_reg->con5 = ETDM_OUT3_CON5; 208*1de9a54aSTrevor Wu break; 209*1de9a54aSTrevor Wu default: 210*1de9a54aSTrevor Wu return -EINVAL; 211*1de9a54aSTrevor Wu } 212*1de9a54aSTrevor Wu return 0; 213*1de9a54aSTrevor Wu } 214*1de9a54aSTrevor Wu 215*1de9a54aSTrevor Wu static int get_etdm_dir(unsigned int dai_id) 216*1de9a54aSTrevor Wu { 217*1de9a54aSTrevor Wu switch (dai_id) { 218*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 219*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 220*1de9a54aSTrevor Wu return ETDM_IN; 221*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 222*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 223*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 224*1de9a54aSTrevor Wu return ETDM_OUT; 225*1de9a54aSTrevor Wu default: 226*1de9a54aSTrevor Wu return -EINVAL; 227*1de9a54aSTrevor Wu } 228*1de9a54aSTrevor Wu } 229*1de9a54aSTrevor Wu 230*1de9a54aSTrevor Wu static int get_etdm_wlen(unsigned int bitwidth) 231*1de9a54aSTrevor Wu { 232*1de9a54aSTrevor Wu return bitwidth <= 16 ? 16 : 32; 233*1de9a54aSTrevor Wu } 234*1de9a54aSTrevor Wu 235*1de9a54aSTrevor Wu static int is_cowork_mode(struct snd_soc_dai *dai) 236*1de9a54aSTrevor Wu { 237*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 238*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 239*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 240*1de9a54aSTrevor Wu 241*1de9a54aSTrevor Wu return (etdm_data->cowork_slv_count > 0 || 242*1de9a54aSTrevor Wu etdm_data->cowork_source_id != COWORK_ETDM_NONE); 243*1de9a54aSTrevor Wu } 244*1de9a54aSTrevor Wu 245*1de9a54aSTrevor Wu static int sync_to_dai_id(int source_sel) 246*1de9a54aSTrevor Wu { 247*1de9a54aSTrevor Wu switch (source_sel) { 248*1de9a54aSTrevor Wu case ETDM_SYNC_FROM_IN1: 249*1de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM1_IN; 250*1de9a54aSTrevor Wu case ETDM_SYNC_FROM_IN2: 251*1de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM2_IN; 252*1de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT1: 253*1de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM1_OUT; 254*1de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT2: 255*1de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM2_OUT; 256*1de9a54aSTrevor Wu case ETDM_SYNC_FROM_OUT3: 257*1de9a54aSTrevor Wu return MT8195_AFE_IO_ETDM3_OUT; 258*1de9a54aSTrevor Wu default: 259*1de9a54aSTrevor Wu return 0; 260*1de9a54aSTrevor Wu } 261*1de9a54aSTrevor Wu } 262*1de9a54aSTrevor Wu 263*1de9a54aSTrevor Wu static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 264*1de9a54aSTrevor Wu { 265*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 266*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 267*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 268*1de9a54aSTrevor Wu int dai_id = etdm_data->cowork_source_id; 269*1de9a54aSTrevor Wu 270*1de9a54aSTrevor Wu if (dai_id == COWORK_ETDM_NONE) 271*1de9a54aSTrevor Wu dai_id = dai->id; 272*1de9a54aSTrevor Wu 273*1de9a54aSTrevor Wu return dai_id; 274*1de9a54aSTrevor Wu } 275*1de9a54aSTrevor Wu 276*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 277*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 278*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 279*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 280*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 281*1de9a54aSTrevor Wu }; 282*1de9a54aSTrevor Wu 283*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 284*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 285*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 286*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 287*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 288*1de9a54aSTrevor Wu }; 289*1de9a54aSTrevor Wu 290*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 291*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 292*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 293*1de9a54aSTrevor Wu }; 294*1de9a54aSTrevor Wu 295*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 296*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 297*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 298*1de9a54aSTrevor Wu }; 299*1de9a54aSTrevor Wu 300*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 301*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 302*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 303*1de9a54aSTrevor Wu }; 304*1de9a54aSTrevor Wu 305*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 306*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 307*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 308*1de9a54aSTrevor Wu }; 309*1de9a54aSTrevor Wu 310*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 311*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 312*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 313*1de9a54aSTrevor Wu }; 314*1de9a54aSTrevor Wu 315*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 316*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 317*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 318*1de9a54aSTrevor Wu }; 319*1de9a54aSTrevor Wu 320*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 321*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 322*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 323*1de9a54aSTrevor Wu }; 324*1de9a54aSTrevor Wu 325*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 326*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 327*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 328*1de9a54aSTrevor Wu }; 329*1de9a54aSTrevor Wu 330*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 331*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 332*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 333*1de9a54aSTrevor Wu }; 334*1de9a54aSTrevor Wu 335*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 336*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 337*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 338*1de9a54aSTrevor Wu }; 339*1de9a54aSTrevor Wu 340*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 341*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 342*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 343*1de9a54aSTrevor Wu }; 344*1de9a54aSTrevor Wu 345*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 346*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 347*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 348*1de9a54aSTrevor Wu }; 349*1de9a54aSTrevor Wu 350*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 351*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 352*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 353*1de9a54aSTrevor Wu }; 354*1de9a54aSTrevor Wu 355*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 356*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 357*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 358*1de9a54aSTrevor Wu }; 359*1de9a54aSTrevor Wu 360*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o064_mix[] = { 361*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN64_1, 6, 1, 0), 362*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN64_1, 30, 1, 0), 363*1de9a54aSTrevor Wu }; 364*1de9a54aSTrevor Wu 365*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o065_mix[] = { 366*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN65_1, 7, 1, 0), 367*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN65_1, 31, 1, 0), 368*1de9a54aSTrevor Wu }; 369*1de9a54aSTrevor Wu 370*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o066_mix[] = { 371*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN66_1, 8, 1, 0), 372*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN66_2, 0, 1, 0), 373*1de9a54aSTrevor Wu }; 374*1de9a54aSTrevor Wu 375*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o067_mix[] = { 376*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN67_1, 9, 1, 0), 377*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN67_2, 1, 1, 0), 378*1de9a54aSTrevor Wu }; 379*1de9a54aSTrevor Wu 380*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o068_mix[] = { 381*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN68_1, 10, 1, 0), 382*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN68_2, 2, 1, 0), 383*1de9a54aSTrevor Wu }; 384*1de9a54aSTrevor Wu 385*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o069_mix[] = { 386*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN69_1, 11, 1, 0), 387*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN69_2, 3, 1, 0), 388*1de9a54aSTrevor Wu }; 389*1de9a54aSTrevor Wu 390*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o070_mix[] = { 391*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN70_1, 12, 1, 0), 392*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN70_2, 4, 1, 0), 393*1de9a54aSTrevor Wu }; 394*1de9a54aSTrevor Wu 395*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o071_mix[] = { 396*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN71_1, 13, 1, 0), 397*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN71_2, 5, 1, 0), 398*1de9a54aSTrevor Wu }; 399*1de9a54aSTrevor Wu 400*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 401*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 402*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 403*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 404*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 405*1de9a54aSTrevor Wu }; 406*1de9a54aSTrevor Wu 407*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 408*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 409*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 410*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 411*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 412*1de9a54aSTrevor Wu }; 413*1de9a54aSTrevor Wu 414*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 415*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 416*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 417*1de9a54aSTrevor Wu }; 418*1de9a54aSTrevor Wu 419*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 420*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 421*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 422*1de9a54aSTrevor Wu }; 423*1de9a54aSTrevor Wu 424*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 425*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 426*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 427*1de9a54aSTrevor Wu }; 428*1de9a54aSTrevor Wu 429*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 430*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 431*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 432*1de9a54aSTrevor Wu }; 433*1de9a54aSTrevor Wu 434*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 435*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 436*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 437*1de9a54aSTrevor Wu }; 438*1de9a54aSTrevor Wu 439*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 440*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 441*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 442*1de9a54aSTrevor Wu }; 443*1de9a54aSTrevor Wu 444*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 445*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 446*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 447*1de9a54aSTrevor Wu }; 448*1de9a54aSTrevor Wu 449*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 450*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 451*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 452*1de9a54aSTrevor Wu }; 453*1de9a54aSTrevor Wu 454*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 455*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 456*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 457*1de9a54aSTrevor Wu }; 458*1de9a54aSTrevor Wu 459*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 460*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 461*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 462*1de9a54aSTrevor Wu }; 463*1de9a54aSTrevor Wu 464*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 465*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 466*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 467*1de9a54aSTrevor Wu }; 468*1de9a54aSTrevor Wu 469*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 470*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 471*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 472*1de9a54aSTrevor Wu }; 473*1de9a54aSTrevor Wu 474*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 475*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 476*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 477*1de9a54aSTrevor Wu }; 478*1de9a54aSTrevor Wu 479*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 480*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 481*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 482*1de9a54aSTrevor Wu }; 483*1de9a54aSTrevor Wu 484*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o088_mix[] = { 485*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I038 Switch", AFE_CONN88_1, 6, 1, 0), 486*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I062 Switch", AFE_CONN88_1, 30, 1, 0), 487*1de9a54aSTrevor Wu }; 488*1de9a54aSTrevor Wu 489*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o089_mix[] = { 490*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I039 Switch", AFE_CONN89_1, 7, 1, 0), 491*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I063 Switch", AFE_CONN89_1, 31, 1, 0), 492*1de9a54aSTrevor Wu }; 493*1de9a54aSTrevor Wu 494*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o090_mix[] = { 495*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I040 Switch", AFE_CONN90_1, 8, 1, 0), 496*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I064 Switch", AFE_CONN90_2, 0, 1, 0), 497*1de9a54aSTrevor Wu }; 498*1de9a54aSTrevor Wu 499*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o091_mix[] = { 500*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I041 Switch", AFE_CONN91_1, 9, 1, 0), 501*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I065 Switch", AFE_CONN91_2, 1, 1, 0), 502*1de9a54aSTrevor Wu }; 503*1de9a54aSTrevor Wu 504*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o092_mix[] = { 505*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I042 Switch", AFE_CONN92_1, 10, 1, 0), 506*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I066 Switch", AFE_CONN92_2, 2, 1, 0), 507*1de9a54aSTrevor Wu }; 508*1de9a54aSTrevor Wu 509*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o093_mix[] = { 510*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I043 Switch", AFE_CONN93_1, 11, 1, 0), 511*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I067 Switch", AFE_CONN93_2, 3, 1, 0), 512*1de9a54aSTrevor Wu }; 513*1de9a54aSTrevor Wu 514*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o094_mix[] = { 515*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I044 Switch", AFE_CONN94_1, 12, 1, 0), 516*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I068 Switch", AFE_CONN94_2, 4, 1, 0), 517*1de9a54aSTrevor Wu }; 518*1de9a54aSTrevor Wu 519*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_o095_mix[] = { 520*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I045 Switch", AFE_CONN95_1, 13, 1, 0), 521*1de9a54aSTrevor Wu SOC_DAPM_SINGLE_AUTODISABLE("I069 Switch", AFE_CONN95_2, 5, 1, 0), 522*1de9a54aSTrevor Wu }; 523*1de9a54aSTrevor Wu 524*1de9a54aSTrevor Wu static const char * const mt8195_etdm_clk_src_sel_text[] = { 525*1de9a54aSTrevor Wu "26m", 526*1de9a54aSTrevor Wu "a1sys_a2sys", 527*1de9a54aSTrevor Wu "a3sys", 528*1de9a54aSTrevor Wu "a4sys", 529*1de9a54aSTrevor Wu }; 530*1de9a54aSTrevor Wu 531*1de9a54aSTrevor Wu static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 532*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_text); 533*1de9a54aSTrevor Wu 534*1de9a54aSTrevor Wu static const char * const hdmitx_dptx_mux_map[] = { 535*1de9a54aSTrevor Wu "Disconnect", "Connect", 536*1de9a54aSTrevor Wu }; 537*1de9a54aSTrevor Wu 538*1de9a54aSTrevor Wu static int hdmitx_dptx_mux_map_value[] = { 539*1de9a54aSTrevor Wu 0, 1, 540*1de9a54aSTrevor Wu }; 541*1de9a54aSTrevor Wu 542*1de9a54aSTrevor Wu /* HDMI_OUT_MUX */ 543*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 544*1de9a54aSTrevor Wu SND_SOC_NOPM, 545*1de9a54aSTrevor Wu 0, 546*1de9a54aSTrevor Wu 1, 547*1de9a54aSTrevor Wu hdmitx_dptx_mux_map, 548*1de9a54aSTrevor Wu hdmitx_dptx_mux_map_value); 549*1de9a54aSTrevor Wu 550*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_out_mux_control = 551*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 552*1de9a54aSTrevor Wu 553*1de9a54aSTrevor Wu /* DPTX_OUT_MUX */ 554*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 555*1de9a54aSTrevor Wu SND_SOC_NOPM, 556*1de9a54aSTrevor Wu 0, 557*1de9a54aSTrevor Wu 1, 558*1de9a54aSTrevor Wu hdmitx_dptx_mux_map, 559*1de9a54aSTrevor Wu hdmitx_dptx_mux_map_value); 560*1de9a54aSTrevor Wu 561*1de9a54aSTrevor Wu static const struct snd_kcontrol_new dptx_out_mux_control = 562*1de9a54aSTrevor Wu SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 563*1de9a54aSTrevor Wu 564*1de9a54aSTrevor Wu /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 565*1de9a54aSTrevor Wu static const char *const afe_conn_hdmi_mux_map[] = { 566*1de9a54aSTrevor Wu "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 567*1de9a54aSTrevor Wu }; 568*1de9a54aSTrevor Wu 569*1de9a54aSTrevor Wu static int afe_conn_hdmi_mux_map_value[] = { 570*1de9a54aSTrevor Wu 0, 1, 2, 3, 4, 5, 6, 7, 571*1de9a54aSTrevor Wu }; 572*1de9a54aSTrevor Wu 573*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 574*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 575*1de9a54aSTrevor Wu 0, 576*1de9a54aSTrevor Wu 0xf, 577*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 578*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 579*1de9a54aSTrevor Wu 580*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch0_mux_control = 581*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 582*1de9a54aSTrevor Wu 583*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 584*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 585*1de9a54aSTrevor Wu 4, 586*1de9a54aSTrevor Wu 0xf, 587*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 588*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 589*1de9a54aSTrevor Wu 590*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch1_mux_control = 591*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 592*1de9a54aSTrevor Wu 593*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 594*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 595*1de9a54aSTrevor Wu 8, 596*1de9a54aSTrevor Wu 0xf, 597*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 598*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 599*1de9a54aSTrevor Wu 600*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch2_mux_control = 601*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 602*1de9a54aSTrevor Wu 603*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 604*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 605*1de9a54aSTrevor Wu 12, 606*1de9a54aSTrevor Wu 0xf, 607*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 608*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 609*1de9a54aSTrevor Wu 610*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch3_mux_control = 611*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 612*1de9a54aSTrevor Wu 613*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 614*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 615*1de9a54aSTrevor Wu 16, 616*1de9a54aSTrevor Wu 0xf, 617*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 618*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 619*1de9a54aSTrevor Wu 620*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch4_mux_control = 621*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 622*1de9a54aSTrevor Wu 623*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 624*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 625*1de9a54aSTrevor Wu 20, 626*1de9a54aSTrevor Wu 0xf, 627*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 628*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 629*1de9a54aSTrevor Wu 630*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch5_mux_control = 631*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 632*1de9a54aSTrevor Wu 633*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 634*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 635*1de9a54aSTrevor Wu 24, 636*1de9a54aSTrevor Wu 0xf, 637*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 638*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 639*1de9a54aSTrevor Wu 640*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch6_mux_control = 641*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 642*1de9a54aSTrevor Wu 643*1de9a54aSTrevor Wu static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 644*1de9a54aSTrevor Wu AFE_TDMOUT_CONN0, 645*1de9a54aSTrevor Wu 28, 646*1de9a54aSTrevor Wu 0xf, 647*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map, 648*1de9a54aSTrevor Wu afe_conn_hdmi_mux_map_value); 649*1de9a54aSTrevor Wu 650*1de9a54aSTrevor Wu static const struct snd_kcontrol_new hdmi_ch7_mux_control = 651*1de9a54aSTrevor Wu SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 652*1de9a54aSTrevor Wu 653*1de9a54aSTrevor Wu static int mt8195_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 654*1de9a54aSTrevor Wu struct snd_ctl_elem_value *ucontrol) 655*1de9a54aSTrevor Wu { 656*1de9a54aSTrevor Wu struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 657*1de9a54aSTrevor Wu struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 658*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 659*1de9a54aSTrevor Wu unsigned int source = ucontrol->value.enumerated.item[0]; 660*1de9a54aSTrevor Wu unsigned int val; 661*1de9a54aSTrevor Wu unsigned int mask; 662*1de9a54aSTrevor Wu unsigned int reg; 663*1de9a54aSTrevor Wu 664*1de9a54aSTrevor Wu if (source >= e->items) 665*1de9a54aSTrevor Wu return -EINVAL; 666*1de9a54aSTrevor Wu 667*1de9a54aSTrevor Wu reg = 0; 668*1de9a54aSTrevor Wu if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 669*1de9a54aSTrevor Wu reg = ETDM_OUT1_CON4; 670*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 671*1de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 672*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 673*1de9a54aSTrevor Wu reg = ETDM_OUT2_CON4; 674*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 675*1de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 676*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 677*1de9a54aSTrevor Wu reg = ETDM_OUT3_CON4; 678*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 679*1de9a54aSTrevor Wu val = ETDM_OUT_CON4_CLOCK(source); 680*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 681*1de9a54aSTrevor Wu reg = ETDM_IN1_CON2; 682*1de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 683*1de9a54aSTrevor Wu val = ETDM_IN_CON2_CLOCK(source); 684*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 685*1de9a54aSTrevor Wu reg = ETDM_IN2_CON2; 686*1de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 687*1de9a54aSTrevor Wu val = ETDM_IN_CON2_CLOCK(source); 688*1de9a54aSTrevor Wu } 689*1de9a54aSTrevor Wu 690*1de9a54aSTrevor Wu if (reg) 691*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 692*1de9a54aSTrevor Wu 693*1de9a54aSTrevor Wu return 0; 694*1de9a54aSTrevor Wu } 695*1de9a54aSTrevor Wu 696*1de9a54aSTrevor Wu static int mt8195_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 697*1de9a54aSTrevor Wu struct snd_ctl_elem_value *ucontrol) 698*1de9a54aSTrevor Wu { 699*1de9a54aSTrevor Wu struct snd_soc_component *component = 700*1de9a54aSTrevor Wu snd_soc_kcontrol_component(kcontrol); 701*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 702*1de9a54aSTrevor Wu unsigned int value = 0; 703*1de9a54aSTrevor Wu unsigned int reg = 0; 704*1de9a54aSTrevor Wu unsigned int mask = 0; 705*1de9a54aSTrevor Wu unsigned int shift = 0; 706*1de9a54aSTrevor Wu 707*1de9a54aSTrevor Wu if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 708*1de9a54aSTrevor Wu reg = ETDM_OUT1_CON4; 709*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 710*1de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 711*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 712*1de9a54aSTrevor Wu reg = ETDM_OUT2_CON4; 713*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 714*1de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 715*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 716*1de9a54aSTrevor Wu reg = ETDM_OUT3_CON4; 717*1de9a54aSTrevor Wu mask = ETDM_OUT_CON4_CLOCK_MASK; 718*1de9a54aSTrevor Wu shift = ETDM_OUT_CON4_CLOCK_SHIFT; 719*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 720*1de9a54aSTrevor Wu reg = ETDM_IN1_CON2; 721*1de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 722*1de9a54aSTrevor Wu shift = ETDM_IN_CON2_CLOCK_SHIFT; 723*1de9a54aSTrevor Wu } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 724*1de9a54aSTrevor Wu reg = ETDM_IN2_CON2; 725*1de9a54aSTrevor Wu mask = ETDM_IN_CON2_CLOCK_MASK; 726*1de9a54aSTrevor Wu shift = ETDM_IN_CON2_CLOCK_SHIFT; 727*1de9a54aSTrevor Wu } 728*1de9a54aSTrevor Wu 729*1de9a54aSTrevor Wu if (reg) 730*1de9a54aSTrevor Wu regmap_read(afe->regmap, reg, &value); 731*1de9a54aSTrevor Wu 732*1de9a54aSTrevor Wu value &= mask; 733*1de9a54aSTrevor Wu value >>= shift; 734*1de9a54aSTrevor Wu ucontrol->value.enumerated.item[0] = value; 735*1de9a54aSTrevor Wu return 0; 736*1de9a54aSTrevor Wu } 737*1de9a54aSTrevor Wu 738*1de9a54aSTrevor Wu static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 739*1de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", 740*1de9a54aSTrevor Wu etdmout_clk_src_enum, 741*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 742*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 743*1de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", 744*1de9a54aSTrevor Wu etdmout_clk_src_enum, 745*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 746*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 747*1de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", 748*1de9a54aSTrevor Wu etdmout_clk_src_enum, 749*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 750*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 751*1de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_IN1_Clock_Source", 752*1de9a54aSTrevor Wu etdmout_clk_src_enum, 753*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 754*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 755*1de9a54aSTrevor Wu SOC_ENUM_EXT("ETDM_IN2_Clock_Source", 756*1de9a54aSTrevor Wu etdmout_clk_src_enum, 757*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_get, 758*1de9a54aSTrevor Wu mt8195_etdm_clk_src_sel_put), 759*1de9a54aSTrevor Wu }; 760*1de9a54aSTrevor Wu 761*1de9a54aSTrevor Wu static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 762*1de9a54aSTrevor Wu /* eTDM_IN2 */ 763*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 764*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 765*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 766*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 767*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 768*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 769*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 770*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 771*1de9a54aSTrevor Wu 772*1de9a54aSTrevor Wu /* eTDM_IN1 */ 773*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 774*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 775*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 776*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 777*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 778*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 779*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 780*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 781*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 782*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 783*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 784*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 785*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 786*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 787*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 788*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 789*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I088", SND_SOC_NOPM, 0, 0, NULL, 0), 790*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I089", SND_SOC_NOPM, 0, 0, NULL, 0), 791*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I090", SND_SOC_NOPM, 0, 0, NULL, 0), 792*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I091", SND_SOC_NOPM, 0, 0, NULL, 0), 793*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I092", SND_SOC_NOPM, 0, 0, NULL, 0), 794*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I093", SND_SOC_NOPM, 0, 0, NULL, 0), 795*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I094", SND_SOC_NOPM, 0, 0, NULL, 0), 796*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("I095", SND_SOC_NOPM, 0, 0, NULL, 0), 797*1de9a54aSTrevor Wu 798*1de9a54aSTrevor Wu /* eTDM_OUT2 */ 799*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 800*1de9a54aSTrevor Wu mtk_dai_etdm_o048_mix, 801*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 802*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 803*1de9a54aSTrevor Wu mtk_dai_etdm_o049_mix, 804*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 805*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 806*1de9a54aSTrevor Wu mtk_dai_etdm_o050_mix, 807*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 808*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 809*1de9a54aSTrevor Wu mtk_dai_etdm_o051_mix, 810*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 811*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 812*1de9a54aSTrevor Wu mtk_dai_etdm_o052_mix, 813*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 814*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 815*1de9a54aSTrevor Wu mtk_dai_etdm_o053_mix, 816*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 817*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 818*1de9a54aSTrevor Wu mtk_dai_etdm_o054_mix, 819*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 820*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 821*1de9a54aSTrevor Wu mtk_dai_etdm_o055_mix, 822*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 823*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 824*1de9a54aSTrevor Wu mtk_dai_etdm_o056_mix, 825*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 826*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 827*1de9a54aSTrevor Wu mtk_dai_etdm_o057_mix, 828*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 829*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 830*1de9a54aSTrevor Wu mtk_dai_etdm_o058_mix, 831*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 832*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 833*1de9a54aSTrevor Wu mtk_dai_etdm_o059_mix, 834*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 835*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 836*1de9a54aSTrevor Wu mtk_dai_etdm_o060_mix, 837*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 838*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 839*1de9a54aSTrevor Wu mtk_dai_etdm_o061_mix, 840*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 841*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 842*1de9a54aSTrevor Wu mtk_dai_etdm_o062_mix, 843*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 844*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 845*1de9a54aSTrevor Wu mtk_dai_etdm_o063_mix, 846*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 847*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O064", SND_SOC_NOPM, 0, 0, 848*1de9a54aSTrevor Wu mtk_dai_etdm_o064_mix, 849*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o064_mix)), 850*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O065", SND_SOC_NOPM, 0, 0, 851*1de9a54aSTrevor Wu mtk_dai_etdm_o065_mix, 852*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o065_mix)), 853*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O066", SND_SOC_NOPM, 0, 0, 854*1de9a54aSTrevor Wu mtk_dai_etdm_o066_mix, 855*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o066_mix)), 856*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O067", SND_SOC_NOPM, 0, 0, 857*1de9a54aSTrevor Wu mtk_dai_etdm_o067_mix, 858*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o067_mix)), 859*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O068", SND_SOC_NOPM, 0, 0, 860*1de9a54aSTrevor Wu mtk_dai_etdm_o068_mix, 861*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o068_mix)), 862*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O069", SND_SOC_NOPM, 0, 0, 863*1de9a54aSTrevor Wu mtk_dai_etdm_o069_mix, 864*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o069_mix)), 865*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O070", SND_SOC_NOPM, 0, 0, 866*1de9a54aSTrevor Wu mtk_dai_etdm_o070_mix, 867*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o070_mix)), 868*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O071", SND_SOC_NOPM, 0, 0, 869*1de9a54aSTrevor Wu mtk_dai_etdm_o071_mix, 870*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o071_mix)), 871*1de9a54aSTrevor Wu 872*1de9a54aSTrevor Wu /* eTDM_OUT1 */ 873*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 874*1de9a54aSTrevor Wu mtk_dai_etdm_o072_mix, 875*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 876*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 877*1de9a54aSTrevor Wu mtk_dai_etdm_o073_mix, 878*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 879*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 880*1de9a54aSTrevor Wu mtk_dai_etdm_o074_mix, 881*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 882*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 883*1de9a54aSTrevor Wu mtk_dai_etdm_o075_mix, 884*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 885*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 886*1de9a54aSTrevor Wu mtk_dai_etdm_o076_mix, 887*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 888*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 889*1de9a54aSTrevor Wu mtk_dai_etdm_o077_mix, 890*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 891*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 892*1de9a54aSTrevor Wu mtk_dai_etdm_o078_mix, 893*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 894*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 895*1de9a54aSTrevor Wu mtk_dai_etdm_o079_mix, 896*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 897*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 898*1de9a54aSTrevor Wu mtk_dai_etdm_o080_mix, 899*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 900*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 901*1de9a54aSTrevor Wu mtk_dai_etdm_o081_mix, 902*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 903*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 904*1de9a54aSTrevor Wu mtk_dai_etdm_o082_mix, 905*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 906*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 907*1de9a54aSTrevor Wu mtk_dai_etdm_o083_mix, 908*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 909*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 910*1de9a54aSTrevor Wu mtk_dai_etdm_o084_mix, 911*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 912*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 913*1de9a54aSTrevor Wu mtk_dai_etdm_o085_mix, 914*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 915*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 916*1de9a54aSTrevor Wu mtk_dai_etdm_o086_mix, 917*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 918*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 919*1de9a54aSTrevor Wu mtk_dai_etdm_o087_mix, 920*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 921*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O088", SND_SOC_NOPM, 0, 0, 922*1de9a54aSTrevor Wu mtk_dai_etdm_o088_mix, 923*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o088_mix)), 924*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O089", SND_SOC_NOPM, 0, 0, 925*1de9a54aSTrevor Wu mtk_dai_etdm_o089_mix, 926*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o089_mix)), 927*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O090", SND_SOC_NOPM, 0, 0, 928*1de9a54aSTrevor Wu mtk_dai_etdm_o090_mix, 929*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o090_mix)), 930*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O091", SND_SOC_NOPM, 0, 0, 931*1de9a54aSTrevor Wu mtk_dai_etdm_o091_mix, 932*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o091_mix)), 933*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O092", SND_SOC_NOPM, 0, 0, 934*1de9a54aSTrevor Wu mtk_dai_etdm_o092_mix, 935*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o092_mix)), 936*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O093", SND_SOC_NOPM, 0, 0, 937*1de9a54aSTrevor Wu mtk_dai_etdm_o093_mix, 938*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o093_mix)), 939*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O094", SND_SOC_NOPM, 0, 0, 940*1de9a54aSTrevor Wu mtk_dai_etdm_o094_mix, 941*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o094_mix)), 942*1de9a54aSTrevor Wu SND_SOC_DAPM_MIXER("O095", SND_SOC_NOPM, 0, 0, 943*1de9a54aSTrevor Wu mtk_dai_etdm_o095_mix, 944*1de9a54aSTrevor Wu ARRAY_SIZE(mtk_dai_etdm_o095_mix)), 945*1de9a54aSTrevor Wu 946*1de9a54aSTrevor Wu /* eTDM_OUT3 */ 947*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 948*1de9a54aSTrevor Wu &hdmi_out_mux_control), 949*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 950*1de9a54aSTrevor Wu &dptx_out_mux_control), 951*1de9a54aSTrevor Wu 952*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 953*1de9a54aSTrevor Wu &hdmi_ch0_mux_control), 954*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 955*1de9a54aSTrevor Wu &hdmi_ch1_mux_control), 956*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 957*1de9a54aSTrevor Wu &hdmi_ch2_mux_control), 958*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 959*1de9a54aSTrevor Wu &hdmi_ch3_mux_control), 960*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 961*1de9a54aSTrevor Wu &hdmi_ch4_mux_control), 962*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 963*1de9a54aSTrevor Wu &hdmi_ch5_mux_control), 964*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 965*1de9a54aSTrevor Wu &hdmi_ch6_mux_control), 966*1de9a54aSTrevor Wu SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 967*1de9a54aSTrevor Wu &hdmi_ch7_mux_control), 968*1de9a54aSTrevor Wu 969*1de9a54aSTrevor Wu SND_SOC_DAPM_INPUT("ETDM_INPUT"), 970*1de9a54aSTrevor Wu SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 971*1de9a54aSTrevor Wu }; 972*1de9a54aSTrevor Wu 973*1de9a54aSTrevor Wu static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 974*1de9a54aSTrevor Wu {"I012", NULL, "ETDM2 Capture"}, 975*1de9a54aSTrevor Wu {"I013", NULL, "ETDM2 Capture"}, 976*1de9a54aSTrevor Wu {"I014", NULL, "ETDM2 Capture"}, 977*1de9a54aSTrevor Wu {"I015", NULL, "ETDM2 Capture"}, 978*1de9a54aSTrevor Wu {"I016", NULL, "ETDM2 Capture"}, 979*1de9a54aSTrevor Wu {"I017", NULL, "ETDM2 Capture"}, 980*1de9a54aSTrevor Wu {"I018", NULL, "ETDM2 Capture"}, 981*1de9a54aSTrevor Wu {"I019", NULL, "ETDM2 Capture"}, 982*1de9a54aSTrevor Wu 983*1de9a54aSTrevor Wu {"I072", NULL, "ETDM1 Capture"}, 984*1de9a54aSTrevor Wu {"I073", NULL, "ETDM1 Capture"}, 985*1de9a54aSTrevor Wu {"I074", NULL, "ETDM1 Capture"}, 986*1de9a54aSTrevor Wu {"I075", NULL, "ETDM1 Capture"}, 987*1de9a54aSTrevor Wu {"I076", NULL, "ETDM1 Capture"}, 988*1de9a54aSTrevor Wu {"I077", NULL, "ETDM1 Capture"}, 989*1de9a54aSTrevor Wu {"I078", NULL, "ETDM1 Capture"}, 990*1de9a54aSTrevor Wu {"I079", NULL, "ETDM1 Capture"}, 991*1de9a54aSTrevor Wu {"I080", NULL, "ETDM1 Capture"}, 992*1de9a54aSTrevor Wu {"I081", NULL, "ETDM1 Capture"}, 993*1de9a54aSTrevor Wu {"I082", NULL, "ETDM1 Capture"}, 994*1de9a54aSTrevor Wu {"I083", NULL, "ETDM1 Capture"}, 995*1de9a54aSTrevor Wu {"I084", NULL, "ETDM1 Capture"}, 996*1de9a54aSTrevor Wu {"I085", NULL, "ETDM1 Capture"}, 997*1de9a54aSTrevor Wu {"I086", NULL, "ETDM1 Capture"}, 998*1de9a54aSTrevor Wu {"I087", NULL, "ETDM1 Capture"}, 999*1de9a54aSTrevor Wu {"I088", NULL, "ETDM1 Capture"}, 1000*1de9a54aSTrevor Wu {"I089", NULL, "ETDM1 Capture"}, 1001*1de9a54aSTrevor Wu {"I090", NULL, "ETDM1 Capture"}, 1002*1de9a54aSTrevor Wu {"I091", NULL, "ETDM1 Capture"}, 1003*1de9a54aSTrevor Wu {"I092", NULL, "ETDM1 Capture"}, 1004*1de9a54aSTrevor Wu {"I093", NULL, "ETDM1 Capture"}, 1005*1de9a54aSTrevor Wu {"I094", NULL, "ETDM1 Capture"}, 1006*1de9a54aSTrevor Wu {"I095", NULL, "ETDM1 Capture"}, 1007*1de9a54aSTrevor Wu 1008*1de9a54aSTrevor Wu {"UL8", NULL, "ETDM1 Capture"}, 1009*1de9a54aSTrevor Wu {"UL3", NULL, "ETDM2 Capture"}, 1010*1de9a54aSTrevor Wu 1011*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O048"}, 1012*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O049"}, 1013*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O050"}, 1014*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O051"}, 1015*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O052"}, 1016*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O053"}, 1017*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O054"}, 1018*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O055"}, 1019*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O056"}, 1020*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O057"}, 1021*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O058"}, 1022*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O059"}, 1023*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O060"}, 1024*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O061"}, 1025*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O062"}, 1026*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O063"}, 1027*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O064"}, 1028*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O065"}, 1029*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O066"}, 1030*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O067"}, 1031*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O068"}, 1032*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O069"}, 1033*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O070"}, 1034*1de9a54aSTrevor Wu {"ETDM2 Playback", NULL, "O071"}, 1035*1de9a54aSTrevor Wu 1036*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O072"}, 1037*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O073"}, 1038*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O074"}, 1039*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O075"}, 1040*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O076"}, 1041*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O077"}, 1042*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O078"}, 1043*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O079"}, 1044*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O080"}, 1045*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O081"}, 1046*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O082"}, 1047*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O083"}, 1048*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O084"}, 1049*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O085"}, 1050*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O086"}, 1051*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O087"}, 1052*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O088"}, 1053*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O089"}, 1054*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O090"}, 1055*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O091"}, 1056*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O092"}, 1057*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O093"}, 1058*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O094"}, 1059*1de9a54aSTrevor Wu {"ETDM1 Playback", NULL, "O095"}, 1060*1de9a54aSTrevor Wu 1061*1de9a54aSTrevor Wu {"O048", "I020 Switch", "I020"}, 1062*1de9a54aSTrevor Wu {"O049", "I021 Switch", "I021"}, 1063*1de9a54aSTrevor Wu 1064*1de9a54aSTrevor Wu {"O048", "I022 Switch", "I022"}, 1065*1de9a54aSTrevor Wu {"O049", "I023 Switch", "I023"}, 1066*1de9a54aSTrevor Wu {"O050", "I024 Switch", "I024"}, 1067*1de9a54aSTrevor Wu {"O051", "I025 Switch", "I025"}, 1068*1de9a54aSTrevor Wu {"O052", "I026 Switch", "I026"}, 1069*1de9a54aSTrevor Wu {"O053", "I027 Switch", "I027"}, 1070*1de9a54aSTrevor Wu {"O054", "I028 Switch", "I028"}, 1071*1de9a54aSTrevor Wu {"O055", "I029 Switch", "I029"}, 1072*1de9a54aSTrevor Wu {"O056", "I030 Switch", "I030"}, 1073*1de9a54aSTrevor Wu {"O057", "I031 Switch", "I031"}, 1074*1de9a54aSTrevor Wu {"O058", "I032 Switch", "I032"}, 1075*1de9a54aSTrevor Wu {"O059", "I033 Switch", "I033"}, 1076*1de9a54aSTrevor Wu {"O060", "I034 Switch", "I034"}, 1077*1de9a54aSTrevor Wu {"O061", "I035 Switch", "I035"}, 1078*1de9a54aSTrevor Wu {"O062", "I036 Switch", "I036"}, 1079*1de9a54aSTrevor Wu {"O063", "I037 Switch", "I037"}, 1080*1de9a54aSTrevor Wu {"O064", "I038 Switch", "I038"}, 1081*1de9a54aSTrevor Wu {"O065", "I039 Switch", "I039"}, 1082*1de9a54aSTrevor Wu {"O066", "I040 Switch", "I040"}, 1083*1de9a54aSTrevor Wu {"O067", "I041 Switch", "I041"}, 1084*1de9a54aSTrevor Wu {"O068", "I042 Switch", "I042"}, 1085*1de9a54aSTrevor Wu {"O069", "I043 Switch", "I043"}, 1086*1de9a54aSTrevor Wu {"O070", "I044 Switch", "I044"}, 1087*1de9a54aSTrevor Wu {"O071", "I045 Switch", "I045"}, 1088*1de9a54aSTrevor Wu 1089*1de9a54aSTrevor Wu {"O048", "I046 Switch", "I046"}, 1090*1de9a54aSTrevor Wu {"O049", "I047 Switch", "I047"}, 1091*1de9a54aSTrevor Wu {"O050", "I048 Switch", "I048"}, 1092*1de9a54aSTrevor Wu {"O051", "I049 Switch", "I049"}, 1093*1de9a54aSTrevor Wu {"O052", "I050 Switch", "I050"}, 1094*1de9a54aSTrevor Wu {"O053", "I051 Switch", "I051"}, 1095*1de9a54aSTrevor Wu {"O054", "I052 Switch", "I052"}, 1096*1de9a54aSTrevor Wu {"O055", "I053 Switch", "I053"}, 1097*1de9a54aSTrevor Wu {"O056", "I054 Switch", "I054"}, 1098*1de9a54aSTrevor Wu {"O057", "I055 Switch", "I055"}, 1099*1de9a54aSTrevor Wu {"O058", "I056 Switch", "I056"}, 1100*1de9a54aSTrevor Wu {"O059", "I057 Switch", "I057"}, 1101*1de9a54aSTrevor Wu {"O060", "I058 Switch", "I058"}, 1102*1de9a54aSTrevor Wu {"O061", "I059 Switch", "I059"}, 1103*1de9a54aSTrevor Wu {"O062", "I060 Switch", "I060"}, 1104*1de9a54aSTrevor Wu {"O063", "I061 Switch", "I061"}, 1105*1de9a54aSTrevor Wu {"O064", "I062 Switch", "I062"}, 1106*1de9a54aSTrevor Wu {"O065", "I063 Switch", "I063"}, 1107*1de9a54aSTrevor Wu {"O066", "I064 Switch", "I064"}, 1108*1de9a54aSTrevor Wu {"O067", "I065 Switch", "I065"}, 1109*1de9a54aSTrevor Wu {"O068", "I066 Switch", "I066"}, 1110*1de9a54aSTrevor Wu {"O069", "I067 Switch", "I067"}, 1111*1de9a54aSTrevor Wu {"O070", "I068 Switch", "I068"}, 1112*1de9a54aSTrevor Wu {"O071", "I069 Switch", "I069"}, 1113*1de9a54aSTrevor Wu 1114*1de9a54aSTrevor Wu {"O048", "I070 Switch", "I070"}, 1115*1de9a54aSTrevor Wu {"O049", "I071 Switch", "I071"}, 1116*1de9a54aSTrevor Wu 1117*1de9a54aSTrevor Wu {"O072", "I020 Switch", "I020"}, 1118*1de9a54aSTrevor Wu {"O073", "I021 Switch", "I021"}, 1119*1de9a54aSTrevor Wu 1120*1de9a54aSTrevor Wu {"O072", "I022 Switch", "I022"}, 1121*1de9a54aSTrevor Wu {"O073", "I023 Switch", "I023"}, 1122*1de9a54aSTrevor Wu {"O074", "I024 Switch", "I024"}, 1123*1de9a54aSTrevor Wu {"O075", "I025 Switch", "I025"}, 1124*1de9a54aSTrevor Wu {"O076", "I026 Switch", "I026"}, 1125*1de9a54aSTrevor Wu {"O077", "I027 Switch", "I027"}, 1126*1de9a54aSTrevor Wu {"O078", "I028 Switch", "I028"}, 1127*1de9a54aSTrevor Wu {"O079", "I029 Switch", "I029"}, 1128*1de9a54aSTrevor Wu {"O080", "I030 Switch", "I030"}, 1129*1de9a54aSTrevor Wu {"O081", "I031 Switch", "I031"}, 1130*1de9a54aSTrevor Wu {"O082", "I032 Switch", "I032"}, 1131*1de9a54aSTrevor Wu {"O083", "I033 Switch", "I033"}, 1132*1de9a54aSTrevor Wu {"O084", "I034 Switch", "I034"}, 1133*1de9a54aSTrevor Wu {"O085", "I035 Switch", "I035"}, 1134*1de9a54aSTrevor Wu {"O086", "I036 Switch", "I036"}, 1135*1de9a54aSTrevor Wu {"O087", "I037 Switch", "I037"}, 1136*1de9a54aSTrevor Wu {"O088", "I038 Switch", "I038"}, 1137*1de9a54aSTrevor Wu {"O089", "I039 Switch", "I039"}, 1138*1de9a54aSTrevor Wu {"O090", "I040 Switch", "I040"}, 1139*1de9a54aSTrevor Wu {"O091", "I041 Switch", "I041"}, 1140*1de9a54aSTrevor Wu {"O092", "I042 Switch", "I042"}, 1141*1de9a54aSTrevor Wu {"O093", "I043 Switch", "I043"}, 1142*1de9a54aSTrevor Wu {"O094", "I044 Switch", "I044"}, 1143*1de9a54aSTrevor Wu {"O095", "I045 Switch", "I045"}, 1144*1de9a54aSTrevor Wu 1145*1de9a54aSTrevor Wu {"O072", "I046 Switch", "I046"}, 1146*1de9a54aSTrevor Wu {"O073", "I047 Switch", "I047"}, 1147*1de9a54aSTrevor Wu {"O074", "I048 Switch", "I048"}, 1148*1de9a54aSTrevor Wu {"O075", "I049 Switch", "I049"}, 1149*1de9a54aSTrevor Wu {"O076", "I050 Switch", "I050"}, 1150*1de9a54aSTrevor Wu {"O077", "I051 Switch", "I051"}, 1151*1de9a54aSTrevor Wu {"O078", "I052 Switch", "I052"}, 1152*1de9a54aSTrevor Wu {"O079", "I053 Switch", "I053"}, 1153*1de9a54aSTrevor Wu {"O080", "I054 Switch", "I054"}, 1154*1de9a54aSTrevor Wu {"O081", "I055 Switch", "I055"}, 1155*1de9a54aSTrevor Wu {"O082", "I056 Switch", "I056"}, 1156*1de9a54aSTrevor Wu {"O083", "I057 Switch", "I057"}, 1157*1de9a54aSTrevor Wu {"O084", "I058 Switch", "I058"}, 1158*1de9a54aSTrevor Wu {"O085", "I059 Switch", "I059"}, 1159*1de9a54aSTrevor Wu {"O086", "I060 Switch", "I060"}, 1160*1de9a54aSTrevor Wu {"O087", "I061 Switch", "I061"}, 1161*1de9a54aSTrevor Wu {"O088", "I062 Switch", "I062"}, 1162*1de9a54aSTrevor Wu {"O089", "I063 Switch", "I063"}, 1163*1de9a54aSTrevor Wu {"O090", "I064 Switch", "I064"}, 1164*1de9a54aSTrevor Wu {"O091", "I065 Switch", "I065"}, 1165*1de9a54aSTrevor Wu {"O092", "I066 Switch", "I066"}, 1166*1de9a54aSTrevor Wu {"O093", "I067 Switch", "I067"}, 1167*1de9a54aSTrevor Wu {"O094", "I068 Switch", "I068"}, 1168*1de9a54aSTrevor Wu {"O095", "I069 Switch", "I069"}, 1169*1de9a54aSTrevor Wu 1170*1de9a54aSTrevor Wu {"O072", "I070 Switch", "I070"}, 1171*1de9a54aSTrevor Wu {"O073", "I071 Switch", "I071"}, 1172*1de9a54aSTrevor Wu 1173*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH0", "DL10"}, 1174*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH1", "DL10"}, 1175*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH2", "DL10"}, 1176*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH3", "DL10"}, 1177*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH4", "DL10"}, 1178*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH5", "DL10"}, 1179*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH6", "DL10"}, 1180*1de9a54aSTrevor Wu {"HDMI_CH0_MUX", "CH7", "DL10"}, 1181*1de9a54aSTrevor Wu 1182*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH0", "DL10"}, 1183*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH1", "DL10"}, 1184*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH2", "DL10"}, 1185*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH3", "DL10"}, 1186*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH4", "DL10"}, 1187*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH5", "DL10"}, 1188*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH6", "DL10"}, 1189*1de9a54aSTrevor Wu {"HDMI_CH1_MUX", "CH7", "DL10"}, 1190*1de9a54aSTrevor Wu 1191*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH0", "DL10"}, 1192*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH1", "DL10"}, 1193*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH2", "DL10"}, 1194*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH3", "DL10"}, 1195*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH4", "DL10"}, 1196*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH5", "DL10"}, 1197*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH6", "DL10"}, 1198*1de9a54aSTrevor Wu {"HDMI_CH2_MUX", "CH7", "DL10"}, 1199*1de9a54aSTrevor Wu 1200*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH0", "DL10"}, 1201*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH1", "DL10"}, 1202*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH2", "DL10"}, 1203*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH3", "DL10"}, 1204*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH4", "DL10"}, 1205*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH5", "DL10"}, 1206*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH6", "DL10"}, 1207*1de9a54aSTrevor Wu {"HDMI_CH3_MUX", "CH7", "DL10"}, 1208*1de9a54aSTrevor Wu 1209*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH0", "DL10"}, 1210*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH1", "DL10"}, 1211*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH2", "DL10"}, 1212*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH3", "DL10"}, 1213*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH4", "DL10"}, 1214*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH5", "DL10"}, 1215*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH6", "DL10"}, 1216*1de9a54aSTrevor Wu {"HDMI_CH4_MUX", "CH7", "DL10"}, 1217*1de9a54aSTrevor Wu 1218*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH0", "DL10"}, 1219*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH1", "DL10"}, 1220*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH2", "DL10"}, 1221*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH3", "DL10"}, 1222*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH4", "DL10"}, 1223*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH5", "DL10"}, 1224*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH6", "DL10"}, 1225*1de9a54aSTrevor Wu {"HDMI_CH5_MUX", "CH7", "DL10"}, 1226*1de9a54aSTrevor Wu 1227*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH0", "DL10"}, 1228*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH1", "DL10"}, 1229*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH2", "DL10"}, 1230*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH3", "DL10"}, 1231*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH4", "DL10"}, 1232*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH5", "DL10"}, 1233*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH6", "DL10"}, 1234*1de9a54aSTrevor Wu {"HDMI_CH6_MUX", "CH7", "DL10"}, 1235*1de9a54aSTrevor Wu 1236*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH0", "DL10"}, 1237*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH1", "DL10"}, 1238*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH2", "DL10"}, 1239*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH3", "DL10"}, 1240*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH4", "DL10"}, 1241*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH5", "DL10"}, 1242*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH6", "DL10"}, 1243*1de9a54aSTrevor Wu {"HDMI_CH7_MUX", "CH7", "DL10"}, 1244*1de9a54aSTrevor Wu 1245*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1246*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1247*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1248*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1249*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1250*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1251*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1252*1de9a54aSTrevor Wu {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1253*1de9a54aSTrevor Wu 1254*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1255*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1256*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1257*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1258*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1259*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1260*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1261*1de9a54aSTrevor Wu {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1262*1de9a54aSTrevor Wu 1263*1de9a54aSTrevor Wu {"ETDM3 Playback", NULL, "HDMI_OUT_MUX"}, 1264*1de9a54aSTrevor Wu {"DPTX Playback", NULL, "DPTX_OUT_MUX"}, 1265*1de9a54aSTrevor Wu 1266*1de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "DPTX Playback"}, 1267*1de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM1 Playback"}, 1268*1de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM2 Playback"}, 1269*1de9a54aSTrevor Wu {"ETDM_OUTPUT", NULL, "ETDM3 Playback"}, 1270*1de9a54aSTrevor Wu {"ETDM1 Capture", NULL, "ETDM_INPUT"}, 1271*1de9a54aSTrevor Wu {"ETDM2 Capture", NULL, "ETDM_INPUT"}, 1272*1de9a54aSTrevor Wu }; 1273*1de9a54aSTrevor Wu 1274*1de9a54aSTrevor Wu static int mt8195_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1275*1de9a54aSTrevor Wu { 1276*1de9a54aSTrevor Wu int ret = 0; 1277*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1278*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1279*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1280*1de9a54aSTrevor Wu unsigned long flags; 1281*1de9a54aSTrevor Wu 1282*1de9a54aSTrevor Wu spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1283*1de9a54aSTrevor Wu etdm_data->en_ref_cnt++; 1284*1de9a54aSTrevor Wu if (etdm_data->en_ref_cnt == 1) { 1285*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1286*1de9a54aSTrevor Wu if (ret < 0) 1287*1de9a54aSTrevor Wu goto out; 1288*1de9a54aSTrevor Wu 1289*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, 1290*1de9a54aSTrevor Wu ETDM_CON0_EN, ETDM_CON0_EN); 1291*1de9a54aSTrevor Wu } 1292*1de9a54aSTrevor Wu out: 1293*1de9a54aSTrevor Wu spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1294*1de9a54aSTrevor Wu return ret; 1295*1de9a54aSTrevor Wu } 1296*1de9a54aSTrevor Wu 1297*1de9a54aSTrevor Wu static int mt8195_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1298*1de9a54aSTrevor Wu { 1299*1de9a54aSTrevor Wu int ret = 0; 1300*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1301*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1302*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1303*1de9a54aSTrevor Wu unsigned long flags; 1304*1de9a54aSTrevor Wu 1305*1de9a54aSTrevor Wu spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1306*1de9a54aSTrevor Wu if (etdm_data->en_ref_cnt > 0) { 1307*1de9a54aSTrevor Wu etdm_data->en_ref_cnt--; 1308*1de9a54aSTrevor Wu if (etdm_data->en_ref_cnt == 0) { 1309*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1310*1de9a54aSTrevor Wu if (ret < 0) 1311*1de9a54aSTrevor Wu goto out; 1312*1de9a54aSTrevor Wu 1313*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, 1314*1de9a54aSTrevor Wu ETDM_CON0_EN, 0); 1315*1de9a54aSTrevor Wu } 1316*1de9a54aSTrevor Wu } 1317*1de9a54aSTrevor Wu out: 1318*1de9a54aSTrevor Wu spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1319*1de9a54aSTrevor Wu return 0; 1320*1de9a54aSTrevor Wu } 1321*1de9a54aSTrevor Wu 1322*1de9a54aSTrevor Wu static int etdm_cowork_slv_sel(int id, int slave_mode) 1323*1de9a54aSTrevor Wu { 1324*1de9a54aSTrevor Wu if (slave_mode) { 1325*1de9a54aSTrevor Wu switch (id) { 1326*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1327*1de9a54aSTrevor Wu return COWORK_ETDM_IN1_S; 1328*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1329*1de9a54aSTrevor Wu return COWORK_ETDM_IN2_S; 1330*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1331*1de9a54aSTrevor Wu return COWORK_ETDM_OUT1_S; 1332*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1333*1de9a54aSTrevor Wu return COWORK_ETDM_OUT2_S; 1334*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1335*1de9a54aSTrevor Wu return COWORK_ETDM_OUT3_S; 1336*1de9a54aSTrevor Wu default: 1337*1de9a54aSTrevor Wu return -EINVAL; 1338*1de9a54aSTrevor Wu } 1339*1de9a54aSTrevor Wu } else { 1340*1de9a54aSTrevor Wu switch (id) { 1341*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1342*1de9a54aSTrevor Wu return COWORK_ETDM_IN1_M; 1343*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1344*1de9a54aSTrevor Wu return COWORK_ETDM_IN2_M; 1345*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1346*1de9a54aSTrevor Wu return COWORK_ETDM_OUT1_M; 1347*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1348*1de9a54aSTrevor Wu return COWORK_ETDM_OUT2_M; 1349*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1350*1de9a54aSTrevor Wu return COWORK_ETDM_OUT3_M; 1351*1de9a54aSTrevor Wu default: 1352*1de9a54aSTrevor Wu return -EINVAL; 1353*1de9a54aSTrevor Wu } 1354*1de9a54aSTrevor Wu } 1355*1de9a54aSTrevor Wu } 1356*1de9a54aSTrevor Wu 1357*1de9a54aSTrevor Wu static int mt8195_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1358*1de9a54aSTrevor Wu { 1359*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1360*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1361*1de9a54aSTrevor Wu unsigned int reg = 0; 1362*1de9a54aSTrevor Wu unsigned int mask; 1363*1de9a54aSTrevor Wu unsigned int val; 1364*1de9a54aSTrevor Wu int cowork_source_sel; 1365*1de9a54aSTrevor Wu 1366*1de9a54aSTrevor Wu if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1367*1de9a54aSTrevor Wu return 0; 1368*1de9a54aSTrevor Wu 1369*1de9a54aSTrevor Wu cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1370*1de9a54aSTrevor Wu etdm_data->slave_mode); 1371*1de9a54aSTrevor Wu if (cowork_source_sel < 0) 1372*1de9a54aSTrevor Wu return cowork_source_sel; 1373*1de9a54aSTrevor Wu 1374*1de9a54aSTrevor Wu switch (dai_id) { 1375*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1376*1de9a54aSTrevor Wu reg = ETDM_COWORK_CON1; 1377*1de9a54aSTrevor Wu mask = ETDM_IN1_SLAVE_SEL_MASK; 1378*1de9a54aSTrevor Wu val = ETDM_IN1_SLAVE_SEL(cowork_source_sel); 1379*1de9a54aSTrevor Wu break; 1380*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1381*1de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 1382*1de9a54aSTrevor Wu mask = ETDM_IN2_SLAVE_SEL_MASK; 1383*1de9a54aSTrevor Wu val = ETDM_IN2_SLAVE_SEL(cowork_source_sel); 1384*1de9a54aSTrevor Wu break; 1385*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1386*1de9a54aSTrevor Wu reg = ETDM_COWORK_CON0; 1387*1de9a54aSTrevor Wu mask = ETDM_OUT1_SLAVE_SEL_MASK; 1388*1de9a54aSTrevor Wu val = ETDM_OUT1_SLAVE_SEL(cowork_source_sel); 1389*1de9a54aSTrevor Wu break; 1390*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1391*1de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 1392*1de9a54aSTrevor Wu mask = ETDM_OUT2_SLAVE_SEL_MASK; 1393*1de9a54aSTrevor Wu val = ETDM_OUT2_SLAVE_SEL(cowork_source_sel); 1394*1de9a54aSTrevor Wu break; 1395*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1396*1de9a54aSTrevor Wu reg = ETDM_COWORK_CON2; 1397*1de9a54aSTrevor Wu mask = ETDM_OUT3_SLAVE_SEL_MASK; 1398*1de9a54aSTrevor Wu val = ETDM_OUT3_SLAVE_SEL(cowork_source_sel); 1399*1de9a54aSTrevor Wu break; 1400*1de9a54aSTrevor Wu default: 1401*1de9a54aSTrevor Wu return 0; 1402*1de9a54aSTrevor Wu } 1403*1de9a54aSTrevor Wu 1404*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 1405*1de9a54aSTrevor Wu 1406*1de9a54aSTrevor Wu return 0; 1407*1de9a54aSTrevor Wu } 1408*1de9a54aSTrevor Wu 1409*1de9a54aSTrevor Wu static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 1410*1de9a54aSTrevor Wu { 1411*1de9a54aSTrevor Wu int cg_id = -1; 1412*1de9a54aSTrevor Wu 1413*1de9a54aSTrevor Wu switch (dai_id) { 1414*1de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 1415*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_HDMI_OUT; 1416*1de9a54aSTrevor Wu break; 1417*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1418*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_TDM_IN; 1419*1de9a54aSTrevor Wu break; 1420*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1421*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_I2SIN; 1422*1de9a54aSTrevor Wu break; 1423*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1424*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_TDM_OUT; 1425*1de9a54aSTrevor Wu break; 1426*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1427*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_I2S_OUT; 1428*1de9a54aSTrevor Wu break; 1429*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1430*1de9a54aSTrevor Wu cg_id = MT8195_CLK_AUD_HDMI_OUT; 1431*1de9a54aSTrevor Wu break; 1432*1de9a54aSTrevor Wu default: 1433*1de9a54aSTrevor Wu break; 1434*1de9a54aSTrevor Wu } 1435*1de9a54aSTrevor Wu 1436*1de9a54aSTrevor Wu return cg_id; 1437*1de9a54aSTrevor Wu } 1438*1de9a54aSTrevor Wu 1439*1de9a54aSTrevor Wu static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 1440*1de9a54aSTrevor Wu { 1441*1de9a54aSTrevor Wu int clk_id = -1; 1442*1de9a54aSTrevor Wu 1443*1de9a54aSTrevor Wu switch (dai_id) { 1444*1de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 1445*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_DPTX_M_SEL; 1446*1de9a54aSTrevor Wu break; 1447*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1448*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SI1_M_SEL; 1449*1de9a54aSTrevor Wu break; 1450*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1451*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SI2_M_SEL; 1452*1de9a54aSTrevor Wu break; 1453*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1454*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SO1_M_SEL; 1455*1de9a54aSTrevor Wu break; 1456*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1457*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_I2SO2_M_SEL; 1458*1de9a54aSTrevor Wu break; 1459*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1460*1de9a54aSTrevor Wu default: 1461*1de9a54aSTrevor Wu break; 1462*1de9a54aSTrevor Wu } 1463*1de9a54aSTrevor Wu 1464*1de9a54aSTrevor Wu return clk_id; 1465*1de9a54aSTrevor Wu } 1466*1de9a54aSTrevor Wu 1467*1de9a54aSTrevor Wu static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 1468*1de9a54aSTrevor Wu { 1469*1de9a54aSTrevor Wu int clk_id = -1; 1470*1de9a54aSTrevor Wu 1471*1de9a54aSTrevor Wu switch (dai_id) { 1472*1de9a54aSTrevor Wu case MT8195_AFE_IO_DPTX: 1473*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV9; 1474*1de9a54aSTrevor Wu break; 1475*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1476*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV0; 1477*1de9a54aSTrevor Wu break; 1478*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1479*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV1; 1480*1de9a54aSTrevor Wu break; 1481*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_OUT: 1482*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV2; 1483*1de9a54aSTrevor Wu break; 1484*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_OUT: 1485*1de9a54aSTrevor Wu clk_id = MT8195_CLK_TOP_APLL12_DIV3; 1486*1de9a54aSTrevor Wu break; 1487*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM3_OUT: 1488*1de9a54aSTrevor Wu default: 1489*1de9a54aSTrevor Wu break; 1490*1de9a54aSTrevor Wu } 1491*1de9a54aSTrevor Wu 1492*1de9a54aSTrevor Wu return clk_id; 1493*1de9a54aSTrevor Wu } 1494*1de9a54aSTrevor Wu 1495*1de9a54aSTrevor Wu static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 1496*1de9a54aSTrevor Wu { 1497*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1498*1de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1499*1de9a54aSTrevor Wu 1500*1de9a54aSTrevor Wu if (clkdiv_id < 0) 1501*1de9a54aSTrevor Wu return -EINVAL; 1502*1de9a54aSTrevor Wu 1503*1de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 1504*1de9a54aSTrevor Wu 1505*1de9a54aSTrevor Wu return 0; 1506*1de9a54aSTrevor Wu } 1507*1de9a54aSTrevor Wu 1508*1de9a54aSTrevor Wu static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 1509*1de9a54aSTrevor Wu { 1510*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1511*1de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1512*1de9a54aSTrevor Wu 1513*1de9a54aSTrevor Wu if (clkdiv_id < 0) 1514*1de9a54aSTrevor Wu return -EINVAL; 1515*1de9a54aSTrevor Wu 1516*1de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 1517*1de9a54aSTrevor Wu 1518*1de9a54aSTrevor Wu return 0; 1519*1de9a54aSTrevor Wu } 1520*1de9a54aSTrevor Wu 1521*1de9a54aSTrevor Wu /* dai ops */ 1522*1de9a54aSTrevor Wu static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1523*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 1524*1de9a54aSTrevor Wu { 1525*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1526*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1527*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 1528*1de9a54aSTrevor Wu int cg_id; 1529*1de9a54aSTrevor Wu int mst_dai_id; 1530*1de9a54aSTrevor Wu int slv_dai_id; 1531*1de9a54aSTrevor Wu int i; 1532*1de9a54aSTrevor Wu 1533*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 1534*1de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 1535*1de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1536*1de9a54aSTrevor Wu 1537*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1538*1de9a54aSTrevor Wu if (cg_id >= 0) 1539*1de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1540*1de9a54aSTrevor Wu 1541*1de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1542*1de9a54aSTrevor Wu 1543*1de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1544*1de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1545*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1546*1de9a54aSTrevor Wu if (cg_id >= 0) 1547*1de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, 1548*1de9a54aSTrevor Wu afe_priv->clk[cg_id]); 1549*1de9a54aSTrevor Wu } 1550*1de9a54aSTrevor Wu } else { 1551*1de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 1552*1de9a54aSTrevor Wu 1553*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1554*1de9a54aSTrevor Wu if (cg_id >= 0) 1555*1de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1556*1de9a54aSTrevor Wu } 1557*1de9a54aSTrevor Wu 1558*1de9a54aSTrevor Wu return 0; 1559*1de9a54aSTrevor Wu } 1560*1de9a54aSTrevor Wu 1561*1de9a54aSTrevor Wu static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1562*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 1563*1de9a54aSTrevor Wu { 1564*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1565*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1566*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 1567*1de9a54aSTrevor Wu int cg_id; 1568*1de9a54aSTrevor Wu int mst_dai_id; 1569*1de9a54aSTrevor Wu int slv_dai_id; 1570*1de9a54aSTrevor Wu int i; 1571*1de9a54aSTrevor Wu 1572*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 1573*1de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 1574*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1575*1de9a54aSTrevor Wu if (cg_id >= 0) 1576*1de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1577*1de9a54aSTrevor Wu 1578*1de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1579*1de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1580*1de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1581*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1582*1de9a54aSTrevor Wu if (cg_id >= 0) 1583*1de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, 1584*1de9a54aSTrevor Wu afe_priv->clk[cg_id]); 1585*1de9a54aSTrevor Wu } 1586*1de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1587*1de9a54aSTrevor Wu } else { 1588*1de9a54aSTrevor Wu cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1589*1de9a54aSTrevor Wu if (cg_id >= 0) 1590*1de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1591*1de9a54aSTrevor Wu 1592*1de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, dai->id); 1593*1de9a54aSTrevor Wu } 1594*1de9a54aSTrevor Wu } 1595*1de9a54aSTrevor Wu 1596*1de9a54aSTrevor Wu static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1597*1de9a54aSTrevor Wu int dai_id, unsigned int rate) 1598*1de9a54aSTrevor Wu { 1599*1de9a54aSTrevor Wu unsigned int mode = 0; 1600*1de9a54aSTrevor Wu unsigned int reg = 0; 1601*1de9a54aSTrevor Wu unsigned int val = 0; 1602*1de9a54aSTrevor Wu unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1603*1de9a54aSTrevor Wu 1604*1de9a54aSTrevor Wu if (rate != 0) 1605*1de9a54aSTrevor Wu mode = mt8195_afe_fs_timing(rate); 1606*1de9a54aSTrevor Wu 1607*1de9a54aSTrevor Wu switch (dai_id) { 1608*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM1_IN: 1609*1de9a54aSTrevor Wu reg = ETDM_IN1_AFIFO_CON; 1610*1de9a54aSTrevor Wu if (rate == 0) 1611*1de9a54aSTrevor Wu mode = MT8195_ETDM_IN1_1X_EN; 1612*1de9a54aSTrevor Wu break; 1613*1de9a54aSTrevor Wu case MT8195_AFE_IO_ETDM2_IN: 1614*1de9a54aSTrevor Wu reg = ETDM_IN2_AFIFO_CON; 1615*1de9a54aSTrevor Wu if (rate == 0) 1616*1de9a54aSTrevor Wu mode = MT8195_ETDM_IN2_1X_EN; 1617*1de9a54aSTrevor Wu break; 1618*1de9a54aSTrevor Wu default: 1619*1de9a54aSTrevor Wu return -EINVAL; 1620*1de9a54aSTrevor Wu } 1621*1de9a54aSTrevor Wu 1622*1de9a54aSTrevor Wu val = (mode | ETDM_IN_USE_AFIFO); 1623*1de9a54aSTrevor Wu 1624*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 1625*1de9a54aSTrevor Wu return 0; 1626*1de9a54aSTrevor Wu } 1627*1de9a54aSTrevor Wu 1628*1de9a54aSTrevor Wu static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1629*1de9a54aSTrevor Wu unsigned int rate, 1630*1de9a54aSTrevor Wu unsigned int channels, 1631*1de9a54aSTrevor Wu int dai_id) 1632*1de9a54aSTrevor Wu { 1633*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1634*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1635*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1636*1de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 1637*1de9a54aSTrevor Wu unsigned int data_mode = etdm_data->data_mode; 1638*1de9a54aSTrevor Wu unsigned int lrck_width = etdm_data->lrck_width; 1639*1de9a54aSTrevor Wu unsigned int val = 0; 1640*1de9a54aSTrevor Wu unsigned int mask = 0; 1641*1de9a54aSTrevor Wu int i; 1642*1de9a54aSTrevor Wu int ret; 1643*1de9a54aSTrevor Wu 1644*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1645*1de9a54aSTrevor Wu __func__, rate, channels, dai_id); 1646*1de9a54aSTrevor Wu 1647*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1648*1de9a54aSTrevor Wu if (ret < 0) 1649*1de9a54aSTrevor Wu return ret; 1650*1de9a54aSTrevor Wu 1651*1de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1652*1de9a54aSTrevor Wu slave_mode = true; 1653*1de9a54aSTrevor Wu 1654*1de9a54aSTrevor Wu /* afifo */ 1655*1de9a54aSTrevor Wu if (slave_mode) 1656*1de9a54aSTrevor Wu mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1657*1de9a54aSTrevor Wu else 1658*1de9a54aSTrevor Wu mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1659*1de9a54aSTrevor Wu 1660*1de9a54aSTrevor Wu /* con1 */ 1661*1de9a54aSTrevor Wu if (lrck_width > 0) { 1662*1de9a54aSTrevor Wu mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1663*1de9a54aSTrevor Wu ETDM_IN_CON1_LRCK_WIDTH_MASK); 1664*1de9a54aSTrevor Wu val |= ETDM_IN_CON1_LRCK_WIDTH(lrck_width); 1665*1de9a54aSTrevor Wu } 1666*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1667*1de9a54aSTrevor Wu 1668*1de9a54aSTrevor Wu mask = 0; 1669*1de9a54aSTrevor Wu val = 0; 1670*1de9a54aSTrevor Wu 1671*1de9a54aSTrevor Wu /* con2 */ 1672*1de9a54aSTrevor Wu if (!slave_mode) { 1673*1de9a54aSTrevor Wu mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1674*1de9a54aSTrevor Wu if (rate == 352800 || rate == 384000) 1675*1de9a54aSTrevor Wu val |= ETDM_IN_CON2_UPDATE_GAP(4); 1676*1de9a54aSTrevor Wu else 1677*1de9a54aSTrevor Wu val |= ETDM_IN_CON2_UPDATE_GAP(3); 1678*1de9a54aSTrevor Wu } 1679*1de9a54aSTrevor Wu mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1680*1de9a54aSTrevor Wu ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1681*1de9a54aSTrevor Wu if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1682*1de9a54aSTrevor Wu val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1683*1de9a54aSTrevor Wu ETDM_IN_CON2_MULTI_IP_TOTAL_CH(channels); 1684*1de9a54aSTrevor Wu } 1685*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1686*1de9a54aSTrevor Wu 1687*1de9a54aSTrevor Wu mask = 0; 1688*1de9a54aSTrevor Wu val = 0; 1689*1de9a54aSTrevor Wu 1690*1de9a54aSTrevor Wu /* con3 */ 1691*1de9a54aSTrevor Wu mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1692*1de9a54aSTrevor Wu for (i = 0; i < channels; i += 2) { 1693*1de9a54aSTrevor Wu if (etdm_data->in_disable_ch[i] && 1694*1de9a54aSTrevor Wu etdm_data->in_disable_ch[i + 1]) 1695*1de9a54aSTrevor Wu val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1696*1de9a54aSTrevor Wu } 1697*1de9a54aSTrevor Wu if (!slave_mode) { 1698*1de9a54aSTrevor Wu mask |= ETDM_IN_CON3_FS_MASK; 1699*1de9a54aSTrevor Wu val |= ETDM_IN_CON3_FS(get_etdm_fs_timing(rate)); 1700*1de9a54aSTrevor Wu } 1701*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1702*1de9a54aSTrevor Wu 1703*1de9a54aSTrevor Wu mask = 0; 1704*1de9a54aSTrevor Wu val = 0; 1705*1de9a54aSTrevor Wu 1706*1de9a54aSTrevor Wu /* con4 */ 1707*1de9a54aSTrevor Wu mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1708*1de9a54aSTrevor Wu ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1709*1de9a54aSTrevor Wu if (slave_mode) { 1710*1de9a54aSTrevor Wu if (etdm_data->lrck_inv) 1711*1de9a54aSTrevor Wu val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1712*1de9a54aSTrevor Wu if (etdm_data->bck_inv) 1713*1de9a54aSTrevor Wu val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1714*1de9a54aSTrevor Wu } else { 1715*1de9a54aSTrevor Wu if (etdm_data->lrck_inv) 1716*1de9a54aSTrevor Wu val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1717*1de9a54aSTrevor Wu if (etdm_data->bck_inv) 1718*1de9a54aSTrevor Wu val |= ETDM_IN_CON4_MASTER_BCK_INV; 1719*1de9a54aSTrevor Wu } 1720*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1721*1de9a54aSTrevor Wu 1722*1de9a54aSTrevor Wu mask = 0; 1723*1de9a54aSTrevor Wu val = 0; 1724*1de9a54aSTrevor Wu 1725*1de9a54aSTrevor Wu /* con5 */ 1726*1de9a54aSTrevor Wu mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1727*1de9a54aSTrevor Wu mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1728*1de9a54aSTrevor Wu for (i = 0; i < channels; i += 2) { 1729*1de9a54aSTrevor Wu if (etdm_data->in_disable_ch[i] && 1730*1de9a54aSTrevor Wu !etdm_data->in_disable_ch[i + 1]) { 1731*1de9a54aSTrevor Wu if (i == (channels - 2)) 1732*1de9a54aSTrevor Wu val |= ETDM_IN_CON5_LR_SWAP(15); 1733*1de9a54aSTrevor Wu else 1734*1de9a54aSTrevor Wu val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1735*1de9a54aSTrevor Wu val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1736*1de9a54aSTrevor Wu } else if (!etdm_data->in_disable_ch[i] && 1737*1de9a54aSTrevor Wu etdm_data->in_disable_ch[i + 1]) { 1738*1de9a54aSTrevor Wu val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1739*1de9a54aSTrevor Wu } 1740*1de9a54aSTrevor Wu } 1741*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1742*1de9a54aSTrevor Wu return 0; 1743*1de9a54aSTrevor Wu } 1744*1de9a54aSTrevor Wu 1745*1de9a54aSTrevor Wu static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1746*1de9a54aSTrevor Wu unsigned int rate, 1747*1de9a54aSTrevor Wu unsigned int channels, 1748*1de9a54aSTrevor Wu int dai_id) 1749*1de9a54aSTrevor Wu { 1750*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1751*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1752*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1753*1de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 1754*1de9a54aSTrevor Wu unsigned int lrck_width = etdm_data->lrck_width; 1755*1de9a54aSTrevor Wu unsigned int val = 0; 1756*1de9a54aSTrevor Wu unsigned int mask = 0; 1757*1de9a54aSTrevor Wu int ret; 1758*1de9a54aSTrevor Wu int fs = 0; 1759*1de9a54aSTrevor Wu 1760*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1761*1de9a54aSTrevor Wu __func__, rate, channels, dai_id); 1762*1de9a54aSTrevor Wu 1763*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1764*1de9a54aSTrevor Wu if (ret < 0) 1765*1de9a54aSTrevor Wu return ret; 1766*1de9a54aSTrevor Wu 1767*1de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1768*1de9a54aSTrevor Wu slave_mode = true; 1769*1de9a54aSTrevor Wu 1770*1de9a54aSTrevor Wu /* con0 */ 1771*1de9a54aSTrevor Wu mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1772*1de9a54aSTrevor Wu val = ETDM_OUT_CON0_RELATCH_DOMAIN(ETDM_RELATCH_TIMING_A1A2SYS); 1773*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1774*1de9a54aSTrevor Wu 1775*1de9a54aSTrevor Wu mask = 0; 1776*1de9a54aSTrevor Wu val = 0; 1777*1de9a54aSTrevor Wu 1778*1de9a54aSTrevor Wu /* con1 */ 1779*1de9a54aSTrevor Wu if (lrck_width > 0) { 1780*1de9a54aSTrevor Wu mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1781*1de9a54aSTrevor Wu ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1782*1de9a54aSTrevor Wu val |= ETDM_OUT_CON1_LRCK_WIDTH(lrck_width); 1783*1de9a54aSTrevor Wu } 1784*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1785*1de9a54aSTrevor Wu 1786*1de9a54aSTrevor Wu mask = 0; 1787*1de9a54aSTrevor Wu val = 0; 1788*1de9a54aSTrevor Wu 1789*1de9a54aSTrevor Wu if (slave_mode) { 1790*1de9a54aSTrevor Wu /* con2 */ 1791*1de9a54aSTrevor Wu mask = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1792*1de9a54aSTrevor Wu ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1793*1de9a54aSTrevor Wu val = (ETDM_OUT_CON2_LRCK_DELAY_BCK_INV | 1794*1de9a54aSTrevor Wu ETDM_OUT_CON2_LRCK_DELAY_0P5T_EN); 1795*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con2, 1796*1de9a54aSTrevor Wu mask, val); 1797*1de9a54aSTrevor Wu mask = 0; 1798*1de9a54aSTrevor Wu val = 0; 1799*1de9a54aSTrevor Wu } else { 1800*1de9a54aSTrevor Wu /* con4 */ 1801*1de9a54aSTrevor Wu mask |= ETDM_OUT_CON4_FS_MASK; 1802*1de9a54aSTrevor Wu val |= ETDM_OUT_CON4_FS(get_etdm_fs_timing(rate)); 1803*1de9a54aSTrevor Wu } 1804*1de9a54aSTrevor Wu 1805*1de9a54aSTrevor Wu mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1806*1de9a54aSTrevor Wu if (dai_id == MT8195_AFE_IO_ETDM1_OUT) 1807*1de9a54aSTrevor Wu fs = MT8195_ETDM_OUT1_1X_EN; 1808*1de9a54aSTrevor Wu else if (dai_id == MT8195_AFE_IO_ETDM2_OUT) 1809*1de9a54aSTrevor Wu fs = MT8195_ETDM_OUT2_1X_EN; 1810*1de9a54aSTrevor Wu 1811*1de9a54aSTrevor Wu val |= ETDM_OUT_CON4_RELATCH_EN(fs); 1812*1de9a54aSTrevor Wu 1813*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1814*1de9a54aSTrevor Wu 1815*1de9a54aSTrevor Wu mask = 0; 1816*1de9a54aSTrevor Wu val = 0; 1817*1de9a54aSTrevor Wu 1818*1de9a54aSTrevor Wu /* con5 */ 1819*1de9a54aSTrevor Wu mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1820*1de9a54aSTrevor Wu ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1821*1de9a54aSTrevor Wu if (slave_mode) { 1822*1de9a54aSTrevor Wu if (etdm_data->lrck_inv) 1823*1de9a54aSTrevor Wu val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1824*1de9a54aSTrevor Wu if (etdm_data->bck_inv) 1825*1de9a54aSTrevor Wu val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1826*1de9a54aSTrevor Wu } else { 1827*1de9a54aSTrevor Wu if (etdm_data->lrck_inv) 1828*1de9a54aSTrevor Wu val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1829*1de9a54aSTrevor Wu if (etdm_data->bck_inv) 1830*1de9a54aSTrevor Wu val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1831*1de9a54aSTrevor Wu } 1832*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1833*1de9a54aSTrevor Wu 1834*1de9a54aSTrevor Wu return 0; 1835*1de9a54aSTrevor Wu } 1836*1de9a54aSTrevor Wu 1837*1de9a54aSTrevor Wu static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1838*1de9a54aSTrevor Wu { 1839*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1840*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1841*1de9a54aSTrevor Wu int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1842*1de9a54aSTrevor Wu int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1843*1de9a54aSTrevor Wu int apll; 1844*1de9a54aSTrevor Wu int apll_clk_id; 1845*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1846*1de9a54aSTrevor Wu unsigned int val = 0; 1847*1de9a54aSTrevor Wu unsigned int mask = 0; 1848*1de9a54aSTrevor Wu int ret = 0; 1849*1de9a54aSTrevor Wu 1850*1de9a54aSTrevor Wu if (clk_id < 0 || clkdiv_id < 0) 1851*1de9a54aSTrevor Wu return 0; 1852*1de9a54aSTrevor Wu 1853*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1854*1de9a54aSTrevor Wu if (ret < 0) 1855*1de9a54aSTrevor Wu return ret; 1856*1de9a54aSTrevor Wu 1857*1de9a54aSTrevor Wu mask |= ETDM_CON1_MCLK_OUTPUT; 1858*1de9a54aSTrevor Wu if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1859*1de9a54aSTrevor Wu val |= ETDM_CON1_MCLK_OUTPUT; 1860*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1861*1de9a54aSTrevor Wu 1862*1de9a54aSTrevor Wu if (etdm_data->mclk_freq) { 1863*1de9a54aSTrevor Wu apll = etdm_data->mclk_apll; 1864*1de9a54aSTrevor Wu apll_clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 1865*1de9a54aSTrevor Wu if (apll_clk_id < 0) 1866*1de9a54aSTrevor Wu return apll_clk_id; 1867*1de9a54aSTrevor Wu 1868*1de9a54aSTrevor Wu /* select apll */ 1869*1de9a54aSTrevor Wu ret = mt8195_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1870*1de9a54aSTrevor Wu afe_priv->clk[apll_clk_id]); 1871*1de9a54aSTrevor Wu if (ret) 1872*1de9a54aSTrevor Wu return ret; 1873*1de9a54aSTrevor Wu 1874*1de9a54aSTrevor Wu /* set rate */ 1875*1de9a54aSTrevor Wu ret = mt8195_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1876*1de9a54aSTrevor Wu etdm_data->mclk_freq); 1877*1de9a54aSTrevor Wu } else { 1878*1de9a54aSTrevor Wu if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1879*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1880*1de9a54aSTrevor Wu } 1881*1de9a54aSTrevor Wu return ret; 1882*1de9a54aSTrevor Wu } 1883*1de9a54aSTrevor Wu 1884*1de9a54aSTrevor Wu static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1885*1de9a54aSTrevor Wu unsigned int rate, 1886*1de9a54aSTrevor Wu unsigned int channels, 1887*1de9a54aSTrevor Wu unsigned int bit_width, 1888*1de9a54aSTrevor Wu int dai_id) 1889*1de9a54aSTrevor Wu { 1890*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1891*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 1892*1de9a54aSTrevor Wu struct etdm_con_reg etdm_reg; 1893*1de9a54aSTrevor Wu bool slave_mode = etdm_data->slave_mode; 1894*1de9a54aSTrevor Wu unsigned int etdm_channels; 1895*1de9a54aSTrevor Wu unsigned int val = 0; 1896*1de9a54aSTrevor Wu unsigned int mask = 0; 1897*1de9a54aSTrevor Wu unsigned int bck; 1898*1de9a54aSTrevor Wu unsigned int wlen = get_etdm_wlen(bit_width); 1899*1de9a54aSTrevor Wu int ret; 1900*1de9a54aSTrevor Wu 1901*1de9a54aSTrevor Wu ret = get_etdm_reg(dai_id, &etdm_reg); 1902*1de9a54aSTrevor Wu if (ret < 0) 1903*1de9a54aSTrevor Wu return ret; 1904*1de9a54aSTrevor Wu 1905*1de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) 1906*1de9a54aSTrevor Wu slave_mode = true; 1907*1de9a54aSTrevor Wu 1908*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1909*1de9a54aSTrevor Wu __func__, etdm_data->format, etdm_data->data_mode, 1910*1de9a54aSTrevor Wu etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1911*1de9a54aSTrevor Wu etdm_data->clock_mode, etdm_data->slave_mode); 1912*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s rate %u channels %u bitwiedh %u, id %d\n", 1913*1de9a54aSTrevor Wu __func__, rate, channels, bit_width, dai_id); 1914*1de9a54aSTrevor Wu 1915*1de9a54aSTrevor Wu etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1916*1de9a54aSTrevor Wu get_etdm_ch_fixup(channels) : 2; 1917*1de9a54aSTrevor Wu 1918*1de9a54aSTrevor Wu bck = rate * etdm_channels * wlen; 1919*1de9a54aSTrevor Wu if (bck > MT8195_ETDM_NORMAL_MAX_BCK_RATE) { 1920*1de9a54aSTrevor Wu dev_info(afe->dev, "%s bck rate %u not support\n", 1921*1de9a54aSTrevor Wu __func__, bck); 1922*1de9a54aSTrevor Wu return -EINVAL; 1923*1de9a54aSTrevor Wu } 1924*1de9a54aSTrevor Wu 1925*1de9a54aSTrevor Wu /* con0 */ 1926*1de9a54aSTrevor Wu mask |= ETDM_CON0_BIT_LEN_MASK; 1927*1de9a54aSTrevor Wu val |= ETDM_CON0_BIT_LEN(bit_width); 1928*1de9a54aSTrevor Wu mask |= ETDM_CON0_WORD_LEN_MASK; 1929*1de9a54aSTrevor Wu val |= ETDM_CON0_WORD_LEN(wlen); 1930*1de9a54aSTrevor Wu mask |= ETDM_CON0_FORMAT_MASK; 1931*1de9a54aSTrevor Wu val |= ETDM_CON0_FORMAT(etdm_data->format); 1932*1de9a54aSTrevor Wu mask |= ETDM_CON0_CH_NUM_MASK; 1933*1de9a54aSTrevor Wu val |= ETDM_CON0_CH_NUM(etdm_channels); 1934*1de9a54aSTrevor Wu 1935*1de9a54aSTrevor Wu mask |= ETDM_CON0_SLAVE_MODE; 1936*1de9a54aSTrevor Wu if (slave_mode) { 1937*1de9a54aSTrevor Wu if (dai_id == MT8195_AFE_IO_ETDM1_OUT && 1938*1de9a54aSTrevor Wu etdm_data->cowork_source_id == COWORK_ETDM_NONE) { 1939*1de9a54aSTrevor Wu dev_info(afe->dev, "%s id %d only support master mode\n", 1940*1de9a54aSTrevor Wu __func__, dai_id); 1941*1de9a54aSTrevor Wu return -EINVAL; 1942*1de9a54aSTrevor Wu } 1943*1de9a54aSTrevor Wu val |= ETDM_CON0_SLAVE_MODE; 1944*1de9a54aSTrevor Wu } 1945*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1946*1de9a54aSTrevor Wu 1947*1de9a54aSTrevor Wu if (get_etdm_dir(dai_id) == ETDM_IN) 1948*1de9a54aSTrevor Wu mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 1949*1de9a54aSTrevor Wu else 1950*1de9a54aSTrevor Wu mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 1951*1de9a54aSTrevor Wu 1952*1de9a54aSTrevor Wu return 0; 1953*1de9a54aSTrevor Wu } 1954*1de9a54aSTrevor Wu 1955*1de9a54aSTrevor Wu static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 1956*1de9a54aSTrevor Wu struct snd_pcm_hw_params *params, 1957*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 1958*1de9a54aSTrevor Wu { 1959*1de9a54aSTrevor Wu int ret = 0; 1960*1de9a54aSTrevor Wu unsigned int rate = params_rate(params); 1961*1de9a54aSTrevor Wu unsigned int bit_width = params_width(params); 1962*1de9a54aSTrevor Wu unsigned int channels = params_channels(params); 1963*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1964*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 1965*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 1966*1de9a54aSTrevor Wu int mst_dai_id; 1967*1de9a54aSTrevor Wu int slv_dai_id; 1968*1de9a54aSTrevor Wu int i; 1969*1de9a54aSTrevor Wu 1970*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 1971*1de9a54aSTrevor Wu __func__, snd_pcm_stream_str(substream), 1972*1de9a54aSTrevor Wu params_period_size(params), params_periods(params)); 1973*1de9a54aSTrevor Wu 1974*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 1975*1de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 1976*1de9a54aSTrevor Wu 1977*1de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 1978*1de9a54aSTrevor Wu if (ret) 1979*1de9a54aSTrevor Wu return ret; 1980*1de9a54aSTrevor Wu 1981*1de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 1982*1de9a54aSTrevor Wu bit_width, mst_dai_id); 1983*1de9a54aSTrevor Wu if (ret) 1984*1de9a54aSTrevor Wu return ret; 1985*1de9a54aSTrevor Wu 1986*1de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1987*1de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1988*1de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1989*1de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 1990*1de9a54aSTrevor Wu bit_width, slv_dai_id); 1991*1de9a54aSTrevor Wu if (ret) 1992*1de9a54aSTrevor Wu return ret; 1993*1de9a54aSTrevor Wu 1994*1de9a54aSTrevor Wu ret = mt8195_etdm_sync_mode_configure(afe, slv_dai_id); 1995*1de9a54aSTrevor Wu if (ret) 1996*1de9a54aSTrevor Wu return ret; 1997*1de9a54aSTrevor Wu } 1998*1de9a54aSTrevor Wu } else { 1999*1de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2000*1de9a54aSTrevor Wu if (ret) 2001*1de9a54aSTrevor Wu return ret; 2002*1de9a54aSTrevor Wu 2003*1de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, 2004*1de9a54aSTrevor Wu bit_width, dai->id); 2005*1de9a54aSTrevor Wu } 2006*1de9a54aSTrevor Wu 2007*1de9a54aSTrevor Wu return ret; 2008*1de9a54aSTrevor Wu } 2009*1de9a54aSTrevor Wu 2010*1de9a54aSTrevor Wu static int mtk_dai_etdm_trigger(struct snd_pcm_substream *substream, int cmd, 2011*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 2012*1de9a54aSTrevor Wu { 2013*1de9a54aSTrevor Wu int ret = 0; 2014*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2015*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2016*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_etdm_data; 2017*1de9a54aSTrevor Wu int mst_dai_id; 2018*1de9a54aSTrevor Wu int slv_dai_id; 2019*1de9a54aSTrevor Wu int i; 2020*1de9a54aSTrevor Wu 2021*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2022*1de9a54aSTrevor Wu switch (cmd) { 2023*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_START: 2024*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_RESUME: 2025*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 2026*1de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 2027*1de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2028*1de9a54aSTrevor Wu 2029*1de9a54aSTrevor Wu //open master first 2030*1de9a54aSTrevor Wu ret |= mt8195_afe_enable_etdm(afe, mst_dai_id); 2031*1de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2032*1de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2033*1de9a54aSTrevor Wu ret |= mt8195_afe_enable_etdm(afe, slv_dai_id); 2034*1de9a54aSTrevor Wu } 2035*1de9a54aSTrevor Wu } else { 2036*1de9a54aSTrevor Wu ret = mt8195_afe_enable_etdm(afe, dai->id); 2037*1de9a54aSTrevor Wu } 2038*1de9a54aSTrevor Wu break; 2039*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_STOP: 2040*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_SUSPEND: 2041*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) { 2042*1de9a54aSTrevor Wu mst_dai_id = get_etdm_cowork_master_id(dai); 2043*1de9a54aSTrevor Wu mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 2044*1de9a54aSTrevor Wu 2045*1de9a54aSTrevor Wu for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 2046*1de9a54aSTrevor Wu slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 2047*1de9a54aSTrevor Wu ret |= mt8195_afe_disable_etdm(afe, slv_dai_id); 2048*1de9a54aSTrevor Wu } 2049*1de9a54aSTrevor Wu // close master at last 2050*1de9a54aSTrevor Wu ret |= mt8195_afe_disable_etdm(afe, mst_dai_id); 2051*1de9a54aSTrevor Wu } else { 2052*1de9a54aSTrevor Wu ret = mt8195_afe_disable_etdm(afe, dai->id); 2053*1de9a54aSTrevor Wu } 2054*1de9a54aSTrevor Wu break; 2055*1de9a54aSTrevor Wu default: 2056*1de9a54aSTrevor Wu break; 2057*1de9a54aSTrevor Wu } 2058*1de9a54aSTrevor Wu return ret; 2059*1de9a54aSTrevor Wu } 2060*1de9a54aSTrevor Wu 2061*1de9a54aSTrevor Wu static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2062*1de9a54aSTrevor Wu { 2063*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2064*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai_id]; 2065*1de9a54aSTrevor Wu int apll; 2066*1de9a54aSTrevor Wu int apll_rate; 2067*1de9a54aSTrevor Wu 2068*1de9a54aSTrevor Wu if (freq == 0) { 2069*1de9a54aSTrevor Wu etdm_data->mclk_freq = freq; 2070*1de9a54aSTrevor Wu return 0; 2071*1de9a54aSTrevor Wu } 2072*1de9a54aSTrevor Wu 2073*1de9a54aSTrevor Wu apll = mt8195_afe_get_default_mclk_source_by_rate(freq); 2074*1de9a54aSTrevor Wu apll_rate = mt8195_afe_get_mclk_source_rate(afe, apll); 2075*1de9a54aSTrevor Wu 2076*1de9a54aSTrevor Wu if (freq > apll_rate) { 2077*1de9a54aSTrevor Wu dev_info(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2078*1de9a54aSTrevor Wu return -EINVAL; 2079*1de9a54aSTrevor Wu } 2080*1de9a54aSTrevor Wu 2081*1de9a54aSTrevor Wu if (apll_rate % freq != 0) { 2082*1de9a54aSTrevor Wu dev_info(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2083*1de9a54aSTrevor Wu return -EINVAL; 2084*1de9a54aSTrevor Wu } 2085*1de9a54aSTrevor Wu 2086*1de9a54aSTrevor Wu etdm_data->mclk_apll = apll; 2087*1de9a54aSTrevor Wu etdm_data->mclk_freq = freq; 2088*1de9a54aSTrevor Wu 2089*1de9a54aSTrevor Wu return 0; 2090*1de9a54aSTrevor Wu } 2091*1de9a54aSTrevor Wu 2092*1de9a54aSTrevor Wu static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2093*1de9a54aSTrevor Wu int clk_id, unsigned int freq, int dir) 2094*1de9a54aSTrevor Wu { 2095*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2096*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2097*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2098*1de9a54aSTrevor Wu int dai_id; 2099*1de9a54aSTrevor Wu 2100*1de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2101*1de9a54aSTrevor Wu __func__, dai->id, freq, dir); 2102*1de9a54aSTrevor Wu if (is_cowork_mode(dai)) 2103*1de9a54aSTrevor Wu dai_id = get_etdm_cowork_master_id(dai); 2104*1de9a54aSTrevor Wu else 2105*1de9a54aSTrevor Wu dai_id = dai->id; 2106*1de9a54aSTrevor Wu 2107*1de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[dai_id]; 2108*1de9a54aSTrevor Wu etdm_data->mclk_dir = dir; 2109*1de9a54aSTrevor Wu return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2110*1de9a54aSTrevor Wu } 2111*1de9a54aSTrevor Wu 2112*1de9a54aSTrevor Wu static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2113*1de9a54aSTrevor Wu unsigned int tx_mask, unsigned int rx_mask, 2114*1de9a54aSTrevor Wu int slots, int slot_width) 2115*1de9a54aSTrevor Wu { 2116*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2117*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2118*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2119*1de9a54aSTrevor Wu 2120*1de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2121*1de9a54aSTrevor Wu __func__, dai->id, slot_width); 2122*1de9a54aSTrevor Wu 2123*1de9a54aSTrevor Wu etdm_data->slots = slots; 2124*1de9a54aSTrevor Wu etdm_data->lrck_width = slot_width; 2125*1de9a54aSTrevor Wu return 0; 2126*1de9a54aSTrevor Wu } 2127*1de9a54aSTrevor Wu 2128*1de9a54aSTrevor Wu static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2129*1de9a54aSTrevor Wu { 2130*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2131*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2132*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2133*1de9a54aSTrevor Wu 2134*1de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2135*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_I2S: 2136*1de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2137*1de9a54aSTrevor Wu break; 2138*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_LEFT_J: 2139*1de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2140*1de9a54aSTrevor Wu break; 2141*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_RIGHT_J: 2142*1de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2143*1de9a54aSTrevor Wu break; 2144*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_DSP_A: 2145*1de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2146*1de9a54aSTrevor Wu break; 2147*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_DSP_B: 2148*1de9a54aSTrevor Wu etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2149*1de9a54aSTrevor Wu break; 2150*1de9a54aSTrevor Wu default: 2151*1de9a54aSTrevor Wu return -EINVAL; 2152*1de9a54aSTrevor Wu } 2153*1de9a54aSTrevor Wu 2154*1de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2155*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_NB_NF: 2156*1de9a54aSTrevor Wu etdm_data->bck_inv = false; 2157*1de9a54aSTrevor Wu etdm_data->lrck_inv = false; 2158*1de9a54aSTrevor Wu break; 2159*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_NB_IF: 2160*1de9a54aSTrevor Wu etdm_data->bck_inv = false; 2161*1de9a54aSTrevor Wu etdm_data->lrck_inv = true; 2162*1de9a54aSTrevor Wu break; 2163*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_IB_NF: 2164*1de9a54aSTrevor Wu etdm_data->bck_inv = true; 2165*1de9a54aSTrevor Wu etdm_data->lrck_inv = false; 2166*1de9a54aSTrevor Wu break; 2167*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_IB_IF: 2168*1de9a54aSTrevor Wu etdm_data->bck_inv = true; 2169*1de9a54aSTrevor Wu etdm_data->lrck_inv = true; 2170*1de9a54aSTrevor Wu break; 2171*1de9a54aSTrevor Wu default: 2172*1de9a54aSTrevor Wu return -EINVAL; 2173*1de9a54aSTrevor Wu } 2174*1de9a54aSTrevor Wu 2175*1de9a54aSTrevor Wu switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 2176*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_CBM_CFM: 2177*1de9a54aSTrevor Wu etdm_data->slave_mode = true; 2178*1de9a54aSTrevor Wu break; 2179*1de9a54aSTrevor Wu case SND_SOC_DAIFMT_CBS_CFS: 2180*1de9a54aSTrevor Wu etdm_data->slave_mode = false; 2181*1de9a54aSTrevor Wu break; 2182*1de9a54aSTrevor Wu default: 2183*1de9a54aSTrevor Wu return -EINVAL; 2184*1de9a54aSTrevor Wu } 2185*1de9a54aSTrevor Wu 2186*1de9a54aSTrevor Wu return 0; 2187*1de9a54aSTrevor Wu } 2188*1de9a54aSTrevor Wu 2189*1de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2190*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 2191*1de9a54aSTrevor Wu { 2192*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2193*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2194*1de9a54aSTrevor Wu int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2195*1de9a54aSTrevor Wu 2196*1de9a54aSTrevor Wu if (cg_id >= 0) 2197*1de9a54aSTrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2198*1de9a54aSTrevor Wu 2199*1de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 2200*1de9a54aSTrevor Wu 2201*1de9a54aSTrevor Wu return 0; 2202*1de9a54aSTrevor Wu } 2203*1de9a54aSTrevor Wu 2204*1de9a54aSTrevor Wu static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2205*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 2206*1de9a54aSTrevor Wu { 2207*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2208*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2209*1de9a54aSTrevor Wu int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2210*1de9a54aSTrevor Wu 2211*1de9a54aSTrevor Wu mtk_dai_etdm_disable_mclk(afe, dai->id); 2212*1de9a54aSTrevor Wu 2213*1de9a54aSTrevor Wu if (cg_id >= 0) 2214*1de9a54aSTrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2215*1de9a54aSTrevor Wu } 2216*1de9a54aSTrevor Wu 2217*1de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2218*1de9a54aSTrevor Wu { 2219*1de9a54aSTrevor Wu switch (channel) { 2220*1de9a54aSTrevor Wu case 1 ... 2: 2221*1de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_2CH; 2222*1de9a54aSTrevor Wu case 3 ... 4: 2223*1de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_4CH; 2224*1de9a54aSTrevor Wu case 5 ... 6: 2225*1de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_6CH; 2226*1de9a54aSTrevor Wu case 7 ... 8: 2227*1de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_8CH; 2228*1de9a54aSTrevor Wu default: 2229*1de9a54aSTrevor Wu return AFE_DPTX_CON_CH_EN_2CH; 2230*1de9a54aSTrevor Wu } 2231*1de9a54aSTrevor Wu } 2232*1de9a54aSTrevor Wu 2233*1de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2234*1de9a54aSTrevor Wu { 2235*1de9a54aSTrevor Wu return (ch > 2) ? 2236*1de9a54aSTrevor Wu AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2237*1de9a54aSTrevor Wu } 2238*1de9a54aSTrevor Wu 2239*1de9a54aSTrevor Wu static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2240*1de9a54aSTrevor Wu { 2241*1de9a54aSTrevor Wu return snd_pcm_format_physical_width(format) <= 16 ? 2242*1de9a54aSTrevor Wu AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2243*1de9a54aSTrevor Wu } 2244*1de9a54aSTrevor Wu 2245*1de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2246*1de9a54aSTrevor Wu struct snd_pcm_hw_params *params, 2247*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 2248*1de9a54aSTrevor Wu { 2249*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2250*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2251*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2252*1de9a54aSTrevor Wu unsigned int rate = params_rate(params); 2253*1de9a54aSTrevor Wu unsigned int channels = params_channels(params); 2254*1de9a54aSTrevor Wu snd_pcm_format_t format = params_format(params); 2255*1de9a54aSTrevor Wu int width = snd_pcm_format_physical_width(format); 2256*1de9a54aSTrevor Wu int ret = 0; 2257*1de9a54aSTrevor Wu 2258*1de9a54aSTrevor Wu /* dptx configure */ 2259*1de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) { 2260*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2261*1de9a54aSTrevor Wu AFE_DPTX_CON_CH_EN_MASK, 2262*1de9a54aSTrevor Wu mtk_dai_get_dptx_ch_en(channels)); 2263*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2264*1de9a54aSTrevor Wu AFE_DPTX_CON_CH_NUM_MASK, 2265*1de9a54aSTrevor Wu mtk_dai_get_dptx_ch(channels)); 2266*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2267*1de9a54aSTrevor Wu AFE_DPTX_CON_16BIT_MASK, 2268*1de9a54aSTrevor Wu mtk_dai_get_dptx_wlen(format)); 2269*1de9a54aSTrevor Wu 2270*1de9a54aSTrevor Wu if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2271*1de9a54aSTrevor Wu etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2272*1de9a54aSTrevor Wu channels = 8; 2273*1de9a54aSTrevor Wu } else { 2274*1de9a54aSTrevor Wu channels = 2; 2275*1de9a54aSTrevor Wu } 2276*1de9a54aSTrevor Wu } else { 2277*1de9a54aSTrevor Wu etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2278*1de9a54aSTrevor Wu } 2279*1de9a54aSTrevor Wu 2280*1de9a54aSTrevor Wu ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2281*1de9a54aSTrevor Wu if (ret) 2282*1de9a54aSTrevor Wu return ret; 2283*1de9a54aSTrevor Wu 2284*1de9a54aSTrevor Wu ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2285*1de9a54aSTrevor Wu 2286*1de9a54aSTrevor Wu return ret; 2287*1de9a54aSTrevor Wu } 2288*1de9a54aSTrevor Wu 2289*1de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_trigger(struct snd_pcm_substream *substream, 2290*1de9a54aSTrevor Wu int cmd, 2291*1de9a54aSTrevor Wu struct snd_soc_dai *dai) 2292*1de9a54aSTrevor Wu { 2293*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2294*1de9a54aSTrevor Wu int ret = 0; 2295*1de9a54aSTrevor Wu 2296*1de9a54aSTrevor Wu dev_dbg(afe->dev, "%s(), cmd %d, dai id %d\n", __func__, cmd, dai->id); 2297*1de9a54aSTrevor Wu 2298*1de9a54aSTrevor Wu switch (cmd) { 2299*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_START: 2300*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_RESUME: 2301*1de9a54aSTrevor Wu /* enable dptx interface */ 2302*1de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) 2303*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2304*1de9a54aSTrevor Wu AFE_DPTX_CON_ON_MASK, 2305*1de9a54aSTrevor Wu AFE_DPTX_CON_ON); 2306*1de9a54aSTrevor Wu 2307*1de9a54aSTrevor Wu /* enable etdm_out3 */ 2308*1de9a54aSTrevor Wu ret = mt8195_afe_enable_etdm(afe, dai->id); 2309*1de9a54aSTrevor Wu break; 2310*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_STOP: 2311*1de9a54aSTrevor Wu case SNDRV_PCM_TRIGGER_SUSPEND: 2312*1de9a54aSTrevor Wu /* disable etdm_out3 */ 2313*1de9a54aSTrevor Wu ret = mt8195_afe_disable_etdm(afe, dai->id); 2314*1de9a54aSTrevor Wu 2315*1de9a54aSTrevor Wu /* disable dptx interface */ 2316*1de9a54aSTrevor Wu if (dai->id == MT8195_AFE_IO_DPTX) 2317*1de9a54aSTrevor Wu regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2318*1de9a54aSTrevor Wu AFE_DPTX_CON_ON_MASK, 0); 2319*1de9a54aSTrevor Wu break; 2320*1de9a54aSTrevor Wu default: 2321*1de9a54aSTrevor Wu return -EINVAL; 2322*1de9a54aSTrevor Wu } 2323*1de9a54aSTrevor Wu 2324*1de9a54aSTrevor Wu return ret; 2325*1de9a54aSTrevor Wu } 2326*1de9a54aSTrevor Wu 2327*1de9a54aSTrevor Wu static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2328*1de9a54aSTrevor Wu int clk_id, 2329*1de9a54aSTrevor Wu unsigned int freq, 2330*1de9a54aSTrevor Wu int dir) 2331*1de9a54aSTrevor Wu { 2332*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2333*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2334*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2335*1de9a54aSTrevor Wu 2336*1de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2337*1de9a54aSTrevor Wu __func__, dai->id, freq, dir); 2338*1de9a54aSTrevor Wu 2339*1de9a54aSTrevor Wu etdm_data->mclk_dir = dir; 2340*1de9a54aSTrevor Wu return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2341*1de9a54aSTrevor Wu } 2342*1de9a54aSTrevor Wu 2343*1de9a54aSTrevor Wu static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2344*1de9a54aSTrevor Wu .startup = mtk_dai_etdm_startup, 2345*1de9a54aSTrevor Wu .shutdown = mtk_dai_etdm_shutdown, 2346*1de9a54aSTrevor Wu .hw_params = mtk_dai_etdm_hw_params, 2347*1de9a54aSTrevor Wu .trigger = mtk_dai_etdm_trigger, 2348*1de9a54aSTrevor Wu .set_sysclk = mtk_dai_etdm_set_sysclk, 2349*1de9a54aSTrevor Wu .set_fmt = mtk_dai_etdm_set_fmt, 2350*1de9a54aSTrevor Wu .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2351*1de9a54aSTrevor Wu }; 2352*1de9a54aSTrevor Wu 2353*1de9a54aSTrevor Wu static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2354*1de9a54aSTrevor Wu .startup = mtk_dai_hdmitx_dptx_startup, 2355*1de9a54aSTrevor Wu .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2356*1de9a54aSTrevor Wu .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2357*1de9a54aSTrevor Wu .trigger = mtk_dai_hdmitx_dptx_trigger, 2358*1de9a54aSTrevor Wu .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2359*1de9a54aSTrevor Wu .set_fmt = mtk_dai_etdm_set_fmt, 2360*1de9a54aSTrevor Wu }; 2361*1de9a54aSTrevor Wu 2362*1de9a54aSTrevor Wu /* dai driver */ 2363*1de9a54aSTrevor Wu #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_384000) 2364*1de9a54aSTrevor Wu 2365*1de9a54aSTrevor Wu #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2366*1de9a54aSTrevor Wu SNDRV_PCM_FMTBIT_S24_LE |\ 2367*1de9a54aSTrevor Wu SNDRV_PCM_FMTBIT_S32_LE) 2368*1de9a54aSTrevor Wu 2369*1de9a54aSTrevor Wu static int mtk_dai_etdm_probe(struct snd_soc_dai *dai) 2370*1de9a54aSTrevor Wu { 2371*1de9a54aSTrevor Wu struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2372*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2373*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data = afe_priv->dai_priv[dai->id]; 2374*1de9a54aSTrevor Wu 2375*1de9a54aSTrevor Wu dev_dbg(dai->dev, "%s id %d\n", __func__, dai->id); 2376*1de9a54aSTrevor Wu 2377*1de9a54aSTrevor Wu if (etdm_data->mclk_freq) { 2378*1de9a54aSTrevor Wu dev_dbg(afe->dev, "MCLK always on, rate %d\n", 2379*1de9a54aSTrevor Wu etdm_data->mclk_freq); 2380*1de9a54aSTrevor Wu pm_runtime_get_sync(afe->dev); 2381*1de9a54aSTrevor Wu mtk_dai_etdm_mclk_configure(afe, dai->id); 2382*1de9a54aSTrevor Wu mtk_dai_etdm_enable_mclk(afe, dai->id); 2383*1de9a54aSTrevor Wu pm_runtime_put_sync(afe->dev); 2384*1de9a54aSTrevor Wu } 2385*1de9a54aSTrevor Wu return 0; 2386*1de9a54aSTrevor Wu } 2387*1de9a54aSTrevor Wu 2388*1de9a54aSTrevor Wu static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2389*1de9a54aSTrevor Wu { 2390*1de9a54aSTrevor Wu .name = "DPTX", 2391*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_DPTX, 2392*1de9a54aSTrevor Wu .playback = { 2393*1de9a54aSTrevor Wu .stream_name = "DPTX Playback", 2394*1de9a54aSTrevor Wu .channels_min = 1, 2395*1de9a54aSTrevor Wu .channels_max = 8, 2396*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2397*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2398*1de9a54aSTrevor Wu }, 2399*1de9a54aSTrevor Wu .ops = &mtk_dai_hdmitx_dptx_ops, 2400*1de9a54aSTrevor Wu }, 2401*1de9a54aSTrevor Wu { 2402*1de9a54aSTrevor Wu .name = "ETDM1_IN", 2403*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM1_IN, 2404*1de9a54aSTrevor Wu .capture = { 2405*1de9a54aSTrevor Wu .stream_name = "ETDM1 Capture", 2406*1de9a54aSTrevor Wu .channels_min = 1, 2407*1de9a54aSTrevor Wu .channels_max = 24, 2408*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2409*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2410*1de9a54aSTrevor Wu }, 2411*1de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 2412*1de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 2413*1de9a54aSTrevor Wu }, 2414*1de9a54aSTrevor Wu { 2415*1de9a54aSTrevor Wu .name = "ETDM2_IN", 2416*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM2_IN, 2417*1de9a54aSTrevor Wu .capture = { 2418*1de9a54aSTrevor Wu .stream_name = "ETDM2 Capture", 2419*1de9a54aSTrevor Wu .channels_min = 1, 2420*1de9a54aSTrevor Wu .channels_max = 16, 2421*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2422*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2423*1de9a54aSTrevor Wu }, 2424*1de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 2425*1de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 2426*1de9a54aSTrevor Wu }, 2427*1de9a54aSTrevor Wu { 2428*1de9a54aSTrevor Wu .name = "ETDM1_OUT", 2429*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM1_OUT, 2430*1de9a54aSTrevor Wu .playback = { 2431*1de9a54aSTrevor Wu .stream_name = "ETDM1 Playback", 2432*1de9a54aSTrevor Wu .channels_min = 1, 2433*1de9a54aSTrevor Wu .channels_max = 24, 2434*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2435*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2436*1de9a54aSTrevor Wu }, 2437*1de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 2438*1de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 2439*1de9a54aSTrevor Wu }, 2440*1de9a54aSTrevor Wu { 2441*1de9a54aSTrevor Wu .name = "ETDM2_OUT", 2442*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM2_OUT, 2443*1de9a54aSTrevor Wu .playback = { 2444*1de9a54aSTrevor Wu .stream_name = "ETDM2 Playback", 2445*1de9a54aSTrevor Wu .channels_min = 1, 2446*1de9a54aSTrevor Wu .channels_max = 24, 2447*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2448*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2449*1de9a54aSTrevor Wu }, 2450*1de9a54aSTrevor Wu .ops = &mtk_dai_etdm_ops, 2451*1de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 2452*1de9a54aSTrevor Wu }, 2453*1de9a54aSTrevor Wu { 2454*1de9a54aSTrevor Wu .name = "ETDM3_OUT", 2455*1de9a54aSTrevor Wu .id = MT8195_AFE_IO_ETDM3_OUT, 2456*1de9a54aSTrevor Wu .playback = { 2457*1de9a54aSTrevor Wu .stream_name = "ETDM3 Playback", 2458*1de9a54aSTrevor Wu .channels_min = 1, 2459*1de9a54aSTrevor Wu .channels_max = 8, 2460*1de9a54aSTrevor Wu .rates = MTK_ETDM_RATES, 2461*1de9a54aSTrevor Wu .formats = MTK_ETDM_FORMATS, 2462*1de9a54aSTrevor Wu }, 2463*1de9a54aSTrevor Wu .ops = &mtk_dai_hdmitx_dptx_ops, 2464*1de9a54aSTrevor Wu .probe = mtk_dai_etdm_probe, 2465*1de9a54aSTrevor Wu }, 2466*1de9a54aSTrevor Wu }; 2467*1de9a54aSTrevor Wu 2468*1de9a54aSTrevor Wu static void mt8195_etdm_update_sync_info(struct mtk_base_afe *afe) 2469*1de9a54aSTrevor Wu { 2470*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2471*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data; 2472*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *mst_data; 2473*1de9a54aSTrevor Wu int i; 2474*1de9a54aSTrevor Wu int mst_dai_id; 2475*1de9a54aSTrevor Wu 2476*1de9a54aSTrevor Wu for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2477*1de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[i]; 2478*1de9a54aSTrevor Wu if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2479*1de9a54aSTrevor Wu mst_dai_id = etdm_data->cowork_source_id; 2480*1de9a54aSTrevor Wu mst_data = afe_priv->dai_priv[mst_dai_id]; 2481*1de9a54aSTrevor Wu if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2482*1de9a54aSTrevor Wu dev_info(afe->dev, "%s [%d] wrong sync source\n" 2483*1de9a54aSTrevor Wu , __func__, i); 2484*1de9a54aSTrevor Wu mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2485*1de9a54aSTrevor Wu mst_data->cowork_slv_count++; 2486*1de9a54aSTrevor Wu } 2487*1de9a54aSTrevor Wu } 2488*1de9a54aSTrevor Wu } 2489*1de9a54aSTrevor Wu 2490*1de9a54aSTrevor Wu static void mt8195_dai_etdm_parse_of(struct mtk_base_afe *afe) 2491*1de9a54aSTrevor Wu { 2492*1de9a54aSTrevor Wu const struct device_node *of_node = afe->dev->of_node; 2493*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2494*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_data; 2495*1de9a54aSTrevor Wu int i, j; 2496*1de9a54aSTrevor Wu char prop[48]; 2497*1de9a54aSTrevor Wu u8 disable_chn[MT8195_ETDM_MAX_CHANNELS]; 2498*1de9a54aSTrevor Wu int max_chn = MT8195_ETDM_MAX_CHANNELS; 2499*1de9a54aSTrevor Wu u32 sel; 2500*1de9a54aSTrevor Wu int ret; 2501*1de9a54aSTrevor Wu int dai_id; 2502*1de9a54aSTrevor Wu unsigned int sync_id; 2503*1de9a54aSTrevor Wu struct { 2504*1de9a54aSTrevor Wu const char *name; 2505*1de9a54aSTrevor Wu const unsigned int sync_id; 2506*1de9a54aSTrevor Wu } of_afe_etdms[MT8195_AFE_IO_ETDM_NUM] = { 2507*1de9a54aSTrevor Wu {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2508*1de9a54aSTrevor Wu {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2509*1de9a54aSTrevor Wu {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2510*1de9a54aSTrevor Wu {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2511*1de9a54aSTrevor Wu {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2512*1de9a54aSTrevor Wu }; 2513*1de9a54aSTrevor Wu 2514*1de9a54aSTrevor Wu for (i = 0; i < MT8195_AFE_IO_ETDM_NUM; i++) { 2515*1de9a54aSTrevor Wu dai_id = ETDM_TO_DAI_ID(i); 2516*1de9a54aSTrevor Wu etdm_data = afe_priv->dai_priv[dai_id]; 2517*1de9a54aSTrevor Wu 2518*1de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 2519*1de9a54aSTrevor Wu "mediatek,%s-mclk-always-on-rate", 2520*1de9a54aSTrevor Wu of_afe_etdms[i].name); 2521*1de9a54aSTrevor Wu if (ret < 0) { 2522*1de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 2523*1de9a54aSTrevor Wu __func__, ret); 2524*1de9a54aSTrevor Wu return; 2525*1de9a54aSTrevor Wu } 2526*1de9a54aSTrevor Wu ret = of_property_read_u32(of_node, prop, &sel); 2527*1de9a54aSTrevor Wu if (ret == 0) { 2528*1de9a54aSTrevor Wu etdm_data->mclk_dir = SND_SOC_CLOCK_OUT; 2529*1de9a54aSTrevor Wu if (mtk_dai_etdm_cal_mclk(afe, sel, dai_id)) 2530*1de9a54aSTrevor Wu dev_info(afe->dev, "%s unsupported mclk %uHz\n", 2531*1de9a54aSTrevor Wu __func__, sel); 2532*1de9a54aSTrevor Wu } 2533*1de9a54aSTrevor Wu 2534*1de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 2535*1de9a54aSTrevor Wu "mediatek,%s-multi-pin-mode", 2536*1de9a54aSTrevor Wu of_afe_etdms[i].name); 2537*1de9a54aSTrevor Wu if (ret < 0) { 2538*1de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 2539*1de9a54aSTrevor Wu __func__, ret); 2540*1de9a54aSTrevor Wu return; 2541*1de9a54aSTrevor Wu } 2542*1de9a54aSTrevor Wu etdm_data->data_mode = of_property_read_bool(of_node, prop); 2543*1de9a54aSTrevor Wu 2544*1de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 2545*1de9a54aSTrevor Wu "mediatek,%s-cowork-source", 2546*1de9a54aSTrevor Wu of_afe_etdms[i].name); 2547*1de9a54aSTrevor Wu if (ret < 0) { 2548*1de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 2549*1de9a54aSTrevor Wu __func__, ret); 2550*1de9a54aSTrevor Wu return; 2551*1de9a54aSTrevor Wu } 2552*1de9a54aSTrevor Wu ret = of_property_read_u32(of_node, prop, &sel); 2553*1de9a54aSTrevor Wu if (ret == 0) { 2554*1de9a54aSTrevor Wu if (sel >= MT8195_AFE_IO_ETDM_NUM) { 2555*1de9a54aSTrevor Wu dev_info(afe->dev, "%s invalid id=%d\n", 2556*1de9a54aSTrevor Wu __func__, sel); 2557*1de9a54aSTrevor Wu etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2558*1de9a54aSTrevor Wu } else { 2559*1de9a54aSTrevor Wu sync_id = of_afe_etdms[sel].sync_id; 2560*1de9a54aSTrevor Wu etdm_data->cowork_source_id = 2561*1de9a54aSTrevor Wu sync_to_dai_id(sync_id); 2562*1de9a54aSTrevor Wu } 2563*1de9a54aSTrevor Wu } else { 2564*1de9a54aSTrevor Wu etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2565*1de9a54aSTrevor Wu } 2566*1de9a54aSTrevor Wu } 2567*1de9a54aSTrevor Wu 2568*1de9a54aSTrevor Wu /* etdm in only */ 2569*1de9a54aSTrevor Wu for (i = 0; i < 2; i++) { 2570*1de9a54aSTrevor Wu ret = snprintf(prop, sizeof(prop), 2571*1de9a54aSTrevor Wu "mediatek,%s-chn-disabled", 2572*1de9a54aSTrevor Wu of_afe_etdms[i].name); 2573*1de9a54aSTrevor Wu if (ret < 0) { 2574*1de9a54aSTrevor Wu dev_info(afe->dev, "%s snprintf err=%d\n", 2575*1de9a54aSTrevor Wu __func__, ret); 2576*1de9a54aSTrevor Wu return; 2577*1de9a54aSTrevor Wu } 2578*1de9a54aSTrevor Wu ret = of_property_read_variable_u8_array(of_node, prop, 2579*1de9a54aSTrevor Wu disable_chn, 2580*1de9a54aSTrevor Wu 1, max_chn); 2581*1de9a54aSTrevor Wu if (ret < 0) 2582*1de9a54aSTrevor Wu continue; 2583*1de9a54aSTrevor Wu 2584*1de9a54aSTrevor Wu for (j = 0; j < ret; j++) { 2585*1de9a54aSTrevor Wu if (disable_chn[j] >= MT8195_ETDM_MAX_CHANNELS) 2586*1de9a54aSTrevor Wu dev_info(afe->dev, "%s [%d] invalid chn %u\n", 2587*1de9a54aSTrevor Wu __func__, j, disable_chn[j]); 2588*1de9a54aSTrevor Wu else 2589*1de9a54aSTrevor Wu etdm_data->in_disable_ch[disable_chn[j]] = true; 2590*1de9a54aSTrevor Wu } 2591*1de9a54aSTrevor Wu } 2592*1de9a54aSTrevor Wu mt8195_etdm_update_sync_info(afe); 2593*1de9a54aSTrevor Wu } 2594*1de9a54aSTrevor Wu 2595*1de9a54aSTrevor Wu static int init_etdm_priv_data(struct mtk_base_afe *afe) 2596*1de9a54aSTrevor Wu { 2597*1de9a54aSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 2598*1de9a54aSTrevor Wu struct mtk_dai_etdm_priv *etdm_priv; 2599*1de9a54aSTrevor Wu int i; 2600*1de9a54aSTrevor Wu 2601*1de9a54aSTrevor Wu for (i = MT8195_AFE_IO_ETDM_START; i < MT8195_AFE_IO_ETDM_END; i++) { 2602*1de9a54aSTrevor Wu etdm_priv = devm_kzalloc(afe->dev, 2603*1de9a54aSTrevor Wu sizeof(struct mtk_dai_etdm_priv), 2604*1de9a54aSTrevor Wu GFP_KERNEL); 2605*1de9a54aSTrevor Wu if (!etdm_priv) 2606*1de9a54aSTrevor Wu return -ENOMEM; 2607*1de9a54aSTrevor Wu 2608*1de9a54aSTrevor Wu afe_priv->dai_priv[i] = etdm_priv; 2609*1de9a54aSTrevor Wu } 2610*1de9a54aSTrevor Wu 2611*1de9a54aSTrevor Wu afe_priv->dai_priv[MT8195_AFE_IO_DPTX] = 2612*1de9a54aSTrevor Wu afe_priv->dai_priv[MT8195_AFE_IO_ETDM3_OUT]; 2613*1de9a54aSTrevor Wu 2614*1de9a54aSTrevor Wu mt8195_dai_etdm_parse_of(afe); 2615*1de9a54aSTrevor Wu return 0; 2616*1de9a54aSTrevor Wu } 2617*1de9a54aSTrevor Wu 2618*1de9a54aSTrevor Wu int mt8195_dai_etdm_register(struct mtk_base_afe *afe) 2619*1de9a54aSTrevor Wu { 2620*1de9a54aSTrevor Wu struct mtk_base_afe_dai *dai; 2621*1de9a54aSTrevor Wu 2622*1de9a54aSTrevor Wu dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2623*1de9a54aSTrevor Wu if (!dai) 2624*1de9a54aSTrevor Wu return -ENOMEM; 2625*1de9a54aSTrevor Wu 2626*1de9a54aSTrevor Wu list_add(&dai->list, &afe->sub_dais); 2627*1de9a54aSTrevor Wu 2628*1de9a54aSTrevor Wu dai->dai_drivers = mtk_dai_etdm_driver; 2629*1de9a54aSTrevor Wu dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2630*1de9a54aSTrevor Wu 2631*1de9a54aSTrevor Wu dai->dapm_widgets = mtk_dai_etdm_widgets; 2632*1de9a54aSTrevor Wu dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2633*1de9a54aSTrevor Wu dai->dapm_routes = mtk_dai_etdm_routes; 2634*1de9a54aSTrevor Wu dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2635*1de9a54aSTrevor Wu dai->controls = mtk_dai_etdm_controls; 2636*1de9a54aSTrevor Wu dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2637*1de9a54aSTrevor Wu 2638*1de9a54aSTrevor Wu return init_etdm_priv_data(afe); 2639*1de9a54aSTrevor Wu } 2640