1*d62ad762STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*d62ad762STrevor Wu /* 3*d62ad762STrevor Wu * mt8195-audsys-clkid.h -- Mediatek 8195 audsys clock id definition 4*d62ad762STrevor Wu * 5*d62ad762STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*d62ad762STrevor Wu * Author: Trevor Wu <trevor.wu@mediatek.com> 7*d62ad762STrevor Wu */ 8*d62ad762STrevor Wu 9*d62ad762STrevor Wu #ifndef _MT8195_AUDSYS_CLKID_H_ 10*d62ad762STrevor Wu #define _MT8195_AUDSYS_CLKID_H_ 11*d62ad762STrevor Wu 12*d62ad762STrevor Wu enum{ 13*d62ad762STrevor Wu CLK_AUD_AFE, 14*d62ad762STrevor Wu CLK_AUD_LRCK_CNT, 15*d62ad762STrevor Wu CLK_AUD_SPDIFIN_TUNER_APLL, 16*d62ad762STrevor Wu CLK_AUD_SPDIFIN_TUNER_DBG, 17*d62ad762STrevor Wu CLK_AUD_UL_TML, 18*d62ad762STrevor Wu CLK_AUD_APLL1_TUNER, 19*d62ad762STrevor Wu CLK_AUD_APLL2_TUNER, 20*d62ad762STrevor Wu CLK_AUD_TOP0_SPDF, 21*d62ad762STrevor Wu CLK_AUD_APLL, 22*d62ad762STrevor Wu CLK_AUD_APLL2, 23*d62ad762STrevor Wu CLK_AUD_DAC, 24*d62ad762STrevor Wu CLK_AUD_DAC_PREDIS, 25*d62ad762STrevor Wu CLK_AUD_TML, 26*d62ad762STrevor Wu CLK_AUD_ADC, 27*d62ad762STrevor Wu CLK_AUD_DAC_HIRES, 28*d62ad762STrevor Wu CLK_AUD_A1SYS_HP, 29*d62ad762STrevor Wu CLK_AUD_AFE_DMIC1, 30*d62ad762STrevor Wu CLK_AUD_AFE_DMIC2, 31*d62ad762STrevor Wu CLK_AUD_AFE_DMIC3, 32*d62ad762STrevor Wu CLK_AUD_AFE_DMIC4, 33*d62ad762STrevor Wu CLK_AUD_AFE_26M_DMIC_TM, 34*d62ad762STrevor Wu CLK_AUD_UL_TML_HIRES, 35*d62ad762STrevor Wu CLK_AUD_ADC_HIRES, 36*d62ad762STrevor Wu CLK_AUD_ADDA6_ADC, 37*d62ad762STrevor Wu CLK_AUD_ADDA6_ADC_HIRES, 38*d62ad762STrevor Wu CLK_AUD_LINEIN_TUNER, 39*d62ad762STrevor Wu CLK_AUD_EARC_TUNER, 40*d62ad762STrevor Wu CLK_AUD_I2SIN, 41*d62ad762STrevor Wu CLK_AUD_TDM_IN, 42*d62ad762STrevor Wu CLK_AUD_I2S_OUT, 43*d62ad762STrevor Wu CLK_AUD_TDM_OUT, 44*d62ad762STrevor Wu CLK_AUD_HDMI_OUT, 45*d62ad762STrevor Wu CLK_AUD_ASRC11, 46*d62ad762STrevor Wu CLK_AUD_ASRC12, 47*d62ad762STrevor Wu CLK_AUD_MULTI_IN, 48*d62ad762STrevor Wu CLK_AUD_INTDIR, 49*d62ad762STrevor Wu CLK_AUD_A1SYS, 50*d62ad762STrevor Wu CLK_AUD_A2SYS, 51*d62ad762STrevor Wu CLK_AUD_PCMIF, 52*d62ad762STrevor Wu CLK_AUD_A3SYS, 53*d62ad762STrevor Wu CLK_AUD_A4SYS, 54*d62ad762STrevor Wu CLK_AUD_MEMIF_UL1, 55*d62ad762STrevor Wu CLK_AUD_MEMIF_UL2, 56*d62ad762STrevor Wu CLK_AUD_MEMIF_UL3, 57*d62ad762STrevor Wu CLK_AUD_MEMIF_UL4, 58*d62ad762STrevor Wu CLK_AUD_MEMIF_UL5, 59*d62ad762STrevor Wu CLK_AUD_MEMIF_UL6, 60*d62ad762STrevor Wu CLK_AUD_MEMIF_UL8, 61*d62ad762STrevor Wu CLK_AUD_MEMIF_UL9, 62*d62ad762STrevor Wu CLK_AUD_MEMIF_UL10, 63*d62ad762STrevor Wu CLK_AUD_MEMIF_DL2, 64*d62ad762STrevor Wu CLK_AUD_MEMIF_DL3, 65*d62ad762STrevor Wu CLK_AUD_MEMIF_DL6, 66*d62ad762STrevor Wu CLK_AUD_MEMIF_DL7, 67*d62ad762STrevor Wu CLK_AUD_MEMIF_DL8, 68*d62ad762STrevor Wu CLK_AUD_MEMIF_DL10, 69*d62ad762STrevor Wu CLK_AUD_MEMIF_DL11, 70*d62ad762STrevor Wu CLK_AUD_GASRC0, 71*d62ad762STrevor Wu CLK_AUD_GASRC1, 72*d62ad762STrevor Wu CLK_AUD_GASRC2, 73*d62ad762STrevor Wu CLK_AUD_GASRC3, 74*d62ad762STrevor Wu CLK_AUD_GASRC4, 75*d62ad762STrevor Wu CLK_AUD_GASRC5, 76*d62ad762STrevor Wu CLK_AUD_GASRC6, 77*d62ad762STrevor Wu CLK_AUD_GASRC7, 78*d62ad762STrevor Wu CLK_AUD_GASRC8, 79*d62ad762STrevor Wu CLK_AUD_GASRC9, 80*d62ad762STrevor Wu CLK_AUD_GASRC10, 81*d62ad762STrevor Wu CLK_AUD_GASRC11, 82*d62ad762STrevor Wu CLK_AUD_GASRC12, 83*d62ad762STrevor Wu CLK_AUD_GASRC13, 84*d62ad762STrevor Wu CLK_AUD_GASRC14, 85*d62ad762STrevor Wu CLK_AUD_GASRC15, 86*d62ad762STrevor Wu CLK_AUD_GASRC16, 87*d62ad762STrevor Wu CLK_AUD_GASRC17, 88*d62ad762STrevor Wu CLK_AUD_GASRC18, 89*d62ad762STrevor Wu CLK_AUD_GASRC19, 90*d62ad762STrevor Wu CLK_AUD_NR_CLK, 91*d62ad762STrevor Wu }; 92*d62ad762STrevor Wu 93*d62ad762STrevor Wu #endif 94