1*d62ad762STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*d62ad762STrevor Wu /* 3*d62ad762STrevor Wu * mt8195-audsys-clk.h -- Mediatek 8195 audsys clock definition 4*d62ad762STrevor Wu * 5*d62ad762STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*d62ad762STrevor Wu * Author: Trevor Wu <trevor.wu@mediatek.com> 7*d62ad762STrevor Wu */ 8*d62ad762STrevor Wu 9*d62ad762STrevor Wu #ifndef _MT8195_AUDSYS_CLK_H_ 10*d62ad762STrevor Wu #define _MT8195_AUDSYS_CLK_H_ 11*d62ad762STrevor Wu 12*d62ad762STrevor Wu int mt8195_audsys_clk_register(struct mtk_base_afe *afe); 13*d62ad762STrevor Wu 14*d62ad762STrevor Wu #endif 15