1d62ad762STrevor Wu // SPDX-License-Identifier: GPL-2.0 2d62ad762STrevor Wu /* 3d62ad762STrevor Wu * mt8195-audsys-clk.h -- Mediatek 8195 audsys clock control 4d62ad762STrevor Wu * 5d62ad762STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6d62ad762STrevor Wu * Author: Trevor Wu <trevor.wu@mediatek.com> 7d62ad762STrevor Wu */ 8d62ad762STrevor Wu 9d62ad762STrevor Wu #include <linux/clk.h> 10d62ad762STrevor Wu #include <linux/clk-provider.h> 11d62ad762STrevor Wu #include <linux/clkdev.h> 12d62ad762STrevor Wu #include "mt8195-afe-common.h" 13d62ad762STrevor Wu #include "mt8195-audsys-clk.h" 14d62ad762STrevor Wu #include "mt8195-audsys-clkid.h" 15d62ad762STrevor Wu #include "mt8195-reg.h" 16d62ad762STrevor Wu 17d62ad762STrevor Wu struct afe_gate { 18d62ad762STrevor Wu int id; 19d62ad762STrevor Wu const char *name; 20d62ad762STrevor Wu const char *parent_name; 21d62ad762STrevor Wu int reg; 22d62ad762STrevor Wu u8 bit; 23d62ad762STrevor Wu const struct clk_ops *ops; 24d62ad762STrevor Wu unsigned long flags; 25d62ad762STrevor Wu u8 cg_flags; 26d62ad762STrevor Wu }; 27d62ad762STrevor Wu 28d62ad762STrevor Wu #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 29d62ad762STrevor Wu .id = _id, \ 30d62ad762STrevor Wu .name = _name, \ 31d62ad762STrevor Wu .parent_name = _parent, \ 32d62ad762STrevor Wu .reg = _reg, \ 33d62ad762STrevor Wu .bit = _bit, \ 34d62ad762STrevor Wu .flags = _flags, \ 35d62ad762STrevor Wu .cg_flags = _cgflags, \ 36d62ad762STrevor Wu } 37d62ad762STrevor Wu 38d62ad762STrevor Wu #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 39d62ad762STrevor Wu GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \ 40d62ad762STrevor Wu CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE) 41d62ad762STrevor Wu 42d62ad762STrevor Wu #define GATE_AUD0(_id, _name, _parent, _bit) \ 43d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit) 44d62ad762STrevor Wu 45d62ad762STrevor Wu #define GATE_AUD1(_id, _name, _parent, _bit) \ 46d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit) 47d62ad762STrevor Wu 48d62ad762STrevor Wu #define GATE_AUD3(_id, _name, _parent, _bit) \ 49d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit) 50d62ad762STrevor Wu 51d62ad762STrevor Wu #define GATE_AUD4(_id, _name, _parent, _bit) \ 52d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON4, _bit) 53d62ad762STrevor Wu 54d62ad762STrevor Wu #define GATE_AUD5(_id, _name, _parent, _bit) \ 55d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON5, _bit) 56d62ad762STrevor Wu 57d62ad762STrevor Wu #define GATE_AUD6(_id, _name, _parent, _bit) \ 58d62ad762STrevor Wu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON6, _bit) 59d62ad762STrevor Wu 60d62ad762STrevor Wu static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = { 61d62ad762STrevor Wu /* AUD0 */ 6252453525STrevor Wu GATE_AUD0(CLK_AUD_AFE, "aud_afe", "top_a1sys_hp", 2), 6352453525STrevor Wu GATE_AUD0(CLK_AUD_LRCK_CNT, "aud_lrck_cnt", "top_a1sys_hp", 4), 6452453525STrevor Wu GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_APLL, "aud_spdifin_tuner_apll", "top_apll4", 10), 6552453525STrevor Wu GATE_AUD0(CLK_AUD_SPDIFIN_TUNER_DBG, "aud_spdifin_tuner_dbg", "top_apll4", 11), 6652453525STrevor Wu GATE_AUD0(CLK_AUD_UL_TML, "aud_ul_tml", "top_a1sys_hp", 18), 6752453525STrevor Wu GATE_AUD0(CLK_AUD_APLL1_TUNER, "aud_apll1_tuner", "top_apll1", 19), 6852453525STrevor Wu GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner", "top_apll2", 20), 6952453525STrevor Wu GATE_AUD0(CLK_AUD_TOP0_SPDF, "aud_top0_spdf", "top_aud_iec_clk", 21), 7052453525STrevor Wu GATE_AUD0(CLK_AUD_APLL, "aud_apll", "top_apll1", 23), 7152453525STrevor Wu GATE_AUD0(CLK_AUD_APLL2, "aud_apll2", "top_apll2", 24), 7252453525STrevor Wu GATE_AUD0(CLK_AUD_DAC, "aud_dac", "top_a1sys_hp", 25), 7352453525STrevor Wu GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis", "top_a1sys_hp", 26), 7452453525STrevor Wu GATE_AUD0(CLK_AUD_TML, "aud_tml", "top_a1sys_hp", 27), 7552453525STrevor Wu GATE_AUD0(CLK_AUD_ADC, "aud_adc", "top_a1sys_hp", 28), 7652453525STrevor Wu GATE_AUD0(CLK_AUD_DAC_HIRES, "aud_dac_hires", "top_audio_h", 31), 77d62ad762STrevor Wu 78d62ad762STrevor Wu /* AUD1 */ 7952453525STrevor Wu GATE_AUD1(CLK_AUD_A1SYS_HP, "aud_a1sys_hp", "top_a1sys_hp", 2), 8052453525STrevor Wu GATE_AUD1(CLK_AUD_AFE_DMIC1, "aud_afe_dmic1", "top_a1sys_hp", 10), 8152453525STrevor Wu GATE_AUD1(CLK_AUD_AFE_DMIC2, "aud_afe_dmic2", "top_a1sys_hp", 11), 8252453525STrevor Wu GATE_AUD1(CLK_AUD_AFE_DMIC3, "aud_afe_dmic3", "top_a1sys_hp", 12), 8352453525STrevor Wu GATE_AUD1(CLK_AUD_AFE_DMIC4, "aud_afe_dmic4", "top_a1sys_hp", 13), 8452453525STrevor Wu GATE_AUD1(CLK_AUD_AFE_26M_DMIC_TM, "aud_afe_26m_dmic_tm", "top_a1sys_hp", 14), 8552453525STrevor Wu GATE_AUD1(CLK_AUD_UL_TML_HIRES, "aud_ul_tml_hires", "top_audio_h", 16), 8652453525STrevor Wu GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires", "top_audio_h", 17), 8752453525STrevor Wu GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_a1sys_hp", 18), 8852453525STrevor Wu GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 19), 89d62ad762STrevor Wu 90d62ad762STrevor Wu /* AUD3 */ 9152453525STrevor Wu GATE_AUD3(CLK_AUD_LINEIN_TUNER, "aud_linein_tuner", "top_apll5", 5), 9252453525STrevor Wu GATE_AUD3(CLK_AUD_EARC_TUNER, "aud_earc_tuner", "top_apll3", 7), 93d62ad762STrevor Wu 94d62ad762STrevor Wu /* AUD4 */ 9552453525STrevor Wu GATE_AUD4(CLK_AUD_I2SIN, "aud_i2sin", "top_a1sys_hp", 0), 9652453525STrevor Wu GATE_AUD4(CLK_AUD_TDM_IN, "aud_tdm_in", "top_a1sys_hp", 1), 9752453525STrevor Wu GATE_AUD4(CLK_AUD_I2S_OUT, "aud_i2s_out", "top_a1sys_hp", 6), 9852453525STrevor Wu GATE_AUD4(CLK_AUD_TDM_OUT, "aud_tdm_out", "top_a1sys_hp", 7), 9952453525STrevor Wu GATE_AUD4(CLK_AUD_HDMI_OUT, "aud_hdmi_out", "top_a1sys_hp", 8), 10052453525STrevor Wu GATE_AUD4(CLK_AUD_ASRC11, "aud_asrc11", "top_a1sys_hp", 16), 10152453525STrevor Wu GATE_AUD4(CLK_AUD_ASRC12, "aud_asrc12", "top_a1sys_hp", 17), 102d62ad762STrevor Wu GATE_AUD4(CLK_AUD_MULTI_IN, "aud_multi_in", "mphone_slave_b", 19), 10352453525STrevor Wu GATE_AUD4(CLK_AUD_INTDIR, "aud_intdir", "top_intdir", 20), 10452453525STrevor Wu GATE_AUD4(CLK_AUD_A1SYS, "aud_a1sys", "top_a1sys_hp", 21), 10552453525STrevor Wu GATE_AUD4(CLK_AUD_A2SYS, "aud_a2sys", "top_a2sys_hf", 22), 10652453525STrevor Wu GATE_AUD4(CLK_AUD_PCMIF, "aud_pcmif", "top_a1sys_hp", 24), 10752453525STrevor Wu GATE_AUD4(CLK_AUD_A3SYS, "aud_a3sys", "top_a3sys_hf", 30), 10852453525STrevor Wu GATE_AUD4(CLK_AUD_A4SYS, "aud_a4sys", "top_a4sys_hf", 31), 109d62ad762STrevor Wu 110d62ad762STrevor Wu /* AUD5 */ 11152453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL1, "aud_memif_ul1", "top_a1sys_hp", 0), 11252453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL2, "aud_memif_ul2", "top_a1sys_hp", 1), 11352453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL3, "aud_memif_ul3", "top_a1sys_hp", 2), 11452453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL4, "aud_memif_ul4", "top_a1sys_hp", 3), 11552453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL5, "aud_memif_ul5", "top_a1sys_hp", 4), 11652453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL6, "aud_memif_ul6", "top_a1sys_hp", 5), 11752453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL8, "aud_memif_ul8", "top_a1sys_hp", 7), 11852453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL9, "aud_memif_ul9", "top_a1sys_hp", 8), 11952453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_UL10, "aud_memif_ul10", "top_a1sys_hp", 9), 12052453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL2, "aud_memif_dl2", "top_a1sys_hp", 18), 12152453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL3, "aud_memif_dl3", "top_a1sys_hp", 19), 12252453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL6, "aud_memif_dl6", "top_a1sys_hp", 22), 12352453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL7, "aud_memif_dl7", "top_a1sys_hp", 23), 12452453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL8, "aud_memif_dl8", "top_a1sys_hp", 24), 12552453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL10, "aud_memif_dl10", "top_a1sys_hp", 26), 12652453525STrevor Wu GATE_AUD5(CLK_AUD_MEMIF_DL11, "aud_memif_dl11", "top_a1sys_hp", 27), 127d62ad762STrevor Wu 128d62ad762STrevor Wu /* AUD6 */ 12952453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC0, "aud_gasrc0", "top_asm_h", 0), 13052453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC1, "aud_gasrc1", "top_asm_h", 1), 13152453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC2, "aud_gasrc2", "top_asm_h", 2), 13252453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC3, "aud_gasrc3", "top_asm_h", 3), 13352453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC4, "aud_gasrc4", "top_asm_h", 4), 13452453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC5, "aud_gasrc5", "top_asm_h", 5), 13552453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC6, "aud_gasrc6", "top_asm_h", 6), 13652453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC7, "aud_gasrc7", "top_asm_h", 7), 13752453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC8, "aud_gasrc8", "top_asm_h", 8), 13852453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC9, "aud_gasrc9", "top_asm_h", 9), 13952453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC10, "aud_gasrc10", "top_asm_h", 10), 14052453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC11, "aud_gasrc11", "top_asm_h", 11), 14152453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC12, "aud_gasrc12", "top_asm_h", 12), 14252453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC13, "aud_gasrc13", "top_asm_h", 13), 14352453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC14, "aud_gasrc14", "top_asm_h", 14), 14452453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC15, "aud_gasrc15", "top_asm_h", 15), 14552453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC16, "aud_gasrc16", "top_asm_h", 16), 14652453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC17, "aud_gasrc17", "top_asm_h", 17), 14752453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC18, "aud_gasrc18", "top_asm_h", 18), 14852453525STrevor Wu GATE_AUD6(CLK_AUD_GASRC19, "aud_gasrc19", "top_asm_h", 19), 149d62ad762STrevor Wu }; 150d62ad762STrevor Wu 151*dc93f0dcSTrevor Wu static void mt8195_audsys_clk_unregister(void *data) 152*dc93f0dcSTrevor Wu { 153*dc93f0dcSTrevor Wu struct mtk_base_afe *afe = data; 154*dc93f0dcSTrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 155*dc93f0dcSTrevor Wu struct clk *clk; 156*dc93f0dcSTrevor Wu struct clk_lookup *cl; 157*dc93f0dcSTrevor Wu int i; 158*dc93f0dcSTrevor Wu 159*dc93f0dcSTrevor Wu if (!afe_priv) 160*dc93f0dcSTrevor Wu return; 161*dc93f0dcSTrevor Wu 162*dc93f0dcSTrevor Wu for (i = 0; i < CLK_AUD_NR_CLK; i++) { 163*dc93f0dcSTrevor Wu cl = afe_priv->lookup[i]; 164*dc93f0dcSTrevor Wu if (!cl) 165*dc93f0dcSTrevor Wu continue; 166*dc93f0dcSTrevor Wu 167*dc93f0dcSTrevor Wu clk = cl->clk; 168*dc93f0dcSTrevor Wu clk_unregister_gate(clk); 169*dc93f0dcSTrevor Wu 170*dc93f0dcSTrevor Wu clkdev_drop(cl); 171*dc93f0dcSTrevor Wu } 172*dc93f0dcSTrevor Wu } 173*dc93f0dcSTrevor Wu 174d62ad762STrevor Wu int mt8195_audsys_clk_register(struct mtk_base_afe *afe) 175d62ad762STrevor Wu { 176d62ad762STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 177d62ad762STrevor Wu struct clk *clk; 178d62ad762STrevor Wu struct clk_lookup *cl; 179d62ad762STrevor Wu int i; 180d62ad762STrevor Wu 181d62ad762STrevor Wu afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK, 182d62ad762STrevor Wu sizeof(*afe_priv->lookup), 183d62ad762STrevor Wu GFP_KERNEL); 184d62ad762STrevor Wu 185d62ad762STrevor Wu if (!afe_priv->lookup) 186d62ad762STrevor Wu return -ENOMEM; 187d62ad762STrevor Wu 188d62ad762STrevor Wu for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 189d62ad762STrevor Wu const struct afe_gate *gate = &aud_clks[i]; 190d62ad762STrevor Wu 191d62ad762STrevor Wu clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 192d62ad762STrevor Wu gate->flags, afe->base_addr + gate->reg, 193d62ad762STrevor Wu gate->bit, gate->cg_flags, NULL); 194d62ad762STrevor Wu 195d62ad762STrevor Wu if (IS_ERR(clk)) { 196d62ad762STrevor Wu dev_err(afe->dev, "Failed to register clk %s: %ld\n", 197d62ad762STrevor Wu gate->name, PTR_ERR(clk)); 198d62ad762STrevor Wu continue; 199d62ad762STrevor Wu } 200d62ad762STrevor Wu 201d62ad762STrevor Wu /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */ 202d62ad762STrevor Wu cl = kzalloc(sizeof(*cl), GFP_KERNEL); 203d62ad762STrevor Wu if (!cl) 204d62ad762STrevor Wu return -ENOMEM; 205d62ad762STrevor Wu 206d62ad762STrevor Wu cl->clk = clk; 207d62ad762STrevor Wu cl->con_id = gate->name; 208d62ad762STrevor Wu cl->dev_id = dev_name(afe->dev); 209d62ad762STrevor Wu clkdev_add(cl); 210d62ad762STrevor Wu 211d62ad762STrevor Wu afe_priv->lookup[i] = cl; 212d62ad762STrevor Wu } 213d62ad762STrevor Wu 214*dc93f0dcSTrevor Wu return devm_add_action_or_reset(afe->dev, mt8195_audsys_clk_unregister, afe); 215d62ad762STrevor Wu } 216