1*6746cc85STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*6746cc85STrevor Wu /* 3*6746cc85STrevor Wu * mt8195-afe-common.h -- Mediatek 8195 audio driver definitions 4*6746cc85STrevor Wu * 5*6746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*6746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*6746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*6746cc85STrevor Wu */ 9*6746cc85STrevor Wu 10*6746cc85STrevor Wu #ifndef _MT_8195_AFE_COMMON_H_ 11*6746cc85STrevor Wu #define _MT_8195_AFE_COMMON_H_ 12*6746cc85STrevor Wu 13*6746cc85STrevor Wu #include <sound/soc.h> 14*6746cc85STrevor Wu #include <linux/list.h> 15*6746cc85STrevor Wu #include <linux/regmap.h> 16*6746cc85STrevor Wu #include "../common/mtk-base-afe.h" 17*6746cc85STrevor Wu 18*6746cc85STrevor Wu enum { 19*6746cc85STrevor Wu MT8195_DAI_START, 20*6746cc85STrevor Wu MT8195_AFE_MEMIF_START = MT8195_DAI_START, 21*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL2 = MT8195_AFE_MEMIF_START, 22*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL3, 23*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL6, 24*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL7, 25*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL8, 26*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL10, 27*6746cc85STrevor Wu MT8195_AFE_MEMIF_DL11, 28*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL_START, 29*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL1 = MT8195_AFE_MEMIF_UL_START, 30*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL2, 31*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL3, 32*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL4, 33*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL5, 34*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL6, 35*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL8, 36*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL9, 37*6746cc85STrevor Wu MT8195_AFE_MEMIF_UL10, 38*6746cc85STrevor Wu MT8195_AFE_MEMIF_END, 39*6746cc85STrevor Wu MT8195_AFE_MEMIF_NUM = (MT8195_AFE_MEMIF_END - MT8195_AFE_MEMIF_START), 40*6746cc85STrevor Wu MT8195_AFE_IO_START = MT8195_AFE_MEMIF_END, 41*6746cc85STrevor Wu MT8195_AFE_IO_DL_SRC = MT8195_AFE_IO_START, 42*6746cc85STrevor Wu MT8195_AFE_IO_DPTX, 43*6746cc85STrevor Wu MT8195_AFE_IO_ETDM_START, 44*6746cc85STrevor Wu MT8195_AFE_IO_ETDM1_IN = MT8195_AFE_IO_ETDM_START, 45*6746cc85STrevor Wu MT8195_AFE_IO_ETDM2_IN, 46*6746cc85STrevor Wu MT8195_AFE_IO_ETDM1_OUT, 47*6746cc85STrevor Wu MT8195_AFE_IO_ETDM2_OUT, 48*6746cc85STrevor Wu MT8195_AFE_IO_ETDM3_OUT, 49*6746cc85STrevor Wu MT8195_AFE_IO_ETDM_END, 50*6746cc85STrevor Wu MT8195_AFE_IO_ETDM_NUM = 51*6746cc85STrevor Wu (MT8195_AFE_IO_ETDM_END - MT8195_AFE_IO_ETDM_START), 52*6746cc85STrevor Wu MT8195_AFE_IO_PCM = MT8195_AFE_IO_ETDM_END, 53*6746cc85STrevor Wu MT8195_AFE_IO_UL_SRC1, 54*6746cc85STrevor Wu MT8195_AFE_IO_UL_SRC2, 55*6746cc85STrevor Wu MT8195_AFE_IO_END, 56*6746cc85STrevor Wu MT8195_AFE_IO_NUM = (MT8195_AFE_IO_END - MT8195_AFE_IO_START), 57*6746cc85STrevor Wu MT8195_DAI_END = MT8195_AFE_IO_END, 58*6746cc85STrevor Wu MT8195_DAI_NUM = (MT8195_DAI_END - MT8195_DAI_START), 59*6746cc85STrevor Wu }; 60*6746cc85STrevor Wu 61*6746cc85STrevor Wu enum { 62*6746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 63*6746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 64*6746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 65*6746cc85STrevor Wu MT8195_TOP_CG_NUM, 66*6746cc85STrevor Wu }; 67*6746cc85STrevor Wu 68*6746cc85STrevor Wu enum { 69*6746cc85STrevor Wu MT8195_AFE_IRQ_1, 70*6746cc85STrevor Wu MT8195_AFE_IRQ_2, 71*6746cc85STrevor Wu MT8195_AFE_IRQ_3, 72*6746cc85STrevor Wu MT8195_AFE_IRQ_8, 73*6746cc85STrevor Wu MT8195_AFE_IRQ_9, 74*6746cc85STrevor Wu MT8195_AFE_IRQ_10, 75*6746cc85STrevor Wu MT8195_AFE_IRQ_13, 76*6746cc85STrevor Wu MT8195_AFE_IRQ_14, 77*6746cc85STrevor Wu MT8195_AFE_IRQ_15, 78*6746cc85STrevor Wu MT8195_AFE_IRQ_16, 79*6746cc85STrevor Wu MT8195_AFE_IRQ_17, 80*6746cc85STrevor Wu MT8195_AFE_IRQ_18, 81*6746cc85STrevor Wu MT8195_AFE_IRQ_19, 82*6746cc85STrevor Wu MT8195_AFE_IRQ_20, 83*6746cc85STrevor Wu MT8195_AFE_IRQ_21, 84*6746cc85STrevor Wu MT8195_AFE_IRQ_22, 85*6746cc85STrevor Wu MT8195_AFE_IRQ_23, 86*6746cc85STrevor Wu MT8195_AFE_IRQ_24, 87*6746cc85STrevor Wu MT8195_AFE_IRQ_25, 88*6746cc85STrevor Wu MT8195_AFE_IRQ_26, 89*6746cc85STrevor Wu MT8195_AFE_IRQ_27, 90*6746cc85STrevor Wu MT8195_AFE_IRQ_28, 91*6746cc85STrevor Wu MT8195_AFE_IRQ_NUM, 92*6746cc85STrevor Wu }; 93*6746cc85STrevor Wu 94*6746cc85STrevor Wu enum { 95*6746cc85STrevor Wu MT8195_ETDM_OUT1_1X_EN = 9, 96*6746cc85STrevor Wu MT8195_ETDM_OUT2_1X_EN = 10, 97*6746cc85STrevor Wu MT8195_ETDM_OUT3_1X_EN = 11, 98*6746cc85STrevor Wu MT8195_ETDM_IN1_1X_EN = 12, 99*6746cc85STrevor Wu MT8195_ETDM_IN2_1X_EN = 13, 100*6746cc85STrevor Wu MT8195_ETDM_IN1_NX_EN = 25, 101*6746cc85STrevor Wu MT8195_ETDM_IN2_NX_EN = 26, 102*6746cc85STrevor Wu }; 103*6746cc85STrevor Wu 104*6746cc85STrevor Wu enum { 105*6746cc85STrevor Wu MT8195_MTKAIF_MISO_0, 106*6746cc85STrevor Wu MT8195_MTKAIF_MISO_1, 107*6746cc85STrevor Wu MT8195_MTKAIF_MISO_2, 108*6746cc85STrevor Wu MT8195_MTKAIF_MISO_NUM, 109*6746cc85STrevor Wu }; 110*6746cc85STrevor Wu 111*6746cc85STrevor Wu struct mtk_dai_memif_irq_priv { 112*6746cc85STrevor Wu unsigned int asys_timing_sel; 113*6746cc85STrevor Wu }; 114*6746cc85STrevor Wu 115*6746cc85STrevor Wu struct mtkaif_param { 116*6746cc85STrevor Wu bool mtkaif_calibration_ok; 117*6746cc85STrevor Wu int mtkaif_chosen_phase[MT8195_MTKAIF_MISO_NUM]; 118*6746cc85STrevor Wu int mtkaif_phase_cycle[MT8195_MTKAIF_MISO_NUM]; 119*6746cc85STrevor Wu int mtkaif_dmic_on; 120*6746cc85STrevor Wu int mtkaif_adda6_only; 121*6746cc85STrevor Wu }; 122*6746cc85STrevor Wu 123*6746cc85STrevor Wu struct clk; 124*6746cc85STrevor Wu 125*6746cc85STrevor Wu struct mt8195_afe_private { 126*6746cc85STrevor Wu struct clk **clk; 127*6746cc85STrevor Wu struct clk_lookup **lookup; 128*6746cc85STrevor Wu struct regmap *topckgen; 129*6746cc85STrevor Wu int pm_runtime_bypass_reg_ctl; 130*6746cc85STrevor Wu #ifdef CONFIG_DEBUG_FS 131*6746cc85STrevor Wu struct dentry **debugfs_dentry; 132*6746cc85STrevor Wu #endif 133*6746cc85STrevor Wu int afe_on_ref_cnt; 134*6746cc85STrevor Wu int top_cg_ref_cnt[MT8195_TOP_CG_NUM]; 135*6746cc85STrevor Wu spinlock_t afe_ctrl_lock; /* Lock for afe control */ 136*6746cc85STrevor Wu struct mtk_dai_memif_irq_priv irq_priv[MT8195_AFE_IRQ_NUM]; 137*6746cc85STrevor Wu struct mtkaif_param mtkaif_params; 138*6746cc85STrevor Wu 139*6746cc85STrevor Wu /* dai */ 140*6746cc85STrevor Wu void *dai_priv[MT8195_DAI_NUM]; 141*6746cc85STrevor Wu }; 142*6746cc85STrevor Wu 143*6746cc85STrevor Wu int mt8195_afe_fs_timing(unsigned int rate); 144*6746cc85STrevor Wu /* dai register */ 145*6746cc85STrevor Wu int mt8195_dai_adda_register(struct mtk_base_afe *afe); 146*6746cc85STrevor Wu int mt8195_dai_etdm_register(struct mtk_base_afe *afe); 147*6746cc85STrevor Wu int mt8195_dai_pcm_register(struct mtk_base_afe *afe); 148*6746cc85STrevor Wu 149*6746cc85STrevor Wu #define MT8195_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \ 150*6746cc85STrevor Wu { \ 151*6746cc85STrevor Wu .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 152*6746cc85STrevor Wu .info = snd_soc_info_enum_double, \ 153*6746cc85STrevor Wu .get = xhandler_get, .put = xhandler_put, \ 154*6746cc85STrevor Wu .device = id, \ 155*6746cc85STrevor Wu .private_value = (unsigned long)&xenum, \ 156*6746cc85STrevor Wu } 157*6746cc85STrevor Wu 158*6746cc85STrevor Wu #endif 159