1*6746cc85STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*6746cc85STrevor Wu /* 3*6746cc85STrevor Wu * mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition 4*6746cc85STrevor Wu * 5*6746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*6746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*6746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*6746cc85STrevor Wu */ 9*6746cc85STrevor Wu 10*6746cc85STrevor Wu #ifndef _MT8195_AFE_CLK_H_ 11*6746cc85STrevor Wu #define _MT8195_AFE_CLK_H_ 12*6746cc85STrevor Wu 13*6746cc85STrevor Wu enum { 14*6746cc85STrevor Wu /* xtal */ 15*6746cc85STrevor Wu MT8195_CLK_XTAL_26M, 16*6746cc85STrevor Wu /* divider */ 17*6746cc85STrevor Wu MT8195_CLK_TOP_APLL1, 18*6746cc85STrevor Wu MT8195_CLK_TOP_APLL2, 19*6746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV0, 20*6746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV1, 21*6746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV2, 22*6746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV3, 23*6746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV9, 24*6746cc85STrevor Wu /* mux */ 25*6746cc85STrevor Wu MT8195_CLK_TOP_A1SYS_HP_SEL, 26*6746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, 27*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, 28*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 29*6746cc85STrevor Wu MT8195_CLK_TOP_DPTX_M_SEL, 30*6746cc85STrevor Wu MT8195_CLK_TOP_I2SO1_M_SEL, 31*6746cc85STrevor Wu MT8195_CLK_TOP_I2SO2_M_SEL, 32*6746cc85STrevor Wu MT8195_CLK_TOP_I2SI1_M_SEL, 33*6746cc85STrevor Wu MT8195_CLK_TOP_I2SI2_M_SEL, 34*6746cc85STrevor Wu /* clock gate */ 35*6746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, 36*6746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, 37*6746cc85STrevor Wu MT8195_CLK_AUD_AFE, 38*6746cc85STrevor Wu MT8195_CLK_AUD_APLL, 39*6746cc85STrevor Wu MT8195_CLK_AUD_APLL2, 40*6746cc85STrevor Wu MT8195_CLK_AUD_DAC, 41*6746cc85STrevor Wu MT8195_CLK_AUD_ADC, 42*6746cc85STrevor Wu MT8195_CLK_AUD_DAC_HIRES, 43*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, 44*6746cc85STrevor Wu MT8195_CLK_AUD_ADC_HIRES, 45*6746cc85STrevor Wu MT8195_CLK_AUD_ADDA6_ADC, 46*6746cc85STrevor Wu MT8195_CLK_AUD_ADDA6_ADC_HIRES, 47*6746cc85STrevor Wu MT8195_CLK_AUD_I2SIN, 48*6746cc85STrevor Wu MT8195_CLK_AUD_TDM_IN, 49*6746cc85STrevor Wu MT8195_CLK_AUD_I2S_OUT, 50*6746cc85STrevor Wu MT8195_CLK_AUD_TDM_OUT, 51*6746cc85STrevor Wu MT8195_CLK_AUD_HDMI_OUT, 52*6746cc85STrevor Wu MT8195_CLK_AUD_ASRC11, 53*6746cc85STrevor Wu MT8195_CLK_AUD_ASRC12, 54*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 55*6746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 56*6746cc85STrevor Wu MT8195_CLK_AUD_PCMIF, 57*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL1, 58*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL2, 59*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL3, 60*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL4, 61*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL5, 62*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL6, 63*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL8, 64*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL9, 65*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL10, 66*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL2, 67*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL3, 68*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL6, 69*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL7, 70*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL8, 71*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL10, 72*6746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL11, 73*6746cc85STrevor Wu MT8195_CLK_NUM, 74*6746cc85STrevor Wu }; 75*6746cc85STrevor Wu 76*6746cc85STrevor Wu enum { 77*6746cc85STrevor Wu MT8195_MCK_SEL_26M, 78*6746cc85STrevor Wu MT8195_MCK_SEL_APLL1, 79*6746cc85STrevor Wu MT8195_MCK_SEL_APLL2, 80*6746cc85STrevor Wu MT8195_MCK_SEL_APLL3, 81*6746cc85STrevor Wu MT8195_MCK_SEL_APLL4, 82*6746cc85STrevor Wu MT8195_MCK_SEL_APLL5, 83*6746cc85STrevor Wu MT8195_MCK_SEL_HDMIRX_APLL, 84*6746cc85STrevor Wu MT8195_MCK_SEL_NUM, 85*6746cc85STrevor Wu }; 86*6746cc85STrevor Wu 87*6746cc85STrevor Wu struct mtk_base_afe; 88*6746cc85STrevor Wu 89*6746cc85STrevor Wu int mt8195_afe_get_mclk_source_clk_id(int sel); 90*6746cc85STrevor Wu int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 91*6746cc85STrevor Wu int mt8195_afe_get_default_mclk_source_by_rate(int rate); 92*6746cc85STrevor Wu int mt8195_afe_init_clock(struct mtk_base_afe *afe); 93*6746cc85STrevor Wu void mt8195_afe_deinit_clock(struct mtk_base_afe *afe); 94*6746cc85STrevor Wu int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 95*6746cc85STrevor Wu void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 96*6746cc85STrevor Wu int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk); 97*6746cc85STrevor Wu void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk); 98*6746cc85STrevor Wu int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk); 99*6746cc85STrevor Wu void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk); 100*6746cc85STrevor Wu int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 101*6746cc85STrevor Wu unsigned int rate); 102*6746cc85STrevor Wu int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 103*6746cc85STrevor Wu struct clk *parent); 104*6746cc85STrevor Wu int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe); 105*6746cc85STrevor Wu int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe); 106*6746cc85STrevor Wu int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 107*6746cc85STrevor Wu int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 108*6746cc85STrevor Wu 109*6746cc85STrevor Wu #endif 110