16746cc85STrevor Wu // SPDX-License-Identifier: GPL-2.0 26746cc85STrevor Wu /* 36746cc85STrevor Wu * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl 46746cc85STrevor Wu * 56746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 66746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 76746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 86746cc85STrevor Wu */ 96746cc85STrevor Wu 106746cc85STrevor Wu #include <linux/clk.h> 116746cc85STrevor Wu 126746cc85STrevor Wu #include "mt8195-afe-common.h" 136746cc85STrevor Wu #include "mt8195-afe-clk.h" 146746cc85STrevor Wu #include "mt8195-reg.h" 156746cc85STrevor Wu #include "mt8195-audsys-clk.h" 166746cc85STrevor Wu 176746cc85STrevor Wu static const char *aud_clks[MT8195_CLK_NUM] = { 186746cc85STrevor Wu /* xtal */ 196746cc85STrevor Wu [MT8195_CLK_XTAL_26M] = "clk26m", 206746cc85STrevor Wu /* divider */ 216746cc85STrevor Wu [MT8195_CLK_TOP_APLL1] = "apll1_ck", 226746cc85STrevor Wu [MT8195_CLK_TOP_APLL2] = "apll2_ck", 236746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0", 246746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1", 256746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2", 266746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3", 276746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9", 286746cc85STrevor Wu /* mux */ 296746cc85STrevor Wu [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel", 306746cc85STrevor Wu [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel", 316746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel", 326746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel", 336746cc85STrevor Wu [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel", 346746cc85STrevor Wu [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel", 356746cc85STrevor Wu [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel", 366746cc85STrevor Wu [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel", 376746cc85STrevor Wu [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel", 386746cc85STrevor Wu /* clock gate */ 396746cc85STrevor Wu [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b", 406746cc85STrevor Wu [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", 416746cc85STrevor Wu /* afe clock gate */ 426746cc85STrevor Wu [MT8195_CLK_AUD_AFE] = "aud_afe", 43*ff5a9017STrevor Wu [MT8195_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", 44*ff5a9017STrevor Wu [MT8195_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", 456746cc85STrevor Wu [MT8195_CLK_AUD_APLL] = "aud_apll", 466746cc85STrevor Wu [MT8195_CLK_AUD_APLL2] = "aud_apll2", 476746cc85STrevor Wu [MT8195_CLK_AUD_DAC] = "aud_dac", 486746cc85STrevor Wu [MT8195_CLK_AUD_ADC] = "aud_adc", 496746cc85STrevor Wu [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires", 506746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", 516746cc85STrevor Wu [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires", 526746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc", 536746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires", 546746cc85STrevor Wu [MT8195_CLK_AUD_I2SIN] = "aud_i2sin", 556746cc85STrevor Wu [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in", 566746cc85STrevor Wu [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out", 576746cc85STrevor Wu [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out", 586746cc85STrevor Wu [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", 596746cc85STrevor Wu [MT8195_CLK_AUD_ASRC11] = "aud_asrc11", 606746cc85STrevor Wu [MT8195_CLK_AUD_ASRC12] = "aud_asrc12", 616746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS] = "aud_a1sys", 626746cc85STrevor Wu [MT8195_CLK_AUD_A2SYS] = "aud_a2sys", 636746cc85STrevor Wu [MT8195_CLK_AUD_PCMIF] = "aud_pcmif", 646746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", 656746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", 666746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", 676746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", 686746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", 696746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", 706746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", 716746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", 726746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", 736746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", 746746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", 756746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", 766746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", 776746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", 786746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", 796746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", 806746cc85STrevor Wu }; 816746cc85STrevor Wu 82*ff5a9017STrevor Wu struct mt8195_afe_tuner_cfg { 83*ff5a9017STrevor Wu unsigned int id; 84*ff5a9017STrevor Wu int apll_div_reg; 85*ff5a9017STrevor Wu unsigned int apll_div_shift; 86*ff5a9017STrevor Wu unsigned int apll_div_maskbit; 87*ff5a9017STrevor Wu unsigned int apll_div_default; 88*ff5a9017STrevor Wu int ref_ck_sel_reg; 89*ff5a9017STrevor Wu unsigned int ref_ck_sel_shift; 90*ff5a9017STrevor Wu unsigned int ref_ck_sel_maskbit; 91*ff5a9017STrevor Wu unsigned int ref_ck_sel_default; 92*ff5a9017STrevor Wu int tuner_en_reg; 93*ff5a9017STrevor Wu unsigned int tuner_en_shift; 94*ff5a9017STrevor Wu unsigned int tuner_en_maskbit; 95*ff5a9017STrevor Wu int upper_bound_reg; 96*ff5a9017STrevor Wu unsigned int upper_bound_shift; 97*ff5a9017STrevor Wu unsigned int upper_bound_maskbit; 98*ff5a9017STrevor Wu unsigned int upper_bound_default; 99*ff5a9017STrevor Wu spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/ 100*ff5a9017STrevor Wu int ref_cnt; 101*ff5a9017STrevor Wu }; 102*ff5a9017STrevor Wu 103*ff5a9017STrevor Wu static struct mt8195_afe_tuner_cfg mt8195_afe_tuner_cfgs[MT8195_AUD_PLL_NUM] = { 104*ff5a9017STrevor Wu [MT8195_AUD_PLL1] = { 105*ff5a9017STrevor Wu .id = MT8195_AUD_PLL1, 106*ff5a9017STrevor Wu .apll_div_reg = AFE_APLL_TUNER_CFG, 107*ff5a9017STrevor Wu .apll_div_shift = 4, 108*ff5a9017STrevor Wu .apll_div_maskbit = 0xf, 109*ff5a9017STrevor Wu .apll_div_default = 0x7, 110*ff5a9017STrevor Wu .ref_ck_sel_reg = AFE_APLL_TUNER_CFG, 111*ff5a9017STrevor Wu .ref_ck_sel_shift = 1, 112*ff5a9017STrevor Wu .ref_ck_sel_maskbit = 0x3, 113*ff5a9017STrevor Wu .ref_ck_sel_default = 0x2, 114*ff5a9017STrevor Wu .tuner_en_reg = AFE_APLL_TUNER_CFG, 115*ff5a9017STrevor Wu .tuner_en_shift = 0, 116*ff5a9017STrevor Wu .tuner_en_maskbit = 0x1, 117*ff5a9017STrevor Wu .upper_bound_reg = AFE_APLL_TUNER_CFG, 118*ff5a9017STrevor Wu .upper_bound_shift = 8, 119*ff5a9017STrevor Wu .upper_bound_maskbit = 0xff, 120*ff5a9017STrevor Wu .upper_bound_default = 0x2, 121*ff5a9017STrevor Wu }, 122*ff5a9017STrevor Wu [MT8195_AUD_PLL2] = { 123*ff5a9017STrevor Wu .id = MT8195_AUD_PLL2, 124*ff5a9017STrevor Wu .apll_div_reg = AFE_APLL_TUNER_CFG1, 125*ff5a9017STrevor Wu .apll_div_shift = 4, 126*ff5a9017STrevor Wu .apll_div_maskbit = 0xf, 127*ff5a9017STrevor Wu .apll_div_default = 0x7, 128*ff5a9017STrevor Wu .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1, 129*ff5a9017STrevor Wu .ref_ck_sel_shift = 1, 130*ff5a9017STrevor Wu .ref_ck_sel_maskbit = 0x3, 131*ff5a9017STrevor Wu .ref_ck_sel_default = 0x1, 132*ff5a9017STrevor Wu .tuner_en_reg = AFE_APLL_TUNER_CFG1, 133*ff5a9017STrevor Wu .tuner_en_shift = 0, 134*ff5a9017STrevor Wu .tuner_en_maskbit = 0x1, 135*ff5a9017STrevor Wu .upper_bound_reg = AFE_APLL_TUNER_CFG1, 136*ff5a9017STrevor Wu .upper_bound_shift = 8, 137*ff5a9017STrevor Wu .upper_bound_maskbit = 0xff, 138*ff5a9017STrevor Wu .upper_bound_default = 0x2, 139*ff5a9017STrevor Wu }, 140*ff5a9017STrevor Wu [MT8195_AUD_PLL3] = { 141*ff5a9017STrevor Wu .id = MT8195_AUD_PLL3, 142*ff5a9017STrevor Wu .apll_div_reg = AFE_EARC_APLL_TUNER_CFG, 143*ff5a9017STrevor Wu .apll_div_shift = 4, 144*ff5a9017STrevor Wu .apll_div_maskbit = 0x3f, 145*ff5a9017STrevor Wu .apll_div_default = 0x3, 146*ff5a9017STrevor Wu .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG, 147*ff5a9017STrevor Wu .ref_ck_sel_shift = 24, 148*ff5a9017STrevor Wu .ref_ck_sel_maskbit = 0x3, 149*ff5a9017STrevor Wu .ref_ck_sel_default = 0x0, 150*ff5a9017STrevor Wu .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG, 151*ff5a9017STrevor Wu .tuner_en_shift = 0, 152*ff5a9017STrevor Wu .tuner_en_maskbit = 0x1, 153*ff5a9017STrevor Wu .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG, 154*ff5a9017STrevor Wu .upper_bound_shift = 12, 155*ff5a9017STrevor Wu .upper_bound_maskbit = 0xff, 156*ff5a9017STrevor Wu .upper_bound_default = 0x4, 157*ff5a9017STrevor Wu }, 158*ff5a9017STrevor Wu [MT8195_AUD_PLL4] = { 159*ff5a9017STrevor Wu .id = MT8195_AUD_PLL4, 160*ff5a9017STrevor Wu .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 161*ff5a9017STrevor Wu .apll_div_shift = 4, 162*ff5a9017STrevor Wu .apll_div_maskbit = 0x3f, 163*ff5a9017STrevor Wu .apll_div_default = 0x7, 164*ff5a9017STrevor Wu .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1, 165*ff5a9017STrevor Wu .ref_ck_sel_shift = 8, 166*ff5a9017STrevor Wu .ref_ck_sel_maskbit = 0x1, 167*ff5a9017STrevor Wu .ref_ck_sel_default = 0, 168*ff5a9017STrevor Wu .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 169*ff5a9017STrevor Wu .tuner_en_shift = 0, 170*ff5a9017STrevor Wu .tuner_en_maskbit = 0x1, 171*ff5a9017STrevor Wu .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 172*ff5a9017STrevor Wu .upper_bound_shift = 12, 173*ff5a9017STrevor Wu .upper_bound_maskbit = 0xff, 174*ff5a9017STrevor Wu .upper_bound_default = 0x4, 175*ff5a9017STrevor Wu }, 176*ff5a9017STrevor Wu [MT8195_AUD_PLL5] = { 177*ff5a9017STrevor Wu .id = MT8195_AUD_PLL5, 178*ff5a9017STrevor Wu .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG, 179*ff5a9017STrevor Wu .apll_div_shift = 4, 180*ff5a9017STrevor Wu .apll_div_maskbit = 0x3f, 181*ff5a9017STrevor Wu .apll_div_default = 0x3, 182*ff5a9017STrevor Wu .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG, 183*ff5a9017STrevor Wu .ref_ck_sel_shift = 24, 184*ff5a9017STrevor Wu .ref_ck_sel_maskbit = 0x1, 185*ff5a9017STrevor Wu .ref_ck_sel_default = 0, 186*ff5a9017STrevor Wu .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG, 187*ff5a9017STrevor Wu .tuner_en_shift = 0, 188*ff5a9017STrevor Wu .tuner_en_maskbit = 0x1, 189*ff5a9017STrevor Wu .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG, 190*ff5a9017STrevor Wu .upper_bound_shift = 12, 191*ff5a9017STrevor Wu .upper_bound_maskbit = 0xff, 192*ff5a9017STrevor Wu .upper_bound_default = 0x4, 193*ff5a9017STrevor Wu }, 194*ff5a9017STrevor Wu }; 195*ff5a9017STrevor Wu 196*ff5a9017STrevor Wu static struct mt8195_afe_tuner_cfg *mt8195_afe_found_apll_tuner(unsigned int id) 197*ff5a9017STrevor Wu { 198*ff5a9017STrevor Wu if (id >= MT8195_AUD_PLL_NUM) 199*ff5a9017STrevor Wu return NULL; 200*ff5a9017STrevor Wu 201*ff5a9017STrevor Wu return &mt8195_afe_tuner_cfgs[id]; 202*ff5a9017STrevor Wu } 203*ff5a9017STrevor Wu 204*ff5a9017STrevor Wu static int mt8195_afe_init_apll_tuner(unsigned int id) 205*ff5a9017STrevor Wu { 206*ff5a9017STrevor Wu struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); 207*ff5a9017STrevor Wu 208*ff5a9017STrevor Wu if (!cfg) 209*ff5a9017STrevor Wu return -EINVAL; 210*ff5a9017STrevor Wu 211*ff5a9017STrevor Wu cfg->ref_cnt = 0; 212*ff5a9017STrevor Wu spin_lock_init(&cfg->ctrl_lock); 213*ff5a9017STrevor Wu 214*ff5a9017STrevor Wu return 0; 215*ff5a9017STrevor Wu } 216*ff5a9017STrevor Wu 217*ff5a9017STrevor Wu static int mt8195_afe_setup_apll_tuner(struct mtk_base_afe *afe, 218*ff5a9017STrevor Wu unsigned int id) 219*ff5a9017STrevor Wu { 220*ff5a9017STrevor Wu const struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); 221*ff5a9017STrevor Wu 222*ff5a9017STrevor Wu if (!cfg) 223*ff5a9017STrevor Wu return -EINVAL; 224*ff5a9017STrevor Wu 225*ff5a9017STrevor Wu regmap_update_bits(afe->regmap, cfg->apll_div_reg, 226*ff5a9017STrevor Wu cfg->apll_div_maskbit << cfg->apll_div_shift, 227*ff5a9017STrevor Wu cfg->apll_div_default << cfg->apll_div_shift); 228*ff5a9017STrevor Wu 229*ff5a9017STrevor Wu regmap_update_bits(afe->regmap, cfg->ref_ck_sel_reg, 230*ff5a9017STrevor Wu cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, 231*ff5a9017STrevor Wu cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); 232*ff5a9017STrevor Wu 233*ff5a9017STrevor Wu regmap_update_bits(afe->regmap, cfg->upper_bound_reg, 234*ff5a9017STrevor Wu cfg->upper_bound_maskbit << cfg->upper_bound_shift, 235*ff5a9017STrevor Wu cfg->upper_bound_default << cfg->upper_bound_shift); 236*ff5a9017STrevor Wu 237*ff5a9017STrevor Wu return 0; 238*ff5a9017STrevor Wu } 239*ff5a9017STrevor Wu 240*ff5a9017STrevor Wu static int mt8195_afe_enable_tuner_clk(struct mtk_base_afe *afe, 241*ff5a9017STrevor Wu unsigned int id) 242*ff5a9017STrevor Wu { 243*ff5a9017STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 244*ff5a9017STrevor Wu 245*ff5a9017STrevor Wu switch (id) { 246*ff5a9017STrevor Wu case MT8195_AUD_PLL1: 247*ff5a9017STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); 248*ff5a9017STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); 249*ff5a9017STrevor Wu break; 250*ff5a9017STrevor Wu case MT8195_AUD_PLL2: 251*ff5a9017STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); 252*ff5a9017STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); 253*ff5a9017STrevor Wu break; 254*ff5a9017STrevor Wu default: 255*ff5a9017STrevor Wu break; 256*ff5a9017STrevor Wu } 257*ff5a9017STrevor Wu 258*ff5a9017STrevor Wu return 0; 259*ff5a9017STrevor Wu } 260*ff5a9017STrevor Wu 261*ff5a9017STrevor Wu static int mt8195_afe_disable_tuner_clk(struct mtk_base_afe *afe, 262*ff5a9017STrevor Wu unsigned int id) 263*ff5a9017STrevor Wu { 264*ff5a9017STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 265*ff5a9017STrevor Wu 266*ff5a9017STrevor Wu switch (id) { 267*ff5a9017STrevor Wu case MT8195_AUD_PLL1: 268*ff5a9017STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL1_TUNER]); 269*ff5a9017STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL]); 270*ff5a9017STrevor Wu break; 271*ff5a9017STrevor Wu case MT8195_AUD_PLL2: 272*ff5a9017STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2_TUNER]); 273*ff5a9017STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[MT8195_CLK_AUD_APLL2]); 274*ff5a9017STrevor Wu break; 275*ff5a9017STrevor Wu default: 276*ff5a9017STrevor Wu break; 277*ff5a9017STrevor Wu } 278*ff5a9017STrevor Wu 279*ff5a9017STrevor Wu return 0; 280*ff5a9017STrevor Wu } 281*ff5a9017STrevor Wu 282*ff5a9017STrevor Wu static int mt8195_afe_enable_apll_tuner(struct mtk_base_afe *afe, 283*ff5a9017STrevor Wu unsigned int id) 284*ff5a9017STrevor Wu { 285*ff5a9017STrevor Wu struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); 286*ff5a9017STrevor Wu unsigned long flags; 287*ff5a9017STrevor Wu int ret = 0; 288*ff5a9017STrevor Wu 289*ff5a9017STrevor Wu if (!cfg) 290*ff5a9017STrevor Wu return -EINVAL; 291*ff5a9017STrevor Wu 292*ff5a9017STrevor Wu ret = mt8195_afe_setup_apll_tuner(afe, id); 293*ff5a9017STrevor Wu if (ret) 294*ff5a9017STrevor Wu return ret; 295*ff5a9017STrevor Wu 296*ff5a9017STrevor Wu ret = mt8195_afe_enable_tuner_clk(afe, id); 297*ff5a9017STrevor Wu if (ret) 298*ff5a9017STrevor Wu return ret; 299*ff5a9017STrevor Wu 300*ff5a9017STrevor Wu spin_lock_irqsave(&cfg->ctrl_lock, flags); 301*ff5a9017STrevor Wu 302*ff5a9017STrevor Wu cfg->ref_cnt++; 303*ff5a9017STrevor Wu if (cfg->ref_cnt == 1) 304*ff5a9017STrevor Wu regmap_update_bits(afe->regmap, 305*ff5a9017STrevor Wu cfg->tuner_en_reg, 306*ff5a9017STrevor Wu cfg->tuner_en_maskbit << cfg->tuner_en_shift, 307*ff5a9017STrevor Wu 1 << cfg->tuner_en_shift); 308*ff5a9017STrevor Wu 309*ff5a9017STrevor Wu spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 310*ff5a9017STrevor Wu 311*ff5a9017STrevor Wu return ret; 312*ff5a9017STrevor Wu } 313*ff5a9017STrevor Wu 314*ff5a9017STrevor Wu static int mt8195_afe_disable_apll_tuner(struct mtk_base_afe *afe, 315*ff5a9017STrevor Wu unsigned int id) 316*ff5a9017STrevor Wu { 317*ff5a9017STrevor Wu struct mt8195_afe_tuner_cfg *cfg = mt8195_afe_found_apll_tuner(id); 318*ff5a9017STrevor Wu unsigned long flags; 319*ff5a9017STrevor Wu int ret = 0; 320*ff5a9017STrevor Wu 321*ff5a9017STrevor Wu if (!cfg) 322*ff5a9017STrevor Wu return -EINVAL; 323*ff5a9017STrevor Wu 324*ff5a9017STrevor Wu spin_lock_irqsave(&cfg->ctrl_lock, flags); 325*ff5a9017STrevor Wu 326*ff5a9017STrevor Wu cfg->ref_cnt--; 327*ff5a9017STrevor Wu if (cfg->ref_cnt == 0) 328*ff5a9017STrevor Wu regmap_update_bits(afe->regmap, 329*ff5a9017STrevor Wu cfg->tuner_en_reg, 330*ff5a9017STrevor Wu cfg->tuner_en_maskbit << cfg->tuner_en_shift, 331*ff5a9017STrevor Wu 0 << cfg->tuner_en_shift); 332*ff5a9017STrevor Wu else if (cfg->ref_cnt < 0) 333*ff5a9017STrevor Wu cfg->ref_cnt = 0; 334*ff5a9017STrevor Wu 335*ff5a9017STrevor Wu spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 336*ff5a9017STrevor Wu 337*ff5a9017STrevor Wu ret = mt8195_afe_disable_tuner_clk(afe, id); 338*ff5a9017STrevor Wu if (ret) 339*ff5a9017STrevor Wu return ret; 340*ff5a9017STrevor Wu 341*ff5a9017STrevor Wu return ret; 342*ff5a9017STrevor Wu } 343*ff5a9017STrevor Wu 3446746cc85STrevor Wu int mt8195_afe_get_mclk_source_clk_id(int sel) 3456746cc85STrevor Wu { 3466746cc85STrevor Wu switch (sel) { 3476746cc85STrevor Wu case MT8195_MCK_SEL_26M: 3486746cc85STrevor Wu return MT8195_CLK_XTAL_26M; 3496746cc85STrevor Wu case MT8195_MCK_SEL_APLL1: 3506746cc85STrevor Wu return MT8195_CLK_TOP_APLL1; 3516746cc85STrevor Wu case MT8195_MCK_SEL_APLL2: 3526746cc85STrevor Wu return MT8195_CLK_TOP_APLL2; 3536746cc85STrevor Wu default: 3546746cc85STrevor Wu return -EINVAL; 3556746cc85STrevor Wu } 3566746cc85STrevor Wu } 3576746cc85STrevor Wu 3586746cc85STrevor Wu int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) 3596746cc85STrevor Wu { 3606746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 3616746cc85STrevor Wu int clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 3626746cc85STrevor Wu 3636746cc85STrevor Wu if (clk_id < 0) { 3646746cc85STrevor Wu dev_dbg(afe->dev, "invalid clk id\n"); 3656746cc85STrevor Wu return 0; 3666746cc85STrevor Wu } 3676746cc85STrevor Wu 3686746cc85STrevor Wu return clk_get_rate(afe_priv->clk[clk_id]); 3696746cc85STrevor Wu } 3706746cc85STrevor Wu 3716746cc85STrevor Wu int mt8195_afe_get_default_mclk_source_by_rate(int rate) 3726746cc85STrevor Wu { 3736746cc85STrevor Wu return ((rate % 8000) == 0) ? 3746746cc85STrevor Wu MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2; 3756746cc85STrevor Wu } 3766746cc85STrevor Wu 3776746cc85STrevor Wu int mt8195_afe_init_clock(struct mtk_base_afe *afe) 3786746cc85STrevor Wu { 3796746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 380*ff5a9017STrevor Wu int i, ret; 3816746cc85STrevor Wu 3826746cc85STrevor Wu mt8195_audsys_clk_register(afe); 3836746cc85STrevor Wu 3846746cc85STrevor Wu afe_priv->clk = 3856746cc85STrevor Wu devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), 3866746cc85STrevor Wu GFP_KERNEL); 3876746cc85STrevor Wu if (!afe_priv->clk) 3886746cc85STrevor Wu return -ENOMEM; 3896746cc85STrevor Wu 3906746cc85STrevor Wu for (i = 0; i < MT8195_CLK_NUM; i++) { 3916746cc85STrevor Wu afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 3926746cc85STrevor Wu if (IS_ERR(afe_priv->clk[i])) { 3936746cc85STrevor Wu dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", 3946746cc85STrevor Wu __func__, aud_clks[i], 3956746cc85STrevor Wu PTR_ERR(afe_priv->clk[i])); 3966746cc85STrevor Wu return PTR_ERR(afe_priv->clk[i]); 3976746cc85STrevor Wu } 3986746cc85STrevor Wu } 3996746cc85STrevor Wu 400*ff5a9017STrevor Wu /* initial tuner */ 401*ff5a9017STrevor Wu for (i = 0; i < MT8195_AUD_PLL_NUM; i++) { 402*ff5a9017STrevor Wu ret = mt8195_afe_init_apll_tuner(i); 403*ff5a9017STrevor Wu if (ret) { 404*ff5a9017STrevor Wu dev_dbg(afe->dev, "%s(), init apll_tuner%d failed", 405*ff5a9017STrevor Wu __func__, (i + 1)); 406*ff5a9017STrevor Wu return -EINVAL; 407*ff5a9017STrevor Wu } 408*ff5a9017STrevor Wu } 409*ff5a9017STrevor Wu 4106746cc85STrevor Wu return 0; 4116746cc85STrevor Wu } 4126746cc85STrevor Wu 4136746cc85STrevor Wu void mt8195_afe_deinit_clock(struct mtk_base_afe *afe) 4146746cc85STrevor Wu { 4156746cc85STrevor Wu mt8195_audsys_clk_unregister(afe); 4166746cc85STrevor Wu } 4176746cc85STrevor Wu 4186746cc85STrevor Wu int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) 4196746cc85STrevor Wu { 4206746cc85STrevor Wu int ret; 4216746cc85STrevor Wu 4226746cc85STrevor Wu if (clk) { 4236746cc85STrevor Wu ret = clk_prepare_enable(clk); 4246746cc85STrevor Wu if (ret) { 4256746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to enable clk\n", 4266746cc85STrevor Wu __func__); 4276746cc85STrevor Wu return ret; 4286746cc85STrevor Wu } 4296746cc85STrevor Wu } else { 4306746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4316746cc85STrevor Wu } 4326746cc85STrevor Wu return 0; 4336746cc85STrevor Wu } 4346746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk); 4356746cc85STrevor Wu 4366746cc85STrevor Wu void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) 4376746cc85STrevor Wu { 4386746cc85STrevor Wu if (clk) 4396746cc85STrevor Wu clk_disable_unprepare(clk); 4406746cc85STrevor Wu else 4416746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4426746cc85STrevor Wu } 4436746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk); 4446746cc85STrevor Wu 4456746cc85STrevor Wu int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk) 4466746cc85STrevor Wu { 4476746cc85STrevor Wu int ret; 4486746cc85STrevor Wu 4496746cc85STrevor Wu if (clk) { 4506746cc85STrevor Wu ret = clk_prepare(clk); 4516746cc85STrevor Wu if (ret) { 4526746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to prepare clk\n", 4536746cc85STrevor Wu __func__); 4546746cc85STrevor Wu return ret; 4556746cc85STrevor Wu } 4566746cc85STrevor Wu } else { 4576746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4586746cc85STrevor Wu } 4596746cc85STrevor Wu return 0; 4606746cc85STrevor Wu } 4616746cc85STrevor Wu 4626746cc85STrevor Wu void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk) 4636746cc85STrevor Wu { 4646746cc85STrevor Wu if (clk) 4656746cc85STrevor Wu clk_unprepare(clk); 4666746cc85STrevor Wu else 4676746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4686746cc85STrevor Wu } 4696746cc85STrevor Wu 4706746cc85STrevor Wu int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 4716746cc85STrevor Wu { 4726746cc85STrevor Wu int ret; 4736746cc85STrevor Wu 4746746cc85STrevor Wu if (clk) { 4756746cc85STrevor Wu ret = clk_enable(clk); 4766746cc85STrevor Wu if (ret) { 4776746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to clk enable\n", 4786746cc85STrevor Wu __func__); 4796746cc85STrevor Wu return ret; 4806746cc85STrevor Wu } 4816746cc85STrevor Wu } else { 4826746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4836746cc85STrevor Wu } 4846746cc85STrevor Wu return 0; 4856746cc85STrevor Wu } 4866746cc85STrevor Wu 4876746cc85STrevor Wu void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 4886746cc85STrevor Wu { 4896746cc85STrevor Wu if (clk) 4906746cc85STrevor Wu clk_disable(clk); 4916746cc85STrevor Wu else 4926746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 4936746cc85STrevor Wu } 4946746cc85STrevor Wu 4956746cc85STrevor Wu int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 4966746cc85STrevor Wu unsigned int rate) 4976746cc85STrevor Wu { 4986746cc85STrevor Wu int ret; 4996746cc85STrevor Wu 5006746cc85STrevor Wu if (clk) { 5016746cc85STrevor Wu ret = clk_set_rate(clk, rate); 5026746cc85STrevor Wu if (ret) { 5036746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk rate\n", 5046746cc85STrevor Wu __func__); 5056746cc85STrevor Wu return ret; 5066746cc85STrevor Wu } 5076746cc85STrevor Wu } 5086746cc85STrevor Wu 5096746cc85STrevor Wu return 0; 5106746cc85STrevor Wu } 5116746cc85STrevor Wu 5126746cc85STrevor Wu int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 5136746cc85STrevor Wu struct clk *parent) 5146746cc85STrevor Wu { 5156746cc85STrevor Wu int ret; 5166746cc85STrevor Wu 5176746cc85STrevor Wu if (clk && parent) { 5186746cc85STrevor Wu ret = clk_set_parent(clk, parent); 5196746cc85STrevor Wu if (ret) { 5206746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk parent\n", 5216746cc85STrevor Wu __func__); 5226746cc85STrevor Wu return ret; 5236746cc85STrevor Wu } 5246746cc85STrevor Wu } 5256746cc85STrevor Wu 5266746cc85STrevor Wu return 0; 5276746cc85STrevor Wu } 5286746cc85STrevor Wu 5296746cc85STrevor Wu static unsigned int get_top_cg_reg(unsigned int cg_type) 5306746cc85STrevor Wu { 5316746cc85STrevor Wu switch (cg_type) { 5326746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 5336746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 5346746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 5356746cc85STrevor Wu return ASYS_TOP_CON; 5366746cc85STrevor Wu default: 5376746cc85STrevor Wu return 0; 5386746cc85STrevor Wu } 5396746cc85STrevor Wu } 5406746cc85STrevor Wu 5416746cc85STrevor Wu static unsigned int get_top_cg_mask(unsigned int cg_type) 5426746cc85STrevor Wu { 5436746cc85STrevor Wu switch (cg_type) { 5446746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 5456746cc85STrevor Wu return ASYS_TOP_CON_A1SYS_TIMING_ON; 5466746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 5476746cc85STrevor Wu return ASYS_TOP_CON_A2SYS_TIMING_ON; 5486746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 5496746cc85STrevor Wu return ASYS_TOP_CON_26M_TIMING_ON; 5506746cc85STrevor Wu default: 5516746cc85STrevor Wu return 0; 5526746cc85STrevor Wu } 5536746cc85STrevor Wu } 5546746cc85STrevor Wu 5556746cc85STrevor Wu static unsigned int get_top_cg_on_val(unsigned int cg_type) 5566746cc85STrevor Wu { 5576746cc85STrevor Wu switch (cg_type) { 5586746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 5596746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 5606746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 5616746cc85STrevor Wu return get_top_cg_mask(cg_type); 5626746cc85STrevor Wu default: 5636746cc85STrevor Wu return 0; 5646746cc85STrevor Wu } 5656746cc85STrevor Wu } 5666746cc85STrevor Wu 5676746cc85STrevor Wu static unsigned int get_top_cg_off_val(unsigned int cg_type) 5686746cc85STrevor Wu { 5696746cc85STrevor Wu switch (cg_type) { 5706746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 5716746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 5726746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 5736746cc85STrevor Wu return 0; 5746746cc85STrevor Wu default: 5756746cc85STrevor Wu return get_top_cg_mask(cg_type); 5766746cc85STrevor Wu } 5776746cc85STrevor Wu } 5786746cc85STrevor Wu 5796746cc85STrevor Wu static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 5806746cc85STrevor Wu { 5816746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 5826746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 5836746cc85STrevor Wu unsigned int val = get_top_cg_on_val(cg_type); 5846746cc85STrevor Wu 5856746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 5866746cc85STrevor Wu return 0; 5876746cc85STrevor Wu } 5886746cc85STrevor Wu 5896746cc85STrevor Wu static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 5906746cc85STrevor Wu { 5916746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 5926746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 5936746cc85STrevor Wu unsigned int val = get_top_cg_off_val(cg_type); 5946746cc85STrevor Wu 5956746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 5966746cc85STrevor Wu return 0; 5976746cc85STrevor Wu } 5986746cc85STrevor Wu 5996746cc85STrevor Wu int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) 6006746cc85STrevor Wu { 6016746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6026746cc85STrevor Wu int i; 60391745b03SColin Ian King static const unsigned int clk_array[] = { 6046746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */ 6056746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */ 6066746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */ 6076746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */ 6086746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */ 6096746cc85STrevor Wu MT8195_CLK_AUD_AFE, /* AFE HW master switch */ 6106746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/ 6116746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, /* AFE HW clock */ 6126746cc85STrevor Wu }; 6136746cc85STrevor Wu 6146746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 6156746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 6166746cc85STrevor Wu 6176746cc85STrevor Wu return 0; 6186746cc85STrevor Wu } 6196746cc85STrevor Wu 6206746cc85STrevor Wu int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) 6216746cc85STrevor Wu { 6226746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6236746cc85STrevor Wu int i; 62491745b03SColin Ian King static const unsigned int clk_array[] = { 6256746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 6266746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, 6276746cc85STrevor Wu MT8195_CLK_AUD_AFE, 6286746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, 6296746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, 6306746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 6316746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, 6326746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, 6336746cc85STrevor Wu }; 6346746cc85STrevor Wu 6356746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 6366746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 6376746cc85STrevor Wu 6386746cc85STrevor Wu return 0; 6396746cc85STrevor Wu } 6406746cc85STrevor Wu 6416746cc85STrevor Wu static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe) 6426746cc85STrevor Wu { 6436746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 6446746cc85STrevor Wu return 0; 6456746cc85STrevor Wu } 6466746cc85STrevor Wu 6476746cc85STrevor Wu static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe) 6486746cc85STrevor Wu { 6496746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 6506746cc85STrevor Wu return 0; 6516746cc85STrevor Wu } 6526746cc85STrevor Wu 6536746cc85STrevor Wu static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe) 6546746cc85STrevor Wu { 6556746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6566746cc85STrevor Wu int i; 65791745b03SColin Ian King static const unsigned int clk_array[] = { 6586746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 6596746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 6606746cc85STrevor Wu }; 66191745b03SColin Ian King static const unsigned int cg_array[] = { 6626746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 6636746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 6646746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 6656746cc85STrevor Wu }; 6666746cc85STrevor Wu 6676746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 6686746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 6696746cc85STrevor Wu 6706746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 6716746cc85STrevor Wu mt8195_afe_enable_top_cg(afe, cg_array[i]); 6726746cc85STrevor Wu 6736746cc85STrevor Wu return 0; 6746746cc85STrevor Wu } 6756746cc85STrevor Wu 6766746cc85STrevor Wu static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe) 6776746cc85STrevor Wu { 6786746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 6796746cc85STrevor Wu int i; 68091745b03SColin Ian King static const unsigned int clk_array[] = { 6816746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 6826746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 6836746cc85STrevor Wu }; 68491745b03SColin Ian King static const unsigned int cg_array[] = { 6856746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 6866746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 6876746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 6886746cc85STrevor Wu }; 6896746cc85STrevor Wu 6906746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 6916746cc85STrevor Wu mt8195_afe_disable_top_cg(afe, cg_array[i]); 6926746cc85STrevor Wu 6936746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 6946746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 6956746cc85STrevor Wu 6966746cc85STrevor Wu return 0; 6976746cc85STrevor Wu } 6986746cc85STrevor Wu 6996746cc85STrevor Wu int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) 7006746cc85STrevor Wu { 7016746cc85STrevor Wu mt8195_afe_enable_timing_sys(afe); 7026746cc85STrevor Wu 7036746cc85STrevor Wu mt8195_afe_enable_afe_on(afe); 7046746cc85STrevor Wu 705*ff5a9017STrevor Wu mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL1); 706*ff5a9017STrevor Wu mt8195_afe_enable_apll_tuner(afe, MT8195_AUD_PLL2); 707*ff5a9017STrevor Wu 7086746cc85STrevor Wu return 0; 7096746cc85STrevor Wu } 7106746cc85STrevor Wu 7116746cc85STrevor Wu int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) 7126746cc85STrevor Wu { 713*ff5a9017STrevor Wu mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL2); 714*ff5a9017STrevor Wu mt8195_afe_disable_apll_tuner(afe, MT8195_AUD_PLL1); 715*ff5a9017STrevor Wu 7166746cc85STrevor Wu mt8195_afe_disable_afe_on(afe); 7176746cc85STrevor Wu 7186746cc85STrevor Wu mt8195_afe_disable_timing_sys(afe); 7196746cc85STrevor Wu 7206746cc85STrevor Wu return 0; 7216746cc85STrevor Wu } 722