1*6746cc85STrevor Wu // SPDX-License-Identifier: GPL-2.0 2*6746cc85STrevor Wu /* 3*6746cc85STrevor Wu * mt8195-afe-clk.c -- Mediatek 8195 afe clock ctrl 4*6746cc85STrevor Wu * 5*6746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 6*6746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*6746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*6746cc85STrevor Wu */ 9*6746cc85STrevor Wu 10*6746cc85STrevor Wu #include <linux/clk.h> 11*6746cc85STrevor Wu 12*6746cc85STrevor Wu #include "mt8195-afe-common.h" 13*6746cc85STrevor Wu #include "mt8195-afe-clk.h" 14*6746cc85STrevor Wu #include "mt8195-reg.h" 15*6746cc85STrevor Wu #include "mt8195-audsys-clk.h" 16*6746cc85STrevor Wu 17*6746cc85STrevor Wu static const char *aud_clks[MT8195_CLK_NUM] = { 18*6746cc85STrevor Wu /* xtal */ 19*6746cc85STrevor Wu [MT8195_CLK_XTAL_26M] = "clk26m", 20*6746cc85STrevor Wu /* divider */ 21*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL1] = "apll1_ck", 22*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL2] = "apll2_ck", 23*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV0] = "apll12_div0", 24*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV1] = "apll12_div1", 25*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV2] = "apll12_div2", 26*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV3] = "apll12_div3", 27*6746cc85STrevor Wu [MT8195_CLK_TOP_APLL12_DIV9] = "apll12_div9", 28*6746cc85STrevor Wu /* mux */ 29*6746cc85STrevor Wu [MT8195_CLK_TOP_A1SYS_HP_SEL] = "a1sys_hp_sel", 30*6746cc85STrevor Wu [MT8195_CLK_TOP_AUD_INTBUS_SEL] = "aud_intbus_sel", 31*6746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_H_SEL] = "audio_h_sel", 32*6746cc85STrevor Wu [MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "audio_local_bus_sel", 33*6746cc85STrevor Wu [MT8195_CLK_TOP_DPTX_M_SEL] = "dptx_m_sel", 34*6746cc85STrevor Wu [MT8195_CLK_TOP_I2SO1_M_SEL] = "i2so1_m_sel", 35*6746cc85STrevor Wu [MT8195_CLK_TOP_I2SO2_M_SEL] = "i2so2_m_sel", 36*6746cc85STrevor Wu [MT8195_CLK_TOP_I2SI1_M_SEL] = "i2si1_m_sel", 37*6746cc85STrevor Wu [MT8195_CLK_TOP_I2SI2_M_SEL] = "i2si2_m_sel", 38*6746cc85STrevor Wu /* clock gate */ 39*6746cc85STrevor Wu [MT8195_CLK_INFRA_AO_AUDIO_26M_B] = "infra_ao_audio_26m_b", 40*6746cc85STrevor Wu [MT8195_CLK_SCP_ADSP_AUDIODSP] = "scp_adsp_audiodsp", 41*6746cc85STrevor Wu /* afe clock gate */ 42*6746cc85STrevor Wu [MT8195_CLK_AUD_AFE] = "aud_afe", 43*6746cc85STrevor Wu [MT8195_CLK_AUD_APLL] = "aud_apll", 44*6746cc85STrevor Wu [MT8195_CLK_AUD_APLL2] = "aud_apll2", 45*6746cc85STrevor Wu [MT8195_CLK_AUD_DAC] = "aud_dac", 46*6746cc85STrevor Wu [MT8195_CLK_AUD_ADC] = "aud_adc", 47*6746cc85STrevor Wu [MT8195_CLK_AUD_DAC_HIRES] = "aud_dac_hires", 48*6746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", 49*6746cc85STrevor Wu [MT8195_CLK_AUD_ADC_HIRES] = "aud_adc_hires", 50*6746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC] = "aud_adda6_adc", 51*6746cc85STrevor Wu [MT8195_CLK_AUD_ADDA6_ADC_HIRES] = "aud_adda6_adc_hires", 52*6746cc85STrevor Wu [MT8195_CLK_AUD_I2SIN] = "aud_i2sin", 53*6746cc85STrevor Wu [MT8195_CLK_AUD_TDM_IN] = "aud_tdm_in", 54*6746cc85STrevor Wu [MT8195_CLK_AUD_I2S_OUT] = "aud_i2s_out", 55*6746cc85STrevor Wu [MT8195_CLK_AUD_TDM_OUT] = "aud_tdm_out", 56*6746cc85STrevor Wu [MT8195_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", 57*6746cc85STrevor Wu [MT8195_CLK_AUD_ASRC11] = "aud_asrc11", 58*6746cc85STrevor Wu [MT8195_CLK_AUD_ASRC12] = "aud_asrc12", 59*6746cc85STrevor Wu [MT8195_CLK_AUD_A1SYS] = "aud_a1sys", 60*6746cc85STrevor Wu [MT8195_CLK_AUD_A2SYS] = "aud_a2sys", 61*6746cc85STrevor Wu [MT8195_CLK_AUD_PCMIF] = "aud_pcmif", 62*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", 63*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", 64*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", 65*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", 66*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", 67*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", 68*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", 69*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", 70*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", 71*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", 72*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", 73*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", 74*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", 75*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", 76*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", 77*6746cc85STrevor Wu [MT8195_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", 78*6746cc85STrevor Wu }; 79*6746cc85STrevor Wu 80*6746cc85STrevor Wu int mt8195_afe_get_mclk_source_clk_id(int sel) 81*6746cc85STrevor Wu { 82*6746cc85STrevor Wu switch (sel) { 83*6746cc85STrevor Wu case MT8195_MCK_SEL_26M: 84*6746cc85STrevor Wu return MT8195_CLK_XTAL_26M; 85*6746cc85STrevor Wu case MT8195_MCK_SEL_APLL1: 86*6746cc85STrevor Wu return MT8195_CLK_TOP_APLL1; 87*6746cc85STrevor Wu case MT8195_MCK_SEL_APLL2: 88*6746cc85STrevor Wu return MT8195_CLK_TOP_APLL2; 89*6746cc85STrevor Wu default: 90*6746cc85STrevor Wu return -EINVAL; 91*6746cc85STrevor Wu } 92*6746cc85STrevor Wu } 93*6746cc85STrevor Wu 94*6746cc85STrevor Wu int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) 95*6746cc85STrevor Wu { 96*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 97*6746cc85STrevor Wu int clk_id = mt8195_afe_get_mclk_source_clk_id(apll); 98*6746cc85STrevor Wu 99*6746cc85STrevor Wu if (clk_id < 0) { 100*6746cc85STrevor Wu dev_dbg(afe->dev, "invalid clk id\n"); 101*6746cc85STrevor Wu return 0; 102*6746cc85STrevor Wu } 103*6746cc85STrevor Wu 104*6746cc85STrevor Wu return clk_get_rate(afe_priv->clk[clk_id]); 105*6746cc85STrevor Wu } 106*6746cc85STrevor Wu 107*6746cc85STrevor Wu int mt8195_afe_get_default_mclk_source_by_rate(int rate) 108*6746cc85STrevor Wu { 109*6746cc85STrevor Wu return ((rate % 8000) == 0) ? 110*6746cc85STrevor Wu MT8195_MCK_SEL_APLL1 : MT8195_MCK_SEL_APLL2; 111*6746cc85STrevor Wu } 112*6746cc85STrevor Wu 113*6746cc85STrevor Wu int mt8195_afe_init_clock(struct mtk_base_afe *afe) 114*6746cc85STrevor Wu { 115*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 116*6746cc85STrevor Wu int i; 117*6746cc85STrevor Wu 118*6746cc85STrevor Wu mt8195_audsys_clk_register(afe); 119*6746cc85STrevor Wu 120*6746cc85STrevor Wu afe_priv->clk = 121*6746cc85STrevor Wu devm_kcalloc(afe->dev, MT8195_CLK_NUM, sizeof(*afe_priv->clk), 122*6746cc85STrevor Wu GFP_KERNEL); 123*6746cc85STrevor Wu if (!afe_priv->clk) 124*6746cc85STrevor Wu return -ENOMEM; 125*6746cc85STrevor Wu 126*6746cc85STrevor Wu for (i = 0; i < MT8195_CLK_NUM; i++) { 127*6746cc85STrevor Wu afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 128*6746cc85STrevor Wu if (IS_ERR(afe_priv->clk[i])) { 129*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", 130*6746cc85STrevor Wu __func__, aud_clks[i], 131*6746cc85STrevor Wu PTR_ERR(afe_priv->clk[i])); 132*6746cc85STrevor Wu return PTR_ERR(afe_priv->clk[i]); 133*6746cc85STrevor Wu } 134*6746cc85STrevor Wu } 135*6746cc85STrevor Wu 136*6746cc85STrevor Wu return 0; 137*6746cc85STrevor Wu } 138*6746cc85STrevor Wu 139*6746cc85STrevor Wu void mt8195_afe_deinit_clock(struct mtk_base_afe *afe) 140*6746cc85STrevor Wu { 141*6746cc85STrevor Wu mt8195_audsys_clk_unregister(afe); 142*6746cc85STrevor Wu } 143*6746cc85STrevor Wu 144*6746cc85STrevor Wu int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) 145*6746cc85STrevor Wu { 146*6746cc85STrevor Wu int ret; 147*6746cc85STrevor Wu 148*6746cc85STrevor Wu if (clk) { 149*6746cc85STrevor Wu ret = clk_prepare_enable(clk); 150*6746cc85STrevor Wu if (ret) { 151*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to enable clk\n", 152*6746cc85STrevor Wu __func__); 153*6746cc85STrevor Wu return ret; 154*6746cc85STrevor Wu } 155*6746cc85STrevor Wu } else { 156*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 157*6746cc85STrevor Wu } 158*6746cc85STrevor Wu return 0; 159*6746cc85STrevor Wu } 160*6746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_enable_clk); 161*6746cc85STrevor Wu 162*6746cc85STrevor Wu void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) 163*6746cc85STrevor Wu { 164*6746cc85STrevor Wu if (clk) 165*6746cc85STrevor Wu clk_disable_unprepare(clk); 166*6746cc85STrevor Wu else 167*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 168*6746cc85STrevor Wu } 169*6746cc85STrevor Wu EXPORT_SYMBOL_GPL(mt8195_afe_disable_clk); 170*6746cc85STrevor Wu 171*6746cc85STrevor Wu int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk) 172*6746cc85STrevor Wu { 173*6746cc85STrevor Wu int ret; 174*6746cc85STrevor Wu 175*6746cc85STrevor Wu if (clk) { 176*6746cc85STrevor Wu ret = clk_prepare(clk); 177*6746cc85STrevor Wu if (ret) { 178*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to prepare clk\n", 179*6746cc85STrevor Wu __func__); 180*6746cc85STrevor Wu return ret; 181*6746cc85STrevor Wu } 182*6746cc85STrevor Wu } else { 183*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 184*6746cc85STrevor Wu } 185*6746cc85STrevor Wu return 0; 186*6746cc85STrevor Wu } 187*6746cc85STrevor Wu 188*6746cc85STrevor Wu void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk) 189*6746cc85STrevor Wu { 190*6746cc85STrevor Wu if (clk) 191*6746cc85STrevor Wu clk_unprepare(clk); 192*6746cc85STrevor Wu else 193*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 194*6746cc85STrevor Wu } 195*6746cc85STrevor Wu 196*6746cc85STrevor Wu int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 197*6746cc85STrevor Wu { 198*6746cc85STrevor Wu int ret; 199*6746cc85STrevor Wu 200*6746cc85STrevor Wu if (clk) { 201*6746cc85STrevor Wu ret = clk_enable(clk); 202*6746cc85STrevor Wu if (ret) { 203*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to clk enable\n", 204*6746cc85STrevor Wu __func__); 205*6746cc85STrevor Wu return ret; 206*6746cc85STrevor Wu } 207*6746cc85STrevor Wu } else { 208*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 209*6746cc85STrevor Wu } 210*6746cc85STrevor Wu return 0; 211*6746cc85STrevor Wu } 212*6746cc85STrevor Wu 213*6746cc85STrevor Wu void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk) 214*6746cc85STrevor Wu { 215*6746cc85STrevor Wu if (clk) 216*6746cc85STrevor Wu clk_disable(clk); 217*6746cc85STrevor Wu else 218*6746cc85STrevor Wu dev_dbg(afe->dev, "NULL clk\n"); 219*6746cc85STrevor Wu } 220*6746cc85STrevor Wu 221*6746cc85STrevor Wu int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 222*6746cc85STrevor Wu unsigned int rate) 223*6746cc85STrevor Wu { 224*6746cc85STrevor Wu int ret; 225*6746cc85STrevor Wu 226*6746cc85STrevor Wu if (clk) { 227*6746cc85STrevor Wu ret = clk_set_rate(clk, rate); 228*6746cc85STrevor Wu if (ret) { 229*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk rate\n", 230*6746cc85STrevor Wu __func__); 231*6746cc85STrevor Wu return ret; 232*6746cc85STrevor Wu } 233*6746cc85STrevor Wu } 234*6746cc85STrevor Wu 235*6746cc85STrevor Wu return 0; 236*6746cc85STrevor Wu } 237*6746cc85STrevor Wu 238*6746cc85STrevor Wu int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 239*6746cc85STrevor Wu struct clk *parent) 240*6746cc85STrevor Wu { 241*6746cc85STrevor Wu int ret; 242*6746cc85STrevor Wu 243*6746cc85STrevor Wu if (clk && parent) { 244*6746cc85STrevor Wu ret = clk_set_parent(clk, parent); 245*6746cc85STrevor Wu if (ret) { 246*6746cc85STrevor Wu dev_dbg(afe->dev, "%s(), failed to set clk parent\n", 247*6746cc85STrevor Wu __func__); 248*6746cc85STrevor Wu return ret; 249*6746cc85STrevor Wu } 250*6746cc85STrevor Wu } 251*6746cc85STrevor Wu 252*6746cc85STrevor Wu return 0; 253*6746cc85STrevor Wu } 254*6746cc85STrevor Wu 255*6746cc85STrevor Wu static unsigned int get_top_cg_reg(unsigned int cg_type) 256*6746cc85STrevor Wu { 257*6746cc85STrevor Wu switch (cg_type) { 258*6746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 259*6746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 260*6746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 261*6746cc85STrevor Wu return ASYS_TOP_CON; 262*6746cc85STrevor Wu default: 263*6746cc85STrevor Wu return 0; 264*6746cc85STrevor Wu } 265*6746cc85STrevor Wu } 266*6746cc85STrevor Wu 267*6746cc85STrevor Wu static unsigned int get_top_cg_mask(unsigned int cg_type) 268*6746cc85STrevor Wu { 269*6746cc85STrevor Wu switch (cg_type) { 270*6746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 271*6746cc85STrevor Wu return ASYS_TOP_CON_A1SYS_TIMING_ON; 272*6746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 273*6746cc85STrevor Wu return ASYS_TOP_CON_A2SYS_TIMING_ON; 274*6746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 275*6746cc85STrevor Wu return ASYS_TOP_CON_26M_TIMING_ON; 276*6746cc85STrevor Wu default: 277*6746cc85STrevor Wu return 0; 278*6746cc85STrevor Wu } 279*6746cc85STrevor Wu } 280*6746cc85STrevor Wu 281*6746cc85STrevor Wu static unsigned int get_top_cg_on_val(unsigned int cg_type) 282*6746cc85STrevor Wu { 283*6746cc85STrevor Wu switch (cg_type) { 284*6746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 285*6746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 286*6746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 287*6746cc85STrevor Wu return get_top_cg_mask(cg_type); 288*6746cc85STrevor Wu default: 289*6746cc85STrevor Wu return 0; 290*6746cc85STrevor Wu } 291*6746cc85STrevor Wu } 292*6746cc85STrevor Wu 293*6746cc85STrevor Wu static unsigned int get_top_cg_off_val(unsigned int cg_type) 294*6746cc85STrevor Wu { 295*6746cc85STrevor Wu switch (cg_type) { 296*6746cc85STrevor Wu case MT8195_TOP_CG_A1SYS_TIMING: 297*6746cc85STrevor Wu case MT8195_TOP_CG_A2SYS_TIMING: 298*6746cc85STrevor Wu case MT8195_TOP_CG_26M_TIMING: 299*6746cc85STrevor Wu return 0; 300*6746cc85STrevor Wu default: 301*6746cc85STrevor Wu return get_top_cg_mask(cg_type); 302*6746cc85STrevor Wu } 303*6746cc85STrevor Wu } 304*6746cc85STrevor Wu 305*6746cc85STrevor Wu static int mt8195_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 306*6746cc85STrevor Wu { 307*6746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 308*6746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 309*6746cc85STrevor Wu unsigned int val = get_top_cg_on_val(cg_type); 310*6746cc85STrevor Wu 311*6746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 312*6746cc85STrevor Wu return 0; 313*6746cc85STrevor Wu } 314*6746cc85STrevor Wu 315*6746cc85STrevor Wu static int mt8195_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 316*6746cc85STrevor Wu { 317*6746cc85STrevor Wu unsigned int reg = get_top_cg_reg(cg_type); 318*6746cc85STrevor Wu unsigned int mask = get_top_cg_mask(cg_type); 319*6746cc85STrevor Wu unsigned int val = get_top_cg_off_val(cg_type); 320*6746cc85STrevor Wu 321*6746cc85STrevor Wu regmap_update_bits(afe->regmap, reg, mask, val); 322*6746cc85STrevor Wu return 0; 323*6746cc85STrevor Wu } 324*6746cc85STrevor Wu 325*6746cc85STrevor Wu int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) 326*6746cc85STrevor Wu { 327*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 328*6746cc85STrevor Wu int i; 329*6746cc85STrevor Wu unsigned int clk_array[] = { 330*6746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, /* bus clock for infra */ 331*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, /* clock for ADSP bus */ 332*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, /* bus clock for DRAM access */ 333*6746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, /* bus clock for AFE SRAM access */ 334*6746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, /* audio 26M clock */ 335*6746cc85STrevor Wu MT8195_CLK_AUD_AFE, /* AFE HW master switch */ 336*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, /* AFE HW clock*/ 337*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, /* AFE HW clock */ 338*6746cc85STrevor Wu }; 339*6746cc85STrevor Wu 340*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 341*6746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 342*6746cc85STrevor Wu 343*6746cc85STrevor Wu return 0; 344*6746cc85STrevor Wu } 345*6746cc85STrevor Wu 346*6746cc85STrevor Wu int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) 347*6746cc85STrevor Wu { 348*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 349*6746cc85STrevor Wu int i; 350*6746cc85STrevor Wu unsigned int clk_array[] = { 351*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 352*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, 353*6746cc85STrevor Wu MT8195_CLK_AUD_AFE, 354*6746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, 355*6746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, 356*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 357*6746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, 358*6746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, 359*6746cc85STrevor Wu }; 360*6746cc85STrevor Wu 361*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 362*6746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 363*6746cc85STrevor Wu 364*6746cc85STrevor Wu return 0; 365*6746cc85STrevor Wu } 366*6746cc85STrevor Wu 367*6746cc85STrevor Wu static int mt8195_afe_enable_afe_on(struct mtk_base_afe *afe) 368*6746cc85STrevor Wu { 369*6746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 370*6746cc85STrevor Wu return 0; 371*6746cc85STrevor Wu } 372*6746cc85STrevor Wu 373*6746cc85STrevor Wu static int mt8195_afe_disable_afe_on(struct mtk_base_afe *afe) 374*6746cc85STrevor Wu { 375*6746cc85STrevor Wu regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 376*6746cc85STrevor Wu return 0; 377*6746cc85STrevor Wu } 378*6746cc85STrevor Wu 379*6746cc85STrevor Wu static int mt8195_afe_enable_timing_sys(struct mtk_base_afe *afe) 380*6746cc85STrevor Wu { 381*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 382*6746cc85STrevor Wu int i; 383*6746cc85STrevor Wu unsigned int clk_array[] = { 384*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 385*6746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 386*6746cc85STrevor Wu }; 387*6746cc85STrevor Wu unsigned int cg_array[] = { 388*6746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 389*6746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 390*6746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 391*6746cc85STrevor Wu }; 392*6746cc85STrevor Wu 393*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 394*6746cc85STrevor Wu mt8195_afe_enable_clk(afe, afe_priv->clk[clk_array[i]]); 395*6746cc85STrevor Wu 396*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 397*6746cc85STrevor Wu mt8195_afe_enable_top_cg(afe, cg_array[i]); 398*6746cc85STrevor Wu 399*6746cc85STrevor Wu return 0; 400*6746cc85STrevor Wu } 401*6746cc85STrevor Wu 402*6746cc85STrevor Wu static int mt8195_afe_disable_timing_sys(struct mtk_base_afe *afe) 403*6746cc85STrevor Wu { 404*6746cc85STrevor Wu struct mt8195_afe_private *afe_priv = afe->platform_priv; 405*6746cc85STrevor Wu int i; 406*6746cc85STrevor Wu unsigned int clk_array[] = { 407*6746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 408*6746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 409*6746cc85STrevor Wu }; 410*6746cc85STrevor Wu unsigned int cg_array[] = { 411*6746cc85STrevor Wu MT8195_TOP_CG_26M_TIMING, 412*6746cc85STrevor Wu MT8195_TOP_CG_A2SYS_TIMING, 413*6746cc85STrevor Wu MT8195_TOP_CG_A1SYS_TIMING, 414*6746cc85STrevor Wu }; 415*6746cc85STrevor Wu 416*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(cg_array); i++) 417*6746cc85STrevor Wu mt8195_afe_disable_top_cg(afe, cg_array[i]); 418*6746cc85STrevor Wu 419*6746cc85STrevor Wu for (i = 0; i < ARRAY_SIZE(clk_array); i++) 420*6746cc85STrevor Wu mt8195_afe_disable_clk(afe, afe_priv->clk[clk_array[i]]); 421*6746cc85STrevor Wu 422*6746cc85STrevor Wu return 0; 423*6746cc85STrevor Wu } 424*6746cc85STrevor Wu 425*6746cc85STrevor Wu int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe) 426*6746cc85STrevor Wu { 427*6746cc85STrevor Wu mt8195_afe_enable_timing_sys(afe); 428*6746cc85STrevor Wu 429*6746cc85STrevor Wu mt8195_afe_enable_afe_on(afe); 430*6746cc85STrevor Wu 431*6746cc85STrevor Wu return 0; 432*6746cc85STrevor Wu } 433*6746cc85STrevor Wu 434*6746cc85STrevor Wu int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe) 435*6746cc85STrevor Wu { 436*6746cc85STrevor Wu mt8195_afe_disable_afe_on(afe); 437*6746cc85STrevor Wu 438*6746cc85STrevor Wu mt8195_afe_disable_timing_sys(afe); 439*6746cc85STrevor Wu 440*6746cc85STrevor Wu return 0; 441*6746cc85STrevor Wu } 442