1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI ADDA Control 4 // 5 // Copyright (c) 2020 MediaTek Inc. 6 // Author: Shane Chien <shane.chien@mediatek.com> 7 // 8 9 #include <linux/delay.h> 10 #include <linux/regmap.h> 11 12 #include "mt8192-afe-clk.h" 13 #include "mt8192-afe-common.h" 14 #include "mt8192-afe-gpio.h" 15 #include "mt8192-interconnection.h" 16 17 enum { 18 UL_IIR_SW = 0, 19 UL_IIR_5HZ, 20 UL_IIR_10HZ, 21 UL_IIR_25HZ, 22 UL_IIR_50HZ, 23 UL_IIR_75HZ, 24 }; 25 26 enum { 27 AUDIO_SDM_LEVEL_MUTE = 0, 28 AUDIO_SDM_LEVEL_NORMAL = 0x1d, 29 /* if you change level normal */ 30 /* you need to change formula of hp impedance and dc trim too */ 31 }; 32 33 enum { 34 AUDIO_SDM_2ND = 0, 35 AUDIO_SDM_3RD, 36 }; 37 38 enum { 39 DELAY_DATA_MISO1 = 0, 40 DELAY_DATA_MISO2, 41 }; 42 43 enum { 44 MTK_AFE_ADDA_DL_RATE_8K = 0, 45 MTK_AFE_ADDA_DL_RATE_11K = 1, 46 MTK_AFE_ADDA_DL_RATE_12K = 2, 47 MTK_AFE_ADDA_DL_RATE_16K = 3, 48 MTK_AFE_ADDA_DL_RATE_22K = 4, 49 MTK_AFE_ADDA_DL_RATE_24K = 5, 50 MTK_AFE_ADDA_DL_RATE_32K = 6, 51 MTK_AFE_ADDA_DL_RATE_44K = 7, 52 MTK_AFE_ADDA_DL_RATE_48K = 8, 53 MTK_AFE_ADDA_DL_RATE_96K = 9, 54 MTK_AFE_ADDA_DL_RATE_192K = 10, 55 }; 56 57 enum { 58 MTK_AFE_ADDA_UL_RATE_8K = 0, 59 MTK_AFE_ADDA_UL_RATE_16K = 1, 60 MTK_AFE_ADDA_UL_RATE_32K = 2, 61 MTK_AFE_ADDA_UL_RATE_48K = 3, 62 MTK_AFE_ADDA_UL_RATE_96K = 4, 63 MTK_AFE_ADDA_UL_RATE_192K = 5, 64 MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 65 }; 66 67 #define SDM_AUTO_RESET_THRESHOLD 0x190000 68 69 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 70 unsigned int rate) 71 { 72 switch (rate) { 73 case 8000: 74 return MTK_AFE_ADDA_DL_RATE_8K; 75 case 11025: 76 return MTK_AFE_ADDA_DL_RATE_11K; 77 case 12000: 78 return MTK_AFE_ADDA_DL_RATE_12K; 79 case 16000: 80 return MTK_AFE_ADDA_DL_RATE_16K; 81 case 22050: 82 return MTK_AFE_ADDA_DL_RATE_22K; 83 case 24000: 84 return MTK_AFE_ADDA_DL_RATE_24K; 85 case 32000: 86 return MTK_AFE_ADDA_DL_RATE_32K; 87 case 44100: 88 return MTK_AFE_ADDA_DL_RATE_44K; 89 case 48000: 90 return MTK_AFE_ADDA_DL_RATE_48K; 91 case 96000: 92 return MTK_AFE_ADDA_DL_RATE_96K; 93 case 192000: 94 return MTK_AFE_ADDA_DL_RATE_192K; 95 default: 96 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 97 __func__, rate); 98 return MTK_AFE_ADDA_DL_RATE_48K; 99 } 100 } 101 102 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 103 unsigned int rate) 104 { 105 switch (rate) { 106 case 8000: 107 return MTK_AFE_ADDA_UL_RATE_8K; 108 case 16000: 109 return MTK_AFE_ADDA_UL_RATE_16K; 110 case 32000: 111 return MTK_AFE_ADDA_UL_RATE_32K; 112 case 48000: 113 return MTK_AFE_ADDA_UL_RATE_48K; 114 case 96000: 115 return MTK_AFE_ADDA_UL_RATE_96K; 116 case 192000: 117 return MTK_AFE_ADDA_UL_RATE_192K; 118 default: 119 dev_warn(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 120 __func__, rate); 121 return MTK_AFE_ADDA_UL_RATE_48K; 122 } 123 } 124 125 /* dai component */ 126 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 127 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN3, I_DL1_CH1, 1, 0), 128 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN3, I_DL12_CH1, 1, 0), 129 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN3, I_DL2_CH1, 1, 0), 130 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN3, I_DL3_CH1, 1, 0), 131 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN3_1, I_DL4_CH1, 1, 0), 132 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN3_1, I_DL5_CH1, 1, 0), 133 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN3_1, I_DL6_CH1, 1, 0), 134 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1", AFE_CONN3_1, I_DL8_CH1, 1, 0), 135 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN3, 136 I_ADDA_UL_CH3, 1, 0), 137 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN3, 138 I_ADDA_UL_CH2, 1, 0), 139 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN3, 140 I_ADDA_UL_CH1, 1, 0), 141 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN3, 142 I_GAIN1_OUT_CH1, 1, 0), 143 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN3, 144 I_PCM_1_CAP_CH1, 1, 0), 145 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN3, 146 I_PCM_2_CAP_CH1, 1, 0), 147 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN3_1, 148 I_SRC_1_OUT_CH1, 1, 0), 149 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1", AFE_CONN3_1, 150 I_SRC_2_OUT_CH1, 1, 0), 151 }; 152 153 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 154 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN4, I_DL1_CH1, 1, 0), 155 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN4, I_DL1_CH2, 1, 0), 156 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN4, I_DL12_CH2, 1, 0), 157 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN4, I_DL2_CH1, 1, 0), 158 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN4, I_DL2_CH2, 1, 0), 159 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN4, I_DL3_CH1, 1, 0), 160 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN4, I_DL3_CH2, 1, 0), 161 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN4_1, I_DL4_CH2, 1, 0), 162 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN4_1, I_DL5_CH2, 1, 0), 163 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN4_1, I_DL6_CH2, 1, 0), 164 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2", AFE_CONN4_1, I_DL8_CH2, 1, 0), 165 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN4, 166 I_ADDA_UL_CH3, 1, 0), 167 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN4, 168 I_ADDA_UL_CH2, 1, 0), 169 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN4, 170 I_ADDA_UL_CH1, 1, 0), 171 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN4, 172 I_GAIN1_OUT_CH2, 1, 0), 173 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN4, 174 I_PCM_1_CAP_CH1, 1, 0), 175 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN4, 176 I_PCM_2_CAP_CH1, 1, 0), 177 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN4, 178 I_PCM_1_CAP_CH2, 1, 0), 179 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN4, 180 I_PCM_2_CAP_CH2, 1, 0), 181 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN4_1, 182 I_SRC_1_OUT_CH2, 1, 0), 183 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2", AFE_CONN4_1, 184 I_SRC_2_OUT_CH2, 1, 0), 185 }; 186 187 static const struct snd_kcontrol_new mtk_adda_dl_ch3_mix[] = { 188 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN52, I_DL1_CH1, 1, 0), 189 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN52, I_DL12_CH1, 1, 0), 190 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN52, I_DL2_CH1, 1, 0), 191 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN52, I_DL3_CH1, 1, 0), 192 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN52_1, I_DL4_CH1, 1, 0), 193 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN52_1, I_DL5_CH1, 1, 0), 194 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN52_1, I_DL6_CH1, 1, 0), 195 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN52, 196 I_ADDA_UL_CH3, 1, 0), 197 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN52, 198 I_ADDA_UL_CH2, 1, 0), 199 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN52, 200 I_ADDA_UL_CH1, 1, 0), 201 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1", AFE_CONN52, 202 I_GAIN1_OUT_CH1, 1, 0), 203 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN52, 204 I_PCM_1_CAP_CH1, 1, 0), 205 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN52, 206 I_PCM_2_CAP_CH1, 1, 0), 207 }; 208 209 static const struct snd_kcontrol_new mtk_adda_dl_ch4_mix[] = { 210 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN53, I_DL1_CH1, 1, 0), 211 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN53, I_DL1_CH2, 1, 0), 212 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN53, I_DL12_CH2, 1, 0), 213 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN53, I_DL2_CH1, 1, 0), 214 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN53, I_DL2_CH2, 1, 0), 215 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN53, I_DL3_CH1, 1, 0), 216 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN53, I_DL3_CH2, 1, 0), 217 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN53_1, I_DL4_CH2, 1, 0), 218 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN53_1, I_DL5_CH2, 1, 0), 219 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN53_1, I_DL6_CH1, 1, 0), 220 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN53, 221 I_ADDA_UL_CH3, 1, 0), 222 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN53, 223 I_ADDA_UL_CH2, 1, 0), 224 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN53, 225 I_ADDA_UL_CH1, 1, 0), 226 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2", AFE_CONN53, 227 I_GAIN1_OUT_CH2, 1, 0), 228 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN53, 229 I_PCM_1_CAP_CH1, 1, 0), 230 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN53, 231 I_PCM_2_CAP_CH1, 1, 0), 232 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2", AFE_CONN53, 233 I_PCM_1_CAP_CH2, 1, 0), 234 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2", AFE_CONN53, 235 I_PCM_2_CAP_CH2, 1, 0), 236 }; 237 238 static const struct snd_kcontrol_new mtk_stf_ch1_mix[] = { 239 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN19, 240 I_ADDA_UL_CH1, 1, 0), 241 }; 242 243 static const struct snd_kcontrol_new mtk_stf_ch2_mix[] = { 244 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN20, 245 I_ADDA_UL_CH2, 1, 0), 246 }; 247 248 enum { 249 SUPPLY_SEQ_ADDA_AFE_ON, 250 SUPPLY_SEQ_ADDA_DL_ON, 251 SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 252 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 253 SUPPLY_SEQ_ADDA6_MTKAIF_CFG, 254 SUPPLY_SEQ_ADDA_FIFO, 255 SUPPLY_SEQ_ADDA_AP_DMIC, 256 SUPPLY_SEQ_ADDA_UL_ON, 257 }; 258 259 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) 260 { 261 unsigned int reg; 262 263 switch (id) { 264 case MT8192_DAI_ADDA: 265 case MT8192_DAI_AP_DMIC: 266 reg = AFE_ADDA_UL_SRC_CON0; 267 break; 268 case MT8192_DAI_ADDA_CH34: 269 case MT8192_DAI_AP_DMIC_CH34: 270 reg = AFE_ADDA6_UL_SRC_CON0; 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 /* dmic mode, 3.25M*/ 277 regmap_update_bits(afe->regmap, reg, 278 DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT, 279 0x0); 280 regmap_update_bits(afe->regmap, reg, 281 DMIC_LOW_POWER_MODE_CTL_MASK_SFT, 282 0x0); 283 284 /* turn on dmic, ch1, ch2 */ 285 regmap_update_bits(afe->regmap, reg, 286 UL_SDM_3_LEVEL_CTL_MASK_SFT, 287 0x1 << UL_SDM_3_LEVEL_CTL_SFT); 288 regmap_update_bits(afe->regmap, reg, 289 UL_MODE_3P25M_CH1_CTL_MASK_SFT, 290 0x1 << UL_MODE_3P25M_CH1_CTL_SFT); 291 regmap_update_bits(afe->regmap, reg, 292 UL_MODE_3P25M_CH2_CTL_MASK_SFT, 293 0x1 << UL_MODE_3P25M_CH2_CTL_SFT); 294 return 0; 295 } 296 297 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 298 struct snd_kcontrol *kcontrol, 299 int event) 300 { 301 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 302 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 303 struct mt8192_afe_private *afe_priv = afe->platform_priv; 304 int mtkaif_dmic = afe_priv->mtkaif_dmic; 305 306 switch (event) { 307 case SND_SOC_DAPM_PRE_PMU: 308 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 1); 309 310 /* update setting to dmic */ 311 if (mtkaif_dmic) { 312 /* mtkaif_rxif_data_mode = 1, dmic */ 313 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 314 0x1, 0x1); 315 316 /* dmic mode, 3.25M*/ 317 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 318 MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 319 0x0); 320 mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA); 321 } 322 break; 323 case SND_SOC_DAPM_POST_PMD: 324 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 325 usleep_range(125, 135); 326 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 1); 327 break; 328 default: 329 break; 330 } 331 332 return 0; 333 } 334 335 static int mtk_adda_ch34_ul_event(struct snd_soc_dapm_widget *w, 336 struct snd_kcontrol *kcontrol, 337 int event) 338 { 339 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 340 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 341 struct mt8192_afe_private *afe_priv = afe->platform_priv; 342 int mtkaif_dmic = afe_priv->mtkaif_dmic_ch34; 343 int mtkaif_adda6_only = afe_priv->mtkaif_adda6_only; 344 345 switch (event) { 346 case SND_SOC_DAPM_PRE_PMU: 347 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 348 1); 349 350 /* update setting to dmic */ 351 if (mtkaif_dmic) { 352 /* mtkaif_rxif_data_mode = 1, dmic */ 353 regmap_update_bits(afe->regmap, 354 AFE_ADDA6_MTKAIF_RX_CFG0, 355 0x1, 0x1); 356 357 /* dmic mode, 3.25M*/ 358 regmap_update_bits(afe->regmap, 359 AFE_ADDA6_MTKAIF_RX_CFG0, 360 MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 361 0x0); 362 mtk_adda_ul_src_dmic(afe, MT8192_DAI_ADDA_CH34); 363 } 364 365 /* when using adda6 without adda enabled, 366 * RG_ADDA6_MTKAIF_RX_SYNC_WORD2_DISABLE_SFT need to be set or 367 * data cannot be received. 368 */ 369 if (mtkaif_adda6_only) { 370 regmap_update_bits(afe->regmap, 371 AFE_ADDA_MTKAIF_SYNCWORD_CFG, 372 0x1 << 23, 0x1 << 23); 373 } 374 break; 375 case SND_SOC_DAPM_POST_PMD: 376 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 377 usleep_range(125, 135); 378 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 379 1); 380 381 /* reset dmic */ 382 afe_priv->mtkaif_dmic_ch34 = 0; 383 384 if (mtkaif_adda6_only) { 385 regmap_update_bits(afe->regmap, 386 AFE_ADDA_MTKAIF_SYNCWORD_CFG, 387 0x1 << 23, 0x0 << 23); 388 } 389 break; 390 default: 391 break; 392 } 393 394 return 0; 395 } 396 397 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w, 398 struct snd_kcontrol *kcontrol, 399 int event) 400 { 401 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 402 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 403 struct mt8192_afe_private *afe_priv = afe->platform_priv; 404 405 switch (event) { 406 case SND_SOC_DAPM_PRE_PMU: 407 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) 408 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x38); 409 else 410 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x30); 411 break; 412 default: 413 break; 414 } 415 416 return 0; 417 } 418 419 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 420 struct snd_kcontrol *kcontrol, 421 int event) 422 { 423 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 424 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 425 struct mt8192_afe_private *afe_priv = afe->platform_priv; 426 int delay_data; 427 int delay_cycle; 428 429 switch (event) { 430 case SND_SOC_DAPM_PRE_PMU: 431 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) { 432 /* set protocol 2 */ 433 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 434 0x00010000); 435 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 436 0x00010000); 437 438 if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0 && 439 (afe_priv->mtkaif_chosen_phase[0] < 0 || 440 afe_priv->mtkaif_chosen_phase[1] < 0)) { 441 dev_warn(afe->dev, 442 "%s(), mtkaif_chosen_phase[0/1]:%d/%d\n", 443 __func__, 444 afe_priv->mtkaif_chosen_phase[0], 445 afe_priv->mtkaif_chosen_phase[1]); 446 break; 447 } else if (strcmp(w->name, "ADDA6_MTKAIF_CFG") == 0 && 448 afe_priv->mtkaif_chosen_phase[2] < 0) { 449 dev_warn(afe->dev, 450 "%s(), mtkaif_chosen_phase[2]:%d\n", 451 __func__, 452 afe_priv->mtkaif_chosen_phase[2]); 453 break; 454 } 455 456 /* mtkaif_rxif_clkinv_adc inverse for calibration */ 457 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 458 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 459 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT); 460 regmap_update_bits(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 461 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 462 0x1 << MTKAIF_RXIF_CLKINV_ADC_SFT); 463 464 /* set delay for ch12 */ 465 if (afe_priv->mtkaif_phase_cycle[0] >= 466 afe_priv->mtkaif_phase_cycle[1]) { 467 delay_data = DELAY_DATA_MISO1; 468 delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 469 afe_priv->mtkaif_phase_cycle[1]; 470 } else { 471 delay_data = DELAY_DATA_MISO2; 472 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 473 afe_priv->mtkaif_phase_cycle[0]; 474 } 475 476 regmap_update_bits(afe->regmap, 477 AFE_ADDA_MTKAIF_RX_CFG2, 478 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 479 delay_data << 480 MTKAIF_RXIF_DELAY_DATA_SFT); 481 482 regmap_update_bits(afe->regmap, 483 AFE_ADDA_MTKAIF_RX_CFG2, 484 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 485 delay_cycle << 486 MTKAIF_RXIF_DELAY_CYCLE_SFT); 487 488 /* set delay between ch3 and ch2 */ 489 if (afe_priv->mtkaif_phase_cycle[2] >= 490 afe_priv->mtkaif_phase_cycle[1]) { 491 delay_data = DELAY_DATA_MISO1; /* ch3 */ 492 delay_cycle = afe_priv->mtkaif_phase_cycle[2] - 493 afe_priv->mtkaif_phase_cycle[1]; 494 } else { 495 delay_data = DELAY_DATA_MISO2; /* ch2 */ 496 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 497 afe_priv->mtkaif_phase_cycle[2]; 498 } 499 500 regmap_update_bits(afe->regmap, 501 AFE_ADDA6_MTKAIF_RX_CFG2, 502 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 503 delay_data << 504 MTKAIF_RXIF_DELAY_DATA_SFT); 505 regmap_update_bits(afe->regmap, 506 AFE_ADDA6_MTKAIF_RX_CFG2, 507 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 508 delay_cycle << 509 MTKAIF_RXIF_DELAY_CYCLE_SFT); 510 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) { 511 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 512 0x00010000); 513 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 514 0x00010000); 515 } else { 516 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x0); 517 regmap_write(afe->regmap, AFE_ADDA6_MTKAIF_CFG0, 0x0); 518 } 519 break; 520 default: 521 break; 522 } 523 524 return 0; 525 } 526 527 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 528 struct snd_kcontrol *kcontrol, 529 int event) 530 { 531 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 532 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 533 534 switch (event) { 535 case SND_SOC_DAPM_PRE_PMU: 536 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA, 0); 537 break; 538 case SND_SOC_DAPM_POST_PMD: 539 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 540 usleep_range(125, 135); 541 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA, 0); 542 break; 543 default: 544 break; 545 } 546 547 return 0; 548 } 549 550 static int mtk_adda_ch34_dl_event(struct snd_soc_dapm_widget *w, 551 struct snd_kcontrol *kcontrol, 552 int event) 553 { 554 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 555 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 556 557 switch (event) { 558 case SND_SOC_DAPM_PRE_PMU: 559 mt8192_afe_gpio_request(afe->dev, true, MT8192_DAI_ADDA_CH34, 560 0); 561 break; 562 case SND_SOC_DAPM_POST_PMD: 563 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 564 usleep_range(125, 135); 565 mt8192_afe_gpio_request(afe->dev, false, MT8192_DAI_ADDA_CH34, 566 0); 567 break; 568 default: 569 break; 570 } 571 572 return 0; 573 } 574 575 /* stf */ 576 static int stf_positive_gain_get(struct snd_kcontrol *kcontrol, 577 struct snd_ctl_elem_value *ucontrol) 578 { 579 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 580 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 581 struct mt8192_afe_private *afe_priv = afe->platform_priv; 582 583 ucontrol->value.integer.value[0] = afe_priv->stf_positive_gain_db; 584 return 0; 585 } 586 587 static int stf_positive_gain_set(struct snd_kcontrol *kcontrol, 588 struct snd_ctl_elem_value *ucontrol) 589 { 590 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 591 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 592 struct mt8192_afe_private *afe_priv = afe->platform_priv; 593 int gain_db = ucontrol->value.integer.value[0]; 594 bool change = false; 595 596 afe_priv->stf_positive_gain_db = gain_db; 597 598 if (gain_db >= 0 && gain_db <= 24) { 599 regmap_update_bits_check(afe->regmap, 600 AFE_SIDETONE_GAIN, 601 POSITIVE_GAIN_MASK_SFT, 602 (gain_db / 6) << POSITIVE_GAIN_SFT, 603 &change); 604 } else { 605 return -EINVAL; 606 } 607 608 return change; 609 } 610 611 static int mt8192_adda_dmic_get(struct snd_kcontrol *kcontrol, 612 struct snd_ctl_elem_value *ucontrol) 613 { 614 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 615 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 616 struct mt8192_afe_private *afe_priv = afe->platform_priv; 617 618 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 619 return 0; 620 } 621 622 static int mt8192_adda_dmic_set(struct snd_kcontrol *kcontrol, 623 struct snd_ctl_elem_value *ucontrol) 624 { 625 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 626 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 627 struct mt8192_afe_private *afe_priv = afe->platform_priv; 628 int dmic_on; 629 bool change; 630 631 dmic_on = ucontrol->value.integer.value[0]; 632 633 change = (afe_priv->mtkaif_dmic != dmic_on) || 634 (afe_priv->mtkaif_dmic_ch34 != dmic_on); 635 636 afe_priv->mtkaif_dmic = dmic_on; 637 afe_priv->mtkaif_dmic_ch34 = dmic_on; 638 639 return change; 640 } 641 642 static int mt8192_adda6_only_get(struct snd_kcontrol *kcontrol, 643 struct snd_ctl_elem_value *ucontrol) 644 { 645 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 646 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 647 struct mt8192_afe_private *afe_priv = afe->platform_priv; 648 649 ucontrol->value.integer.value[0] = afe_priv->mtkaif_adda6_only; 650 return 0; 651 } 652 653 static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol, 654 struct snd_ctl_elem_value *ucontrol) 655 { 656 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 657 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 658 struct mt8192_afe_private *afe_priv = afe->platform_priv; 659 int mtkaif_adda6_only; 660 bool change; 661 662 mtkaif_adda6_only = ucontrol->value.integer.value[0]; 663 664 change = afe_priv->mtkaif_adda6_only != mtkaif_adda6_only; 665 afe_priv->mtkaif_adda6_only = mtkaif_adda6_only; 666 667 return change; 668 } 669 670 static const struct snd_kcontrol_new mtk_adda_controls[] = { 671 SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN, 672 SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0), 673 SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 24, 0, 674 stf_positive_gain_get, stf_positive_gain_set), 675 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 676 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), 677 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 678 mt8192_adda_dmic_get, mt8192_adda_dmic_set), 679 SOC_SINGLE_BOOL_EXT("MTKAIF_ADDA6_ONLY Switch", 0, 680 mt8192_adda6_only_get, mt8192_adda6_only_set), 681 }; 682 683 static const struct snd_kcontrol_new stf_ctl = 684 SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0); 685 686 static const u16 stf_coeff_table_16k[] = { 687 0x049C, 0x09E8, 0x09E0, 0x089C, 688 0xFF54, 0xF488, 0xEAFC, 0xEBAC, 689 0xfA40, 0x17AC, 0x3D1C, 0x6028, 690 0x7538 691 }; 692 693 static const u16 stf_coeff_table_32k[] = { 694 0xFE52, 0x0042, 0x00C5, 0x0194, 695 0x029A, 0x03B7, 0x04BF, 0x057D, 696 0x05BE, 0x0555, 0x0426, 0x0230, 697 0xFF92, 0xFC89, 0xF973, 0xF6C6, 698 0xF500, 0xF49D, 0xF603, 0xF970, 699 0xFEF3, 0x065F, 0x0F4F, 0x1928, 700 0x2329, 0x2C80, 0x345E, 0x3A0D, 701 0x3D08 702 }; 703 704 static const u16 stf_coeff_table_48k[] = { 705 0x0401, 0xFFB0, 0xFF5A, 0xFECE, 706 0xFE10, 0xFD28, 0xFC21, 0xFB08, 707 0xF9EF, 0xF8E8, 0xF80A, 0xF76C, 708 0xF724, 0xF746, 0xF7E6, 0xF90F, 709 0xFACC, 0xFD1E, 0xFFFF, 0x0364, 710 0x0737, 0x0B62, 0x0FC1, 0x1431, 711 0x188A, 0x1CA4, 0x2056, 0x237D, 712 0x25F9, 0x27B0, 0x2890 713 }; 714 715 static int mtk_stf_event(struct snd_soc_dapm_widget *w, 716 struct snd_kcontrol *kcontrol, 717 int event) 718 { 719 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 720 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 721 722 size_t half_tap_num; 723 const u16 *stf_coeff_table; 724 unsigned int ul_rate, reg_value; 725 size_t coef_addr; 726 727 regmap_read(afe->regmap, AFE_ADDA_UL_SRC_CON0, &ul_rate); 728 ul_rate = ul_rate >> UL_VOICE_MODE_CH1_CH2_CTL_SFT; 729 ul_rate = ul_rate & UL_VOICE_MODE_CH1_CH2_CTL_MASK; 730 731 if (ul_rate == MTK_AFE_ADDA_UL_RATE_48K) { 732 half_tap_num = ARRAY_SIZE(stf_coeff_table_48k); 733 stf_coeff_table = stf_coeff_table_48k; 734 } else if (ul_rate == MTK_AFE_ADDA_UL_RATE_32K) { 735 half_tap_num = ARRAY_SIZE(stf_coeff_table_32k); 736 stf_coeff_table = stf_coeff_table_32k; 737 } else { 738 half_tap_num = ARRAY_SIZE(stf_coeff_table_16k); 739 stf_coeff_table = stf_coeff_table_16k; 740 } 741 742 regmap_read(afe->regmap, AFE_SIDETONE_CON1, ®_value); 743 744 switch (event) { 745 case SND_SOC_DAPM_PRE_PMU: 746 /* set side tone gain = 0 */ 747 regmap_update_bits(afe->regmap, 748 AFE_SIDETONE_GAIN, 749 SIDE_TONE_GAIN_MASK_SFT, 750 0); 751 regmap_update_bits(afe->regmap, 752 AFE_SIDETONE_GAIN, 753 POSITIVE_GAIN_MASK_SFT, 754 0); 755 /* don't bypass stf */ 756 regmap_update_bits(afe->regmap, 757 AFE_SIDETONE_CON1, 758 0x1f << 27, 759 0x0); 760 /* set stf half tap num */ 761 regmap_update_bits(afe->regmap, 762 AFE_SIDETONE_CON1, 763 SIDE_TONE_HALF_TAP_NUM_MASK_SFT, 764 half_tap_num << SIDE_TONE_HALF_TAP_NUM_SFT); 765 766 /* set side tone coefficient */ 767 regmap_read(afe->regmap, AFE_SIDETONE_CON0, ®_value); 768 for (coef_addr = 0; coef_addr < half_tap_num; coef_addr++) { 769 bool old_w_ready = (reg_value >> W_RDY_SFT) & 0x1; 770 bool new_w_ready = 0; 771 int try_cnt = 0; 772 773 regmap_update_bits(afe->regmap, 774 AFE_SIDETONE_CON0, 775 0x39FFFFF, 776 (1 << R_W_EN_SFT) | 777 (1 << R_W_SEL_SFT) | 778 (0 << SEL_CH2_SFT) | 779 (coef_addr << 780 SIDE_TONE_COEFFICIENT_ADDR_SFT) | 781 stf_coeff_table[coef_addr]); 782 783 /* wait until flag write_ready changed */ 784 for (try_cnt = 0; try_cnt < 10; try_cnt++) { 785 regmap_read(afe->regmap, 786 AFE_SIDETONE_CON0, ®_value); 787 new_w_ready = (reg_value >> W_RDY_SFT) & 0x1; 788 789 /* flip => ok */ 790 if (new_w_ready == old_w_ready) { 791 udelay(3); 792 if (try_cnt == 9) { 793 dev_warn(afe->dev, 794 "%s(), write coeff not ready", 795 __func__); 796 } 797 } else { 798 break; 799 } 800 } 801 /* need write -> read -> write to write next coeff */ 802 regmap_update_bits(afe->regmap, 803 AFE_SIDETONE_CON0, 804 R_W_SEL_MASK_SFT, 805 0x0); 806 } 807 break; 808 case SND_SOC_DAPM_POST_PMD: 809 /* bypass stf */ 810 regmap_update_bits(afe->regmap, 811 AFE_SIDETONE_CON1, 812 0x1f << 27, 813 0x1f << 27); 814 815 /* set side tone gain = 0 */ 816 regmap_update_bits(afe->regmap, 817 AFE_SIDETONE_GAIN, 818 SIDE_TONE_GAIN_MASK_SFT, 819 0); 820 regmap_update_bits(afe->regmap, 821 AFE_SIDETONE_GAIN, 822 POSITIVE_GAIN_MASK_SFT, 823 0); 824 break; 825 default: 826 break; 827 } 828 829 return 0; 830 } 831 832 /* stf mux */ 833 enum { 834 STF_SRC_ADDA_ADDA6 = 0, 835 STF_SRC_O19O20, 836 }; 837 838 static const char *const stf_o19o20_mux_map[] = { 839 "ADDA_ADDA6", 840 "O19O20", 841 }; 842 843 static int stf_o19o20_mux_map_value[] = { 844 STF_SRC_ADDA_ADDA6, 845 STF_SRC_O19O20, 846 }; 847 848 static SOC_VALUE_ENUM_SINGLE_DECL(stf_o19o20_mux_map_enum, 849 AFE_SIDETONE_CON1, 850 STF_SOURCE_FROM_O19O20_SFT, 851 STF_SOURCE_FROM_O19O20_MASK, 852 stf_o19o20_mux_map, 853 stf_o19o20_mux_map_value); 854 855 static const struct snd_kcontrol_new stf_o19O20_mux_control = 856 SOC_DAPM_ENUM("STF_O19O20_MUX", stf_o19o20_mux_map_enum); 857 858 enum { 859 STF_SRC_ADDA = 0, 860 STF_SRC_ADDA6, 861 }; 862 863 static const char *const stf_adda_mux_map[] = { 864 "ADDA", 865 "ADDA6", 866 }; 867 868 static int stf_adda_mux_map_value[] = { 869 STF_SRC_ADDA, 870 STF_SRC_ADDA6, 871 }; 872 873 static SOC_VALUE_ENUM_SINGLE_DECL(stf_adda_mux_map_enum, 874 AFE_SIDETONE_CON1, 875 STF_O19O20_OUT_EN_SEL_SFT, 876 STF_O19O20_OUT_EN_SEL_MASK, 877 stf_adda_mux_map, 878 stf_adda_mux_map_value); 879 880 static const struct snd_kcontrol_new stf_adda_mux_control = 881 SOC_DAPM_ENUM("STF_ADDA_MUX", stf_adda_mux_map_enum); 882 883 /* ADDA UL MUX */ 884 enum { 885 ADDA_UL_MUX_MTKAIF = 0, 886 ADDA_UL_MUX_AP_DMIC, 887 ADDA_UL_MUX_MASK = 0x1, 888 }; 889 890 static const char * const adda_ul_mux_map[] = { 891 "MTKAIF", "AP_DMIC" 892 }; 893 894 static int adda_ul_map_value[] = { 895 ADDA_UL_MUX_MTKAIF, 896 ADDA_UL_MUX_AP_DMIC, 897 }; 898 899 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 900 SND_SOC_NOPM, 901 0, 902 ADDA_UL_MUX_MASK, 903 adda_ul_mux_map, 904 adda_ul_map_value); 905 906 static const struct snd_kcontrol_new adda_ul_mux_control = 907 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 908 909 static const struct snd_kcontrol_new adda_ch34_ul_mux_control = 910 SOC_DAPM_ENUM("ADDA_CH34_UL_MUX Select", adda_ul_mux_map_enum); 911 912 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 913 /* inter-connections */ 914 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 915 mtk_adda_dl_ch1_mix, 916 ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 917 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 918 mtk_adda_dl_ch2_mix, 919 ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 920 921 SND_SOC_DAPM_MIXER("ADDA_DL_CH3", SND_SOC_NOPM, 0, 0, 922 mtk_adda_dl_ch3_mix, 923 ARRAY_SIZE(mtk_adda_dl_ch3_mix)), 924 SND_SOC_DAPM_MIXER("ADDA_DL_CH4", SND_SOC_NOPM, 0, 0, 925 mtk_adda_dl_ch4_mix, 926 ARRAY_SIZE(mtk_adda_dl_ch4_mix)), 927 928 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 929 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 930 NULL, 0), 931 932 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 933 AFE_ADDA_DL_SRC2_CON0, 934 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 935 mtk_adda_dl_event, 936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 937 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Playback Enable", 938 SUPPLY_SEQ_ADDA_DL_ON, 939 AFE_ADDA_3RD_DAC_DL_SRC2_CON0, 940 DL_2_SRC_ON_TMP_CTL_PRE_SFT, 0, 941 mtk_adda_ch34_dl_event, 942 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 943 944 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 945 AFE_ADDA_UL_SRC_CON0, 946 UL_SRC_ON_TMP_CTL_SFT, 0, 947 mtk_adda_ul_event, 948 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 949 SND_SOC_DAPM_SUPPLY_S("ADDA CH34 Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 950 AFE_ADDA6_UL_SRC_CON0, 951 UL_SRC_ON_TMP_CTL_SFT, 0, 952 mtk_adda_ch34_ul_event, 953 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 954 955 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 956 AFE_AUD_PAD_TOP, 957 RG_RX_FIFO_ON_SFT, 0, 958 mtk_adda_pad_top_event, 959 SND_SOC_DAPM_PRE_PMU), 960 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 961 SND_SOC_NOPM, 0, 0, 962 mtk_adda_mtkaif_cfg_event, 963 SND_SOC_DAPM_PRE_PMU), 964 SND_SOC_DAPM_SUPPLY_S("ADDA6_MTKAIF_CFG", SUPPLY_SEQ_ADDA6_MTKAIF_CFG, 965 SND_SOC_NOPM, 0, 0, 966 mtk_adda_mtkaif_cfg_event, 967 SND_SOC_DAPM_PRE_PMU), 968 969 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 970 AFE_ADDA_UL_SRC_CON0, 971 UL_AP_DMIC_ON_SFT, 0, 972 NULL, 0), 973 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_CH34_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 974 AFE_ADDA6_UL_SRC_CON0, 975 UL_AP_DMIC_ON_SFT, 0, 976 NULL, 0), 977 978 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 979 AFE_ADDA_UL_DL_CON0, 980 AFE_ADDA_FIFO_AUTO_RST_SFT, 1, 981 NULL, 0), 982 SND_SOC_DAPM_SUPPLY_S("ADDA_CH34_FIFO", SUPPLY_SEQ_ADDA_FIFO, 983 AFE_ADDA_UL_DL_CON0, 984 AFE_ADDA6_FIFO_AUTO_RST_SFT, 1, 985 NULL, 0), 986 987 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 988 &adda_ul_mux_control), 989 SND_SOC_DAPM_MUX("ADDA_CH34_UL_Mux", SND_SOC_NOPM, 0, 0, 990 &adda_ch34_ul_mux_control), 991 992 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 993 SND_SOC_DAPM_INPUT("AP_DMIC_CH34_INPUT"), 994 995 /* stf */ 996 SND_SOC_DAPM_SWITCH_E("Sidetone Filter", 997 AFE_SIDETONE_CON1, SIDE_TONE_ON_SFT, 0, 998 &stf_ctl, 999 mtk_stf_event, 1000 SND_SOC_DAPM_PRE_PMU | 1001 SND_SOC_DAPM_POST_PMD), 1002 SND_SOC_DAPM_MUX("STF_O19O20_MUX", SND_SOC_NOPM, 0, 0, 1003 &stf_o19O20_mux_control), 1004 SND_SOC_DAPM_MUX("STF_ADDA_MUX", SND_SOC_NOPM, 0, 0, 1005 &stf_adda_mux_control), 1006 SND_SOC_DAPM_MIXER("STF_CH1", SND_SOC_NOPM, 0, 0, 1007 mtk_stf_ch1_mix, 1008 ARRAY_SIZE(mtk_stf_ch1_mix)), 1009 SND_SOC_DAPM_MIXER("STF_CH2", SND_SOC_NOPM, 0, 0, 1010 mtk_stf_ch2_mix, 1011 ARRAY_SIZE(mtk_stf_ch2_mix)), 1012 SND_SOC_DAPM_OUTPUT("STF_OUTPUT"), 1013 1014 /* clock */ 1015 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"), 1016 1017 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 1018 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 1019 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_clk"), 1020 SND_SOC_DAPM_CLOCK_SUPPLY("aud_3rd_dac_predis_clk"), 1021 1022 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 1023 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adda6_adc_clk"), 1024 }; 1025 1026 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 1027 /* playback */ 1028 {"ADDA_DL_CH1", "DL1_CH1", "DL1"}, 1029 {"ADDA_DL_CH2", "DL1_CH1", "DL1"}, 1030 {"ADDA_DL_CH2", "DL1_CH2", "DL1"}, 1031 1032 {"ADDA_DL_CH1", "DL12_CH1", "DL12"}, 1033 {"ADDA_DL_CH2", "DL12_CH2", "DL12"}, 1034 1035 {"ADDA_DL_CH1", "DL6_CH1", "DL6"}, 1036 {"ADDA_DL_CH2", "DL6_CH2", "DL6"}, 1037 1038 {"ADDA_DL_CH1", "DL8_CH1", "DL8"}, 1039 {"ADDA_DL_CH2", "DL8_CH2", "DL8"}, 1040 1041 {"ADDA_DL_CH1", "DL2_CH1", "DL2"}, 1042 {"ADDA_DL_CH2", "DL2_CH1", "DL2"}, 1043 {"ADDA_DL_CH2", "DL2_CH2", "DL2"}, 1044 1045 {"ADDA_DL_CH1", "DL3_CH1", "DL3"}, 1046 {"ADDA_DL_CH2", "DL3_CH1", "DL3"}, 1047 {"ADDA_DL_CH2", "DL3_CH2", "DL3"}, 1048 1049 {"ADDA_DL_CH1", "DL4_CH1", "DL4"}, 1050 {"ADDA_DL_CH2", "DL4_CH2", "DL4"}, 1051 1052 {"ADDA_DL_CH1", "DL5_CH1", "DL5"}, 1053 {"ADDA_DL_CH2", "DL5_CH2", "DL5"}, 1054 1055 {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 1056 {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 1057 1058 {"ADDA Playback", NULL, "ADDA Enable"}, 1059 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 1060 1061 {"ADDA_DL_CH3", "DL1_CH1", "DL1"}, 1062 {"ADDA_DL_CH4", "DL1_CH1", "DL1"}, 1063 {"ADDA_DL_CH4", "DL1_CH2", "DL1"}, 1064 1065 {"ADDA_DL_CH3", "DL12_CH1", "DL12"}, 1066 {"ADDA_DL_CH4", "DL12_CH2", "DL12"}, 1067 1068 {"ADDA_DL_CH3", "DL6_CH1", "DL6"}, 1069 {"ADDA_DL_CH4", "DL6_CH2", "DL6"}, 1070 1071 {"ADDA_DL_CH3", "DL2_CH1", "DL2"}, 1072 {"ADDA_DL_CH4", "DL2_CH1", "DL2"}, 1073 {"ADDA_DL_CH4", "DL2_CH2", "DL2"}, 1074 1075 {"ADDA_DL_CH3", "DL3_CH1", "DL3"}, 1076 {"ADDA_DL_CH4", "DL3_CH1", "DL3"}, 1077 {"ADDA_DL_CH4", "DL3_CH2", "DL3"}, 1078 1079 {"ADDA_DL_CH3", "DL4_CH1", "DL4"}, 1080 {"ADDA_DL_CH4", "DL4_CH2", "DL4"}, 1081 1082 {"ADDA_DL_CH3", "DL5_CH1", "DL5"}, 1083 {"ADDA_DL_CH4", "DL5_CH2", "DL5"}, 1084 1085 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH3"}, 1086 {"ADDA CH34 Playback", NULL, "ADDA_DL_CH4"}, 1087 1088 {"ADDA CH34 Playback", NULL, "ADDA Enable"}, 1089 {"ADDA CH34 Playback", NULL, "ADDA CH34 Playback Enable"}, 1090 1091 /* capture */ 1092 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 1093 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 1094 1095 {"ADDA_CH34_UL_Mux", "MTKAIF", "ADDA CH34 Capture"}, 1096 {"ADDA_CH34_UL_Mux", "AP_DMIC", "AP DMIC CH34 Capture"}, 1097 1098 {"ADDA Capture", NULL, "ADDA Enable"}, 1099 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 1100 {"ADDA Capture", NULL, "AUD_PAD_TOP"}, 1101 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 1102 1103 {"AP DMIC Capture", NULL, "ADDA Enable"}, 1104 {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 1105 {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 1106 {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 1107 1108 {"ADDA CH34 Capture", NULL, "ADDA Enable"}, 1109 {"ADDA CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, 1110 {"ADDA CH34 Capture", NULL, "AUD_PAD_TOP"}, 1111 {"ADDA CH34 Capture", NULL, "ADDA6_MTKAIF_CFG"}, 1112 1113 {"AP DMIC CH34 Capture", NULL, "ADDA Enable"}, 1114 {"AP DMIC CH34 Capture", NULL, "ADDA CH34 Capture Enable"}, 1115 {"AP DMIC CH34 Capture", NULL, "ADDA_CH34_FIFO"}, 1116 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_EN"}, 1117 1118 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 1119 {"AP DMIC CH34 Capture", NULL, "AP_DMIC_CH34_INPUT"}, 1120 1121 /* sidetone filter */ 1122 {"STF_ADDA_MUX", "ADDA", "ADDA_UL_Mux"}, 1123 {"STF_ADDA_MUX", "ADDA6", "ADDA_CH34_UL_Mux"}, 1124 1125 {"STF_O19O20_MUX", "ADDA_ADDA6", "STF_ADDA_MUX"}, 1126 {"STF_O19O20_MUX", "O19O20", "STF_CH1"}, 1127 {"STF_O19O20_MUX", "O19O20", "STF_CH2"}, 1128 1129 {"Sidetone Filter", "Switch", "STF_O19O20_MUX"}, 1130 {"STF_OUTPUT", NULL, "Sidetone Filter"}, 1131 {"ADDA Playback", NULL, "Sidetone Filter"}, 1132 {"ADDA CH34 Playback", NULL, "Sidetone Filter"}, 1133 1134 /* clk */ 1135 {"ADDA Playback", NULL, "aud_dac_clk"}, 1136 {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 1137 1138 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_clk"}, 1139 {"ADDA CH34 Playback", NULL, "aud_3rd_dac_predis_clk"}, 1140 1141 {"ADDA Capture Enable", NULL, "aud_adc_clk"}, 1142 {"ADDA CH34 Capture Enable", NULL, "aud_adda6_adc_clk"}, 1143 }; 1144 1145 /* dai ops */ 1146 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 1147 struct snd_pcm_hw_params *params, 1148 struct snd_soc_dai *dai) 1149 { 1150 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1151 unsigned int rate = params_rate(params); 1152 int id = dai->id; 1153 1154 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 1155 unsigned int dl_src2_con0 = 0; 1156 unsigned int dl_src2_con1 = 0; 1157 1158 /* set sampling rate */ 1159 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 1160 DL_2_INPUT_MODE_CTL_SFT; 1161 1162 /* set output mode, UP_SAMPLING_RATE_X8 */ 1163 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT); 1164 1165 /* turn off mute function */ 1166 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH2_OFF_CTL_PRE_SFT); 1167 dl_src2_con0 |= (0x01 << DL_2_MUTE_CH1_OFF_CTL_PRE_SFT); 1168 1169 /* set voice input data if input sample rate is 8k or 16k */ 1170 if (rate == 8000 || rate == 16000) 1171 dl_src2_con0 |= 0x01 << DL_2_VOICE_MODE_CTL_PRE_SFT; 1172 1173 /* SA suggest apply -0.3db to audio/speech path */ 1174 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL << 1175 DL_2_GAIN_CTL_PRE_SFT; 1176 1177 /* turn on down-link gain */ 1178 dl_src2_con0 |= (0x01 << DL_2_GAIN_ON_CTL_PRE_SFT); 1179 1180 if (id == MT8192_DAI_ADDA) { 1181 /* clean predistortion */ 1182 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 1183 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 1184 1185 regmap_write(afe->regmap, 1186 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 1187 regmap_write(afe->regmap, 1188 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 1189 1190 /* set sdm gain */ 1191 regmap_update_bits(afe->regmap, 1192 AFE_ADDA_DL_SDM_DCCOMP_CON, 1193 ATTGAIN_CTL_MASK_SFT, 1194 AUDIO_SDM_LEVEL_NORMAL << 1195 ATTGAIN_CTL_SFT); 1196 1197 /* 2nd sdm */ 1198 regmap_update_bits(afe->regmap, 1199 AFE_ADDA_DL_SDM_DCCOMP_CON, 1200 USE_3RD_SDM_MASK_SFT, 1201 AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 1202 1203 /* sdm auto reset */ 1204 regmap_write(afe->regmap, 1205 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 1206 SDM_AUTO_RESET_THRESHOLD); 1207 regmap_update_bits(afe->regmap, 1208 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 1209 ADDA_SDM_AUTO_RESET_ONOFF_MASK_SFT, 1210 0x1 << ADDA_SDM_AUTO_RESET_ONOFF_SFT); 1211 } else { 1212 /* clean predistortion */ 1213 regmap_write(afe->regmap, 1214 AFE_ADDA_3RD_DAC_PREDIS_CON0, 0); 1215 regmap_write(afe->regmap, 1216 AFE_ADDA_3RD_DAC_PREDIS_CON1, 0); 1217 1218 regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON0, 1219 dl_src2_con0); 1220 regmap_write(afe->regmap, AFE_ADDA_3RD_DAC_DL_SRC2_CON1, 1221 dl_src2_con1); 1222 1223 /* set sdm gain */ 1224 regmap_update_bits(afe->regmap, 1225 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON, 1226 ATTGAIN_CTL_MASK_SFT, 1227 AUDIO_SDM_LEVEL_NORMAL << 1228 ATTGAIN_CTL_SFT); 1229 1230 /* 2nd sdm */ 1231 regmap_update_bits(afe->regmap, 1232 AFE_ADDA_3RD_DAC_DL_SDM_DCCOMP_CON, 1233 USE_3RD_SDM_MASK_SFT, 1234 AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 1235 1236 /* sdm auto reset */ 1237 regmap_write(afe->regmap, 1238 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON, 1239 SDM_AUTO_RESET_THRESHOLD); 1240 regmap_update_bits(afe->regmap, 1241 AFE_ADDA_3RD_DAC_DL_SDM_AUTO_RESET_CON, 1242 ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_MASK_SFT, 1243 0x1 << ADDA_3RD_DAC_SDM_AUTO_RESET_ONOFF_SFT); 1244 } 1245 } else { 1246 unsigned int voice_mode = 0; 1247 unsigned int ul_src_con0 = 0; /* default value */ 1248 1249 voice_mode = adda_ul_rate_transform(afe, rate); 1250 1251 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 1252 1253 /* enable iir */ 1254 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 1255 UL_IIR_ON_TMP_CTL_MASK_SFT; 1256 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 1257 UL_IIRMODE_CTL_MASK_SFT; 1258 1259 switch (id) { 1260 case MT8192_DAI_ADDA: 1261 case MT8192_DAI_AP_DMIC: 1262 /* 35Hz @ 48k */ 1263 regmap_write(afe->regmap, 1264 AFE_ADDA_IIR_COEF_02_01, 0x00000000); 1265 regmap_write(afe->regmap, 1266 AFE_ADDA_IIR_COEF_04_03, 0x00003FB8); 1267 regmap_write(afe->regmap, 1268 AFE_ADDA_IIR_COEF_06_05, 0x3FB80000); 1269 regmap_write(afe->regmap, 1270 AFE_ADDA_IIR_COEF_08_07, 0x3FB80000); 1271 regmap_write(afe->regmap, 1272 AFE_ADDA_IIR_COEF_10_09, 0x0000C048); 1273 1274 regmap_write(afe->regmap, 1275 AFE_ADDA_UL_SRC_CON0, ul_src_con0); 1276 1277 /* Using Internal ADC */ 1278 regmap_update_bits(afe->regmap, 1279 AFE_ADDA_TOP_CON0, 1280 0x1 << 0, 1281 0x0 << 0); 1282 1283 /* mtkaif_rxif_data_mode = 0, amic */ 1284 regmap_update_bits(afe->regmap, 1285 AFE_ADDA_MTKAIF_RX_CFG0, 1286 0x1 << 0, 1287 0x0 << 0); 1288 break; 1289 case MT8192_DAI_ADDA_CH34: 1290 case MT8192_DAI_AP_DMIC_CH34: 1291 /* 35Hz @ 48k */ 1292 regmap_write(afe->regmap, 1293 AFE_ADDA6_IIR_COEF_02_01, 0x00000000); 1294 regmap_write(afe->regmap, 1295 AFE_ADDA6_IIR_COEF_04_03, 0x00003FB8); 1296 regmap_write(afe->regmap, 1297 AFE_ADDA6_IIR_COEF_06_05, 0x3FB80000); 1298 regmap_write(afe->regmap, 1299 AFE_ADDA6_IIR_COEF_08_07, 0x3FB80000); 1300 regmap_write(afe->regmap, 1301 AFE_ADDA6_IIR_COEF_10_09, 0x0000C048); 1302 1303 regmap_write(afe->regmap, 1304 AFE_ADDA6_UL_SRC_CON0, ul_src_con0); 1305 1306 /* Using Internal ADC */ 1307 regmap_update_bits(afe->regmap, 1308 AFE_ADDA6_TOP_CON0, 1309 0x1 << 0, 1310 0x0 << 0); 1311 1312 /* mtkaif_rxif_data_mode = 0, amic */ 1313 regmap_update_bits(afe->regmap, 1314 AFE_ADDA6_MTKAIF_RX_CFG0, 1315 0x1 << 0, 1316 0x0 << 0); 1317 break; 1318 default: 1319 break; 1320 } 1321 1322 /* ap dmic */ 1323 switch (id) { 1324 case MT8192_DAI_AP_DMIC: 1325 case MT8192_DAI_AP_DMIC_CH34: 1326 mtk_adda_ul_src_dmic(afe, id); 1327 break; 1328 default: 1329 break; 1330 } 1331 } 1332 1333 return 0; 1334 } 1335 1336 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 1337 .hw_params = mtk_dai_adda_hw_params, 1338 }; 1339 1340 /* dai driver */ 1341 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 1342 SNDRV_PCM_RATE_96000 |\ 1343 SNDRV_PCM_RATE_192000) 1344 1345 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 1346 SNDRV_PCM_RATE_16000 |\ 1347 SNDRV_PCM_RATE_32000 |\ 1348 SNDRV_PCM_RATE_48000 |\ 1349 SNDRV_PCM_RATE_96000 |\ 1350 SNDRV_PCM_RATE_192000) 1351 1352 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 1353 SNDRV_PCM_FMTBIT_S24_LE |\ 1354 SNDRV_PCM_FMTBIT_S32_LE) 1355 1356 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 1357 { 1358 .name = "ADDA", 1359 .id = MT8192_DAI_ADDA, 1360 .playback = { 1361 .stream_name = "ADDA Playback", 1362 .channels_min = 1, 1363 .channels_max = 2, 1364 .rates = MTK_ADDA_PLAYBACK_RATES, 1365 .formats = MTK_ADDA_FORMATS, 1366 }, 1367 .capture = { 1368 .stream_name = "ADDA Capture", 1369 .channels_min = 1, 1370 .channels_max = 2, 1371 .rates = MTK_ADDA_CAPTURE_RATES, 1372 .formats = MTK_ADDA_FORMATS, 1373 }, 1374 .ops = &mtk_dai_adda_ops, 1375 }, 1376 { 1377 .name = "ADDA_CH34", 1378 .id = MT8192_DAI_ADDA_CH34, 1379 .playback = { 1380 .stream_name = "ADDA CH34 Playback", 1381 .channels_min = 1, 1382 .channels_max = 2, 1383 .rates = MTK_ADDA_PLAYBACK_RATES, 1384 .formats = MTK_ADDA_FORMATS, 1385 }, 1386 .capture = { 1387 .stream_name = "ADDA CH34 Capture", 1388 .channels_min = 1, 1389 .channels_max = 2, 1390 .rates = MTK_ADDA_CAPTURE_RATES, 1391 .formats = MTK_ADDA_FORMATS, 1392 }, 1393 .ops = &mtk_dai_adda_ops, 1394 }, 1395 { 1396 .name = "AP_DMIC", 1397 .id = MT8192_DAI_AP_DMIC, 1398 .capture = { 1399 .stream_name = "AP DMIC Capture", 1400 .channels_min = 1, 1401 .channels_max = 2, 1402 .rates = MTK_ADDA_CAPTURE_RATES, 1403 .formats = MTK_ADDA_FORMATS, 1404 }, 1405 .ops = &mtk_dai_adda_ops, 1406 }, 1407 { 1408 .name = "AP_DMIC_CH34", 1409 .id = MT8192_DAI_AP_DMIC_CH34, 1410 .capture = { 1411 .stream_name = "AP DMIC CH34 Capture", 1412 .channels_min = 1, 1413 .channels_max = 2, 1414 .rates = MTK_ADDA_CAPTURE_RATES, 1415 .formats = MTK_ADDA_FORMATS, 1416 }, 1417 .ops = &mtk_dai_adda_ops, 1418 }, 1419 }; 1420 1421 int mt8192_dai_adda_register(struct mtk_base_afe *afe) 1422 { 1423 struct mtk_base_afe_dai *dai; 1424 struct mt8192_afe_private *afe_priv = afe->platform_priv; 1425 1426 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 1427 if (!dai) 1428 return -ENOMEM; 1429 1430 list_add(&dai->list, &afe->sub_dais); 1431 1432 dai->dai_drivers = mtk_dai_adda_driver; 1433 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 1434 1435 dai->controls = mtk_adda_controls; 1436 dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 1437 dai->dapm_widgets = mtk_dai_adda_widgets; 1438 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 1439 dai->dapm_routes = mtk_dai_adda_routes; 1440 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 1441 1442 /* ap dmic priv share with adda */ 1443 afe_priv->dai_priv[MT8192_DAI_AP_DMIC] = 1444 afe_priv->dai_priv[MT8192_DAI_ADDA]; 1445 afe_priv->dai_priv[MT8192_DAI_AP_DMIC_CH34] = 1446 afe_priv->dai_priv[MT8192_DAI_ADDA_CH34]; 1447 1448 return 0; 1449 } 1450