1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Mediatek ALSA SoC AFE platform driver for 8192 4 // 5 // Copyright (c) 2020 MediaTek Inc. 6 // Author: Shane Chien <shane.chien@mediatek.com> 7 // 8 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/module.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 #include <sound/soc.h> 19 20 #include "../common/mtk-afe-fe-dai.h" 21 #include "../common/mtk-afe-platform-driver.h" 22 23 #include "mt8192-afe-common.h" 24 #include "mt8192-afe-clk.h" 25 #include "mt8192-afe-gpio.h" 26 #include "mt8192-interconnection.h" 27 28 static const struct snd_pcm_hardware mt8192_afe_hardware = { 29 .info = (SNDRV_PCM_INFO_MMAP | 30 SNDRV_PCM_INFO_INTERLEAVED | 31 SNDRV_PCM_INFO_MMAP_VALID), 32 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 33 SNDRV_PCM_FMTBIT_S24_LE | 34 SNDRV_PCM_FMTBIT_S32_LE), 35 .period_bytes_min = 96, 36 .period_bytes_max = 4 * 48 * 1024, 37 .periods_min = 2, 38 .periods_max = 256, 39 .buffer_bytes_max = 4 * 48 * 1024, 40 .fifo_size = 0, 41 }; 42 43 static int mt8192_memif_fs(struct snd_pcm_substream *substream, 44 unsigned int rate) 45 { 46 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 47 struct snd_soc_component *component = 48 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 49 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 50 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 51 52 return mt8192_rate_transform(afe->dev, rate, id); 53 } 54 55 static int mt8192_get_dai_fs(struct mtk_base_afe *afe, 56 int dai_id, unsigned int rate) 57 { 58 return mt8192_rate_transform(afe->dev, rate, dai_id); 59 } 60 61 static int mt8192_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 62 { 63 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 64 struct snd_soc_component *component = 65 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 66 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 67 68 return mt8192_general_rate_transform(afe->dev, rate); 69 } 70 71 static int mt8192_get_memif_pbuf_size(struct snd_pcm_substream *substream) 72 { 73 struct snd_pcm_runtime *runtime = substream->runtime; 74 75 if ((runtime->period_size * 1000) / runtime->rate > 10) 76 return MT8192_MEMIF_PBUF_SIZE_256_BYTES; 77 else 78 return MT8192_MEMIF_PBUF_SIZE_32_BYTES; 79 } 80 81 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 82 SNDRV_PCM_RATE_88200 |\ 83 SNDRV_PCM_RATE_96000 |\ 84 SNDRV_PCM_RATE_176400 |\ 85 SNDRV_PCM_RATE_192000) 86 87 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 88 SNDRV_PCM_RATE_16000 |\ 89 SNDRV_PCM_RATE_32000 |\ 90 SNDRV_PCM_RATE_48000) 91 92 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 93 SNDRV_PCM_FMTBIT_S24_LE |\ 94 SNDRV_PCM_FMTBIT_S32_LE) 95 96 static struct snd_soc_dai_driver mt8192_memif_dai_driver[] = { 97 /* FE DAIs: memory intefaces to CPU */ 98 { 99 .name = "DL1", 100 .id = MT8192_MEMIF_DL1, 101 .playback = { 102 .stream_name = "DL1", 103 .channels_min = 1, 104 .channels_max = 2, 105 .rates = MTK_PCM_RATES, 106 .formats = MTK_PCM_FORMATS, 107 }, 108 .ops = &mtk_afe_fe_ops, 109 }, 110 { 111 .name = "DL12", 112 .id = MT8192_MEMIF_DL12, 113 .playback = { 114 .stream_name = "DL12", 115 .channels_min = 1, 116 .channels_max = 2, 117 .rates = MTK_PCM_RATES, 118 .formats = MTK_PCM_FORMATS, 119 }, 120 .ops = &mtk_afe_fe_ops, 121 }, 122 { 123 .name = "DL2", 124 .id = MT8192_MEMIF_DL2, 125 .playback = { 126 .stream_name = "DL2", 127 .channels_min = 1, 128 .channels_max = 2, 129 .rates = MTK_PCM_RATES, 130 .formats = MTK_PCM_FORMATS, 131 }, 132 .ops = &mtk_afe_fe_ops, 133 }, 134 { 135 .name = "DL3", 136 .id = MT8192_MEMIF_DL3, 137 .playback = { 138 .stream_name = "DL3", 139 .channels_min = 1, 140 .channels_max = 2, 141 .rates = MTK_PCM_RATES, 142 .formats = MTK_PCM_FORMATS, 143 }, 144 .ops = &mtk_afe_fe_ops, 145 }, 146 { 147 .name = "DL4", 148 .id = MT8192_MEMIF_DL4, 149 .playback = { 150 .stream_name = "DL4", 151 .channels_min = 1, 152 .channels_max = 2, 153 .rates = MTK_PCM_RATES, 154 .formats = MTK_PCM_FORMATS, 155 }, 156 .ops = &mtk_afe_fe_ops, 157 }, 158 { 159 .name = "DL5", 160 .id = MT8192_MEMIF_DL5, 161 .playback = { 162 .stream_name = "DL5", 163 .channels_min = 1, 164 .channels_max = 2, 165 .rates = MTK_PCM_RATES, 166 .formats = MTK_PCM_FORMATS, 167 }, 168 .ops = &mtk_afe_fe_ops, 169 }, 170 { 171 .name = "DL6", 172 .id = MT8192_MEMIF_DL6, 173 .playback = { 174 .stream_name = "DL6", 175 .channels_min = 1, 176 .channels_max = 2, 177 .rates = MTK_PCM_RATES, 178 .formats = MTK_PCM_FORMATS, 179 }, 180 .ops = &mtk_afe_fe_ops, 181 }, 182 { 183 .name = "DL7", 184 .id = MT8192_MEMIF_DL7, 185 .playback = { 186 .stream_name = "DL7", 187 .channels_min = 1, 188 .channels_max = 2, 189 .rates = MTK_PCM_RATES, 190 .formats = MTK_PCM_FORMATS, 191 }, 192 .ops = &mtk_afe_fe_ops, 193 }, 194 { 195 .name = "DL8", 196 .id = MT8192_MEMIF_DL8, 197 .playback = { 198 .stream_name = "DL8", 199 .channels_min = 1, 200 .channels_max = 2, 201 .rates = MTK_PCM_RATES, 202 .formats = MTK_PCM_FORMATS, 203 }, 204 .ops = &mtk_afe_fe_ops, 205 }, 206 { 207 .name = "DL9", 208 .id = MT8192_MEMIF_DL9, 209 .playback = { 210 .stream_name = "DL9", 211 .channels_min = 1, 212 .channels_max = 2, 213 .rates = MTK_PCM_RATES, 214 .formats = MTK_PCM_FORMATS, 215 }, 216 .ops = &mtk_afe_fe_ops, 217 }, 218 { 219 .name = "UL1", 220 .id = MT8192_MEMIF_VUL12, 221 .capture = { 222 .stream_name = "UL1", 223 .channels_min = 1, 224 .channels_max = 4, 225 .rates = MTK_PCM_RATES, 226 .formats = MTK_PCM_FORMATS, 227 }, 228 .ops = &mtk_afe_fe_ops, 229 }, 230 { 231 .name = "UL2", 232 .id = MT8192_MEMIF_AWB, 233 .capture = { 234 .stream_name = "UL2", 235 .channels_min = 1, 236 .channels_max = 2, 237 .rates = MTK_PCM_RATES, 238 .formats = MTK_PCM_FORMATS, 239 }, 240 .ops = &mtk_afe_fe_ops, 241 }, 242 { 243 .name = "UL3", 244 .id = MT8192_MEMIF_VUL2, 245 .capture = { 246 .stream_name = "UL3", 247 .channels_min = 1, 248 .channels_max = 2, 249 .rates = MTK_PCM_RATES, 250 .formats = MTK_PCM_FORMATS, 251 }, 252 .ops = &mtk_afe_fe_ops, 253 }, 254 { 255 .name = "UL4", 256 .id = MT8192_MEMIF_AWB2, 257 .capture = { 258 .stream_name = "UL4", 259 .channels_min = 1, 260 .channels_max = 2, 261 .rates = MTK_PCM_RATES, 262 .formats = MTK_PCM_FORMATS, 263 }, 264 .ops = &mtk_afe_fe_ops, 265 }, 266 { 267 .name = "UL5", 268 .id = MT8192_MEMIF_VUL3, 269 .capture = { 270 .stream_name = "UL5", 271 .channels_min = 1, 272 .channels_max = 2, 273 .rates = MTK_PCM_RATES, 274 .formats = MTK_PCM_FORMATS, 275 }, 276 .ops = &mtk_afe_fe_ops, 277 }, 278 { 279 .name = "UL6", 280 .id = MT8192_MEMIF_VUL4, 281 .capture = { 282 .stream_name = "UL6", 283 .channels_min = 1, 284 .channels_max = 2, 285 .rates = MTK_PCM_RATES, 286 .formats = MTK_PCM_FORMATS, 287 }, 288 .ops = &mtk_afe_fe_ops, 289 }, 290 { 291 .name = "UL7", 292 .id = MT8192_MEMIF_VUL5, 293 .capture = { 294 .stream_name = "UL7", 295 .channels_min = 1, 296 .channels_max = 2, 297 .rates = MTK_PCM_RATES, 298 .formats = MTK_PCM_FORMATS, 299 }, 300 .ops = &mtk_afe_fe_ops, 301 }, 302 { 303 .name = "UL8", 304 .id = MT8192_MEMIF_VUL6, 305 .capture = { 306 .stream_name = "UL8", 307 .channels_min = 1, 308 .channels_max = 2, 309 .rates = MTK_PCM_RATES, 310 .formats = MTK_PCM_FORMATS, 311 }, 312 .ops = &mtk_afe_fe_ops, 313 }, 314 { 315 .name = "UL_MONO_1", 316 .id = MT8192_MEMIF_MOD_DAI, 317 .capture = { 318 .stream_name = "UL_MONO_1", 319 .channels_min = 1, 320 .channels_max = 2, 321 .rates = MTK_PCM_DAI_RATES, 322 .formats = MTK_PCM_FORMATS, 323 }, 324 .ops = &mtk_afe_fe_ops, 325 }, 326 { 327 .name = "UL_MONO_2", 328 .id = MT8192_MEMIF_DAI, 329 .capture = { 330 .stream_name = "UL_MONO_2", 331 .channels_min = 1, 332 .channels_max = 2, 333 .rates = MTK_PCM_DAI_RATES, 334 .formats = MTK_PCM_FORMATS, 335 }, 336 .ops = &mtk_afe_fe_ops, 337 }, 338 { 339 .name = "UL_MONO_3", 340 .id = MT8192_MEMIF_DAI2, 341 .capture = { 342 .stream_name = "UL_MONO_3", 343 .channels_min = 1, 344 .channels_max = 2, 345 .rates = MTK_PCM_DAI_RATES, 346 .formats = MTK_PCM_FORMATS, 347 }, 348 .ops = &mtk_afe_fe_ops, 349 }, 350 { 351 .name = "HDMI", 352 .id = MT8192_MEMIF_HDMI, 353 .playback = { 354 .stream_name = "HDMI", 355 .channels_min = 2, 356 .channels_max = 8, 357 .rates = MTK_PCM_RATES, 358 .formats = MTK_PCM_FORMATS, 359 }, 360 .ops = &mtk_afe_fe_ops, 361 }, 362 }; 363 364 static int ul_tinyconn_event(struct snd_soc_dapm_widget *w, 365 struct snd_kcontrol *kcontrol, 366 int event) 367 { 368 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 369 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 370 unsigned int reg_shift; 371 unsigned int reg_mask_shift; 372 373 dev_dbg(afe->dev, "%s(), event 0x%x\n", __func__, event); 374 375 if (strstr(w->name, "UL1")) { 376 reg_shift = VUL1_USE_TINY_SFT; 377 reg_mask_shift = VUL1_USE_TINY_MASK_SFT; 378 } else if (strstr(w->name, "UL2")) { 379 reg_shift = VUL2_USE_TINY_SFT; 380 reg_mask_shift = VUL2_USE_TINY_MASK_SFT; 381 } else if (strstr(w->name, "UL3")) { 382 reg_shift = VUL12_USE_TINY_SFT; 383 reg_mask_shift = VUL12_USE_TINY_MASK_SFT; 384 } else if (strstr(w->name, "UL4")) { 385 reg_shift = AWB2_USE_TINY_SFT; 386 reg_mask_shift = AWB2_USE_TINY_MASK_SFT; 387 } else { 388 reg_shift = AWB2_USE_TINY_SFT; 389 reg_mask_shift = AWB2_USE_TINY_MASK_SFT; 390 dev_warn(afe->dev, "%s(), err widget name %s, default use UL4", 391 __func__, w->name); 392 } 393 394 switch (event) { 395 case SND_SOC_DAPM_PRE_PMU: 396 regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift, 397 0x1 << reg_shift); 398 break; 399 case SND_SOC_DAPM_PRE_PMD: 400 regmap_update_bits(afe->regmap, AFE_MEMIF_CONN, reg_mask_shift, 401 0x0 << reg_shift); 402 break; 403 default: 404 break; 405 } 406 407 return 0; 408 } 409 410 /* dma widget & routes*/ 411 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 412 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN21, 413 I_ADDA_UL_CH1, 1, 0), 414 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN21, 415 I_ADDA_UL_CH2, 1, 0), 416 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN21, 417 I_ADDA_UL_CH3, 1, 0), 418 }; 419 420 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 421 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN22, 422 I_ADDA_UL_CH1, 1, 0), 423 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN22, 424 I_ADDA_UL_CH2, 1, 0), 425 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN22, 426 I_ADDA_UL_CH3, 1, 0), 427 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN22, 428 I_ADDA_UL_CH4, 1, 0), 429 }; 430 431 static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = { 432 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN9, 433 I_ADDA_UL_CH1, 1, 0), 434 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN9, 435 I_ADDA_UL_CH2, 1, 0), 436 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN9, 437 I_ADDA_UL_CH3, 1, 0), 438 }; 439 440 static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = { 441 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN10, 442 I_ADDA_UL_CH1, 1, 0), 443 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN10, 444 I_ADDA_UL_CH2, 1, 0), 445 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3", AFE_CONN10, 446 I_ADDA_UL_CH3, 1, 0), 447 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4", AFE_CONN10, 448 I_ADDA_UL_CH4, 1, 0), 449 }; 450 451 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 452 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN5, 453 I_I2S0_CH1, 1, 0), 454 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN5, 455 I_DL1_CH1, 1, 0), 456 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN5, 457 I_DL12_CH1, 1, 0), 458 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN5, 459 I_DL2_CH1, 1, 0), 460 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN5, 461 I_DL3_CH1, 1, 0), 462 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN5_1, 463 I_DL4_CH1, 1, 0), 464 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1", AFE_CONN5_1, 465 I_DL5_CH1, 1, 0), 466 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN5_1, 467 I_DL6_CH1, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN5, 469 I_PCM_1_CAP_CH1, 1, 0), 470 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN5, 471 I_PCM_2_CAP_CH1, 1, 0), 472 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1", AFE_CONN5, 473 I_I2S2_CH1, 1, 0), 474 SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH1", AFE_CONN5_1, 475 I_I2S6_CH1, 1, 0), 476 SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH1", AFE_CONN5_1, 477 I_I2S8_CH1, 1, 0), 478 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN5_1, 479 I_CONNSYS_I2S_CH1, 1, 0), 480 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1", AFE_CONN5_1, 481 I_SRC_1_OUT_CH1, 1, 0), 482 }; 483 484 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 485 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN6, 486 I_I2S0_CH2, 1, 0), 487 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN6, 488 I_DL1_CH2, 1, 0), 489 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN6, 490 I_DL12_CH2, 1, 0), 491 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN6, 492 I_DL2_CH2, 1, 0), 493 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN6, 494 I_DL3_CH2, 1, 0), 495 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN6_1, 496 I_DL4_CH2, 1, 0), 497 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2", AFE_CONN6_1, 498 I_DL5_CH2, 1, 0), 499 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN6_1, 500 I_DL6_CH2, 1, 0), 501 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN6, 502 I_PCM_1_CAP_CH1, 1, 0), 503 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN6, 504 I_PCM_2_CAP_CH1, 1, 0), 505 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2", AFE_CONN6, 506 I_I2S2_CH2, 1, 0), 507 SOC_DAPM_SINGLE_AUTODISABLE("I2S6_CH2", AFE_CONN6_1, 508 I_I2S6_CH2, 1, 0), 509 SOC_DAPM_SINGLE_AUTODISABLE("I2S8_CH2", AFE_CONN6_1, 510 I_I2S8_CH2, 1, 0), 511 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN6_1, 512 I_CONNSYS_I2S_CH2, 1, 0), 513 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2", AFE_CONN6_1, 514 I_SRC_1_OUT_CH2, 1, 0), 515 }; 516 517 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 518 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1", AFE_CONN32_1, 519 I_CONNSYS_I2S_CH1, 1, 0), 520 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN32, 521 I_DL1_CH1, 1, 0), 522 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN32, 523 I_DL2_CH1, 1, 0), 524 }; 525 526 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 527 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2", AFE_CONN33_1, 528 I_CONNSYS_I2S_CH2, 1, 0), 529 }; 530 531 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { 532 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN38, 533 I_ADDA_UL_CH1, 1, 0), 534 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1", AFE_CONN38, 535 I_I2S0_CH1, 1, 0), 536 }; 537 538 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { 539 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN39, 540 I_ADDA_UL_CH2, 1, 0), 541 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2", AFE_CONN39, 542 I_I2S0_CH2, 1, 0), 543 }; 544 545 static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = { 546 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN44, 547 I_ADDA_UL_CH1, 1, 0), 548 }; 549 550 static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = { 551 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN45, 552 I_ADDA_UL_CH2, 1, 0), 553 }; 554 555 static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = { 556 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN46, 557 I_ADDA_UL_CH1, 1, 0), 558 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1", AFE_CONN46, 559 I_DL1_CH1, 1, 0), 560 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1", AFE_CONN46, 561 I_DL12_CH1, 1, 0), 562 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1", AFE_CONN46_1, 563 I_DL6_CH1, 1, 0), 564 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1", AFE_CONN46, 565 I_DL2_CH1, 1, 0), 566 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1", AFE_CONN46, 567 I_DL3_CH1, 1, 0), 568 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1", AFE_CONN46_1, 569 I_DL4_CH1, 1, 0), 570 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN46, 571 I_PCM_1_CAP_CH1, 1, 0), 572 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN46, 573 I_PCM_2_CAP_CH1, 1, 0), 574 }; 575 576 static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = { 577 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN47, 578 I_ADDA_UL_CH2, 1, 0), 579 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2", AFE_CONN47, 580 I_DL1_CH2, 1, 0), 581 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2", AFE_CONN47, 582 I_DL12_CH2, 1, 0), 583 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2", AFE_CONN47_1, 584 I_DL6_CH2, 1, 0), 585 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2", AFE_CONN47, 586 I_DL2_CH2, 1, 0), 587 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2", AFE_CONN47, 588 I_DL3_CH2, 1, 0), 589 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2", AFE_CONN47_1, 590 I_DL4_CH2, 1, 0), 591 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN47, 592 I_PCM_1_CAP_CH1, 1, 0), 593 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN47, 594 I_PCM_2_CAP_CH1, 1, 0), 595 }; 596 597 static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = { 598 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN48, 599 I_ADDA_UL_CH1, 1, 0), 600 }; 601 602 static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = { 603 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN49, 604 I_ADDA_UL_CH2, 1, 0), 605 }; 606 607 static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = { 608 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN50, 609 I_ADDA_UL_CH1, 1, 0), 610 }; 611 612 static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = { 613 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2", AFE_CONN51, 614 I_ADDA_UL_CH2, 1, 0), 615 }; 616 617 static const struct snd_kcontrol_new memif_ul_mono_1_mix[] = { 618 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1", AFE_CONN12, 619 I_PCM_1_CAP_CH1, 1, 0), 620 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1", AFE_CONN12, 621 I_PCM_2_CAP_CH1, 1, 0), 622 }; 623 624 static const struct snd_kcontrol_new memif_ul_mono_2_mix[] = { 625 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN11, 626 I_ADDA_UL_CH1, 1, 0), 627 }; 628 629 static const struct snd_kcontrol_new memif_ul_mono_3_mix[] = { 630 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1", AFE_CONN35, 631 I_ADDA_UL_CH1, 1, 0), 632 }; 633 634 /* TINYCONN MUX */ 635 enum { 636 TINYCONN_CH1_MUX_I2S0 = 0x14, 637 TINYCONN_CH2_MUX_I2S0 = 0x15, 638 TINYCONN_CH1_MUX_I2S6 = 0x1a, 639 TINYCONN_CH2_MUX_I2S6 = 0x1b, 640 TINYCONN_CH1_MUX_I2S8 = 0x1c, 641 TINYCONN_CH2_MUX_I2S8 = 0x1d, 642 TINYCONN_MUX_NONE = 0x1f, 643 }; 644 645 static const char * const tinyconn_mux_map[] = { 646 "NONE", 647 "I2S0_CH1", 648 "I2S0_CH2", 649 "I2S6_CH1", 650 "I2S6_CH2", 651 "I2S8_CH1", 652 "I2S8_CH2", 653 }; 654 655 static int tinyconn_mux_map_value[] = { 656 TINYCONN_MUX_NONE, 657 TINYCONN_CH1_MUX_I2S0, 658 TINYCONN_CH2_MUX_I2S0, 659 TINYCONN_CH1_MUX_I2S6, 660 TINYCONN_CH2_MUX_I2S6, 661 TINYCONN_CH1_MUX_I2S8, 662 TINYCONN_CH2_MUX_I2S8, 663 }; 664 665 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch1_mux_map_enum, 666 AFE_TINY_CONN0, 667 O_2_CFG_SFT, 668 O_2_CFG_MASK, 669 tinyconn_mux_map, 670 tinyconn_mux_map_value); 671 static SOC_VALUE_ENUM_SINGLE_DECL(ul4_tinyconn_ch2_mux_map_enum, 672 AFE_TINY_CONN0, 673 O_3_CFG_SFT, 674 O_3_CFG_MASK, 675 tinyconn_mux_map, 676 tinyconn_mux_map_value); 677 678 static const struct snd_kcontrol_new ul4_tinyconn_ch1_mux_control = 679 SOC_DAPM_ENUM("UL4_TINYCONN_CH1_MUX", ul4_tinyconn_ch1_mux_map_enum); 680 static const struct snd_kcontrol_new ul4_tinyconn_ch2_mux_control = 681 SOC_DAPM_ENUM("UL4_TINYCONN_CH2_MUX", ul4_tinyconn_ch2_mux_map_enum); 682 683 static const struct snd_soc_dapm_widget mt8192_memif_widgets[] = { 684 /* inter-connections */ 685 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 686 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 687 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 688 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 689 SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0, 690 memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)), 691 SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0, 692 memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)), 693 694 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 695 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 696 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 697 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 698 699 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 700 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 701 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 702 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 703 704 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, 705 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), 706 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, 707 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), 708 SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH1_MUX", SND_SOC_NOPM, 0, 0, 709 &ul4_tinyconn_ch1_mux_control, 710 ul_tinyconn_event, 711 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 712 SND_SOC_DAPM_MUX_E("UL4_TINYCONN_CH2_MUX", SND_SOC_NOPM, 0, 0, 713 &ul4_tinyconn_ch2_mux_control, 714 ul_tinyconn_event, 715 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD), 716 717 SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0, 718 memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)), 719 SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0, 720 memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)), 721 722 SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0, 723 memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)), 724 SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0, 725 memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)), 726 727 SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0, 728 memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)), 729 SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0, 730 memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)), 731 732 SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0, 733 memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)), 734 SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0, 735 memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)), 736 737 SND_SOC_DAPM_MIXER("UL_MONO_1_CH1", SND_SOC_NOPM, 0, 0, 738 memif_ul_mono_1_mix, 739 ARRAY_SIZE(memif_ul_mono_1_mix)), 740 741 SND_SOC_DAPM_MIXER("UL_MONO_2_CH1", SND_SOC_NOPM, 0, 0, 742 memif_ul_mono_2_mix, 743 ARRAY_SIZE(memif_ul_mono_2_mix)), 744 745 SND_SOC_DAPM_MIXER("UL_MONO_3_CH1", SND_SOC_NOPM, 0, 0, 746 memif_ul_mono_3_mix, 747 ARRAY_SIZE(memif_ul_mono_3_mix)), 748 749 SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"), 750 SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"), 751 SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"), 752 }; 753 754 static const struct snd_soc_dapm_route mt8192_memif_routes[] = { 755 {"UL1", NULL, "UL1_CH1"}, 756 {"UL1", NULL, "UL1_CH2"}, 757 {"UL1", NULL, "UL1_CH3"}, 758 {"UL1", NULL, "UL1_CH4"}, 759 {"UL1_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 760 {"UL1_CH1", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 761 {"UL1_CH1", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 762 {"UL1_CH2", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 763 {"UL1_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 764 {"UL1_CH2", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 765 {"UL1_CH2", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 766 {"UL1_CH3", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 767 {"UL1_CH3", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 768 {"UL1_CH3", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 769 {"UL1_CH4", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 770 {"UL1_CH4", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 771 {"UL1_CH4", "ADDA_UL_CH3", "ADDA_CH34_UL_Mux"}, 772 {"UL1_CH4", "ADDA_UL_CH4", "ADDA_CH34_UL_Mux"}, 773 774 {"UL2", NULL, "UL2_CH1"}, 775 {"UL2", NULL, "UL2_CH2"}, 776 {"UL2_CH1", "I2S0_CH1", "I2S0"}, 777 {"UL2_CH2", "I2S0_CH2", "I2S0"}, 778 {"UL2_CH1", "I2S2_CH1", "I2S2"}, 779 {"UL2_CH2", "I2S2_CH2", "I2S2"}, 780 {"UL2_CH1", "I2S6_CH1", "I2S6"}, 781 {"UL2_CH2", "I2S6_CH2", "I2S6"}, 782 {"UL2_CH1", "I2S8_CH1", "I2S8"}, 783 {"UL2_CH2", "I2S8_CH2", "I2S8"}, 784 785 {"UL2_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"}, 786 {"UL2_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"}, 787 {"UL2_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"}, 788 {"UL2_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"}, 789 790 {"UL_MONO_1", NULL, "UL_MONO_1_CH1"}, 791 {"UL_MONO_1_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"}, 792 {"UL_MONO_1_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"}, 793 794 {"UL_MONO_2", NULL, "UL_MONO_2_CH1"}, 795 {"UL_MONO_2_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 796 797 {"UL_MONO_3", NULL, "UL_MONO_3_CH1"}, 798 {"UL_MONO_3_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 799 800 {"UL2_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"}, 801 {"UL2_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"}, 802 803 {"UL3", NULL, "UL3_CH1"}, 804 {"UL3", NULL, "UL3_CH2"}, 805 {"UL3_CH1", "CONNSYS_I2S_CH1", "Connsys I2S"}, 806 {"UL3_CH2", "CONNSYS_I2S_CH2", "Connsys I2S"}, 807 808 {"UL4", NULL, "UL4_CH1"}, 809 {"UL4", NULL, "UL4_CH2"}, 810 {"UL4", NULL, "UL4_TINYCONN_CH1_MUX"}, 811 {"UL4", NULL, "UL4_TINYCONN_CH2_MUX"}, 812 {"UL4_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 813 {"UL4_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 814 {"UL4_CH1", "I2S0_CH1", "I2S0"}, 815 {"UL4_CH2", "I2S0_CH2", "I2S0"}, 816 {"UL4_TINYCONN_CH1_MUX", "I2S0_CH1", "I2S0"}, 817 {"UL4_TINYCONN_CH2_MUX", "I2S0_CH2", "I2S0"}, 818 819 {"UL5", NULL, "UL5_CH1"}, 820 {"UL5", NULL, "UL5_CH2"}, 821 {"UL5_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 822 {"UL5_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 823 824 {"UL6", NULL, "UL6_CH1"}, 825 {"UL6", NULL, "UL6_CH2"}, 826 827 {"UL6_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 828 {"UL6_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 829 {"UL6_CH1", "PCM_1_CAP_CH1", "PCM 1 Capture"}, 830 {"UL6_CH2", "PCM_1_CAP_CH1", "PCM 1 Capture"}, 831 {"UL6_CH1", "PCM_2_CAP_CH1", "PCM 2 Capture"}, 832 {"UL6_CH2", "PCM_2_CAP_CH1", "PCM 2 Capture"}, 833 834 {"UL7", NULL, "UL7_CH1"}, 835 {"UL7", NULL, "UL7_CH2"}, 836 {"UL7_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 837 {"UL7_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 838 839 {"UL8", NULL, "UL8_CH1"}, 840 {"UL8", NULL, "UL8_CH2"}, 841 {"UL8_CH1", "ADDA_UL_CH1", "ADDA_UL_Mux"}, 842 {"UL8_CH2", "ADDA_UL_CH2", "ADDA_UL_Mux"}, 843 }; 844 845 static const struct mtk_base_memif_data memif_data[MT8192_MEMIF_NUM] = { 846 [MT8192_MEMIF_DL1] = { 847 .name = "DL1", 848 .id = MT8192_MEMIF_DL1, 849 .reg_ofs_base = AFE_DL1_BASE, 850 .reg_ofs_cur = AFE_DL1_CUR, 851 .reg_ofs_end = AFE_DL1_END, 852 .reg_ofs_base_msb = AFE_DL1_BASE_MSB, 853 .reg_ofs_cur_msb = AFE_DL1_CUR_MSB, 854 .reg_ofs_end_msb = AFE_DL1_END_MSB, 855 .fs_reg = AFE_DL1_CON0, 856 .fs_shift = DL1_MODE_SFT, 857 .fs_maskbit = DL1_MODE_MASK, 858 .mono_reg = AFE_DL1_CON0, 859 .mono_shift = DL1_MONO_SFT, 860 .enable_reg = AFE_DAC_CON0, 861 .enable_shift = DL1_ON_SFT, 862 .hd_reg = AFE_DL1_CON0, 863 .hd_shift = DL1_HD_MODE_SFT, 864 .hd_align_reg = AFE_DL1_CON0, 865 .hd_align_mshift = DL1_HALIGN_SFT, 866 .pbuf_reg = AFE_DL1_CON0, 867 .pbuf_shift = DL1_PBUF_SIZE_SFT, 868 .minlen_reg = AFE_DL1_CON0, 869 .minlen_shift = DL1_MINLEN_SFT, 870 }, 871 [MT8192_MEMIF_DL12] = { 872 .name = "DL12", 873 .id = MT8192_MEMIF_DL12, 874 .reg_ofs_base = AFE_DL12_BASE, 875 .reg_ofs_cur = AFE_DL12_CUR, 876 .reg_ofs_end = AFE_DL12_END, 877 .reg_ofs_base_msb = AFE_DL12_BASE_MSB, 878 .reg_ofs_cur_msb = AFE_DL12_CUR_MSB, 879 .reg_ofs_end_msb = AFE_DL12_END_MSB, 880 .fs_reg = AFE_DL12_CON0, 881 .fs_shift = DL12_MODE_SFT, 882 .fs_maskbit = DL12_MODE_MASK, 883 .mono_reg = AFE_DL12_CON0, 884 .mono_shift = DL12_MONO_SFT, 885 .enable_reg = AFE_DAC_CON0, 886 .enable_shift = DL12_ON_SFT, 887 .hd_reg = AFE_DL12_CON0, 888 .hd_shift = DL12_HD_MODE_SFT, 889 .hd_align_reg = AFE_DL12_CON0, 890 .hd_align_mshift = DL12_HALIGN_SFT, 891 .pbuf_reg = AFE_DL12_CON0, 892 .pbuf_shift = DL12_PBUF_SIZE_SFT, 893 .minlen_reg = AFE_DL12_CON0, 894 .minlen_shift = DL12_MINLEN_SFT, 895 }, 896 [MT8192_MEMIF_DL2] = { 897 .name = "DL2", 898 .id = MT8192_MEMIF_DL2, 899 .reg_ofs_base = AFE_DL2_BASE, 900 .reg_ofs_cur = AFE_DL2_CUR, 901 .reg_ofs_end = AFE_DL2_END, 902 .reg_ofs_base_msb = AFE_DL2_BASE_MSB, 903 .reg_ofs_cur_msb = AFE_DL2_CUR_MSB, 904 .reg_ofs_end_msb = AFE_DL2_END_MSB, 905 .fs_reg = AFE_DL2_CON0, 906 .fs_shift = DL2_MODE_SFT, 907 .fs_maskbit = DL2_MODE_MASK, 908 .mono_reg = AFE_DL2_CON0, 909 .mono_shift = DL2_MONO_SFT, 910 .enable_reg = AFE_DAC_CON0, 911 .enable_shift = DL2_ON_SFT, 912 .hd_reg = AFE_DL2_CON0, 913 .hd_shift = DL2_HD_MODE_SFT, 914 .hd_align_reg = AFE_DL2_CON0, 915 .hd_align_mshift = DL2_HALIGN_SFT, 916 .pbuf_reg = AFE_DL2_CON0, 917 .pbuf_shift = DL2_PBUF_SIZE_SFT, 918 .minlen_reg = AFE_DL2_CON0, 919 .minlen_shift = DL2_MINLEN_SFT, 920 }, 921 [MT8192_MEMIF_DL3] = { 922 .name = "DL3", 923 .id = MT8192_MEMIF_DL3, 924 .reg_ofs_base = AFE_DL3_BASE, 925 .reg_ofs_cur = AFE_DL3_CUR, 926 .reg_ofs_end = AFE_DL3_END, 927 .reg_ofs_base_msb = AFE_DL3_BASE_MSB, 928 .reg_ofs_cur_msb = AFE_DL3_CUR_MSB, 929 .reg_ofs_end_msb = AFE_DL3_END_MSB, 930 .fs_reg = AFE_DL3_CON0, 931 .fs_shift = DL3_MODE_SFT, 932 .fs_maskbit = DL3_MODE_MASK, 933 .mono_reg = AFE_DL3_CON0, 934 .mono_shift = DL3_MONO_SFT, 935 .enable_reg = AFE_DAC_CON0, 936 .enable_shift = DL3_ON_SFT, 937 .hd_reg = AFE_DL3_CON0, 938 .hd_shift = DL3_HD_MODE_SFT, 939 .hd_align_reg = AFE_DL3_CON0, 940 .hd_align_mshift = DL3_HALIGN_SFT, 941 .pbuf_reg = AFE_DL3_CON0, 942 .pbuf_shift = DL3_PBUF_SIZE_SFT, 943 .minlen_reg = AFE_DL3_CON0, 944 .minlen_shift = DL3_MINLEN_SFT, 945 }, 946 [MT8192_MEMIF_DL4] = { 947 .name = "DL4", 948 .id = MT8192_MEMIF_DL4, 949 .reg_ofs_base = AFE_DL4_BASE, 950 .reg_ofs_cur = AFE_DL4_CUR, 951 .reg_ofs_end = AFE_DL4_END, 952 .reg_ofs_base_msb = AFE_DL4_BASE_MSB, 953 .reg_ofs_cur_msb = AFE_DL4_CUR_MSB, 954 .reg_ofs_end_msb = AFE_DL4_END_MSB, 955 .fs_reg = AFE_DL4_CON0, 956 .fs_shift = DL4_MODE_SFT, 957 .fs_maskbit = DL4_MODE_MASK, 958 .mono_reg = AFE_DL4_CON0, 959 .mono_shift = DL4_MONO_SFT, 960 .enable_reg = AFE_DAC_CON0, 961 .enable_shift = DL4_ON_SFT, 962 .hd_reg = AFE_DL4_CON0, 963 .hd_shift = DL4_HD_MODE_SFT, 964 .hd_align_reg = AFE_DL4_CON0, 965 .hd_align_mshift = DL4_HALIGN_SFT, 966 .pbuf_reg = AFE_DL4_CON0, 967 .pbuf_shift = DL4_PBUF_SIZE_SFT, 968 .minlen_reg = AFE_DL4_CON0, 969 .minlen_shift = DL4_MINLEN_SFT, 970 }, 971 [MT8192_MEMIF_DL5] = { 972 .name = "DL5", 973 .id = MT8192_MEMIF_DL5, 974 .reg_ofs_base = AFE_DL5_BASE, 975 .reg_ofs_cur = AFE_DL5_CUR, 976 .reg_ofs_end = AFE_DL5_END, 977 .reg_ofs_base_msb = AFE_DL5_BASE_MSB, 978 .reg_ofs_cur_msb = AFE_DL5_CUR_MSB, 979 .reg_ofs_end_msb = AFE_DL5_END_MSB, 980 .fs_reg = AFE_DL5_CON0, 981 .fs_shift = DL5_MODE_SFT, 982 .fs_maskbit = DL5_MODE_MASK, 983 .mono_reg = AFE_DL5_CON0, 984 .mono_shift = DL5_MONO_SFT, 985 .enable_reg = AFE_DAC_CON0, 986 .enable_shift = DL5_ON_SFT, 987 .hd_reg = AFE_DL5_CON0, 988 .hd_shift = DL5_HD_MODE_SFT, 989 .hd_align_reg = AFE_DL5_CON0, 990 .hd_align_mshift = DL5_HALIGN_SFT, 991 .pbuf_reg = AFE_DL5_CON0, 992 .pbuf_shift = DL5_PBUF_SIZE_SFT, 993 .minlen_reg = AFE_DL5_CON0, 994 .minlen_shift = DL5_MINLEN_SFT, 995 }, 996 [MT8192_MEMIF_DL6] = { 997 .name = "DL6", 998 .id = MT8192_MEMIF_DL6, 999 .reg_ofs_base = AFE_DL6_BASE, 1000 .reg_ofs_cur = AFE_DL6_CUR, 1001 .reg_ofs_end = AFE_DL6_END, 1002 .reg_ofs_base_msb = AFE_DL6_BASE_MSB, 1003 .reg_ofs_cur_msb = AFE_DL6_CUR_MSB, 1004 .reg_ofs_end_msb = AFE_DL6_END_MSB, 1005 .fs_reg = AFE_DL6_CON0, 1006 .fs_shift = DL6_MODE_SFT, 1007 .fs_maskbit = DL6_MODE_MASK, 1008 .mono_reg = AFE_DL6_CON0, 1009 .mono_shift = DL6_MONO_SFT, 1010 .enable_reg = AFE_DAC_CON0, 1011 .enable_shift = DL6_ON_SFT, 1012 .hd_reg = AFE_DL6_CON0, 1013 .hd_shift = DL6_HD_MODE_SFT, 1014 .hd_align_reg = AFE_DL6_CON0, 1015 .hd_align_mshift = DL6_HALIGN_SFT, 1016 .pbuf_reg = AFE_DL6_CON0, 1017 .pbuf_shift = DL6_PBUF_SIZE_SFT, 1018 .minlen_reg = AFE_DL6_CON0, 1019 .minlen_shift = DL6_MINLEN_SFT, 1020 }, 1021 [MT8192_MEMIF_DL7] = { 1022 .name = "DL7", 1023 .id = MT8192_MEMIF_DL7, 1024 .reg_ofs_base = AFE_DL7_BASE, 1025 .reg_ofs_cur = AFE_DL7_CUR, 1026 .reg_ofs_end = AFE_DL7_END, 1027 .reg_ofs_base_msb = AFE_DL7_BASE_MSB, 1028 .reg_ofs_cur_msb = AFE_DL7_CUR_MSB, 1029 .reg_ofs_end_msb = AFE_DL7_END_MSB, 1030 .fs_reg = AFE_DL7_CON0, 1031 .fs_shift = DL7_MODE_SFT, 1032 .fs_maskbit = DL7_MODE_MASK, 1033 .mono_reg = AFE_DL7_CON0, 1034 .mono_shift = DL7_MONO_SFT, 1035 .enable_reg = AFE_DAC_CON0, 1036 .enable_shift = DL7_ON_SFT, 1037 .hd_reg = AFE_DL7_CON0, 1038 .hd_shift = DL7_HD_MODE_SFT, 1039 .hd_align_reg = AFE_DL7_CON0, 1040 .hd_align_mshift = DL7_HALIGN_SFT, 1041 .pbuf_reg = AFE_DL7_CON0, 1042 .pbuf_shift = DL7_PBUF_SIZE_SFT, 1043 .minlen_reg = AFE_DL7_CON0, 1044 .minlen_shift = DL7_MINLEN_SFT, 1045 }, 1046 [MT8192_MEMIF_DL8] = { 1047 .name = "DL8", 1048 .id = MT8192_MEMIF_DL8, 1049 .reg_ofs_base = AFE_DL8_BASE, 1050 .reg_ofs_cur = AFE_DL8_CUR, 1051 .reg_ofs_end = AFE_DL8_END, 1052 .reg_ofs_base_msb = AFE_DL8_BASE_MSB, 1053 .reg_ofs_cur_msb = AFE_DL8_CUR_MSB, 1054 .reg_ofs_end_msb = AFE_DL8_END_MSB, 1055 .fs_reg = AFE_DL8_CON0, 1056 .fs_shift = DL8_MODE_SFT, 1057 .fs_maskbit = DL8_MODE_MASK, 1058 .mono_reg = AFE_DL8_CON0, 1059 .mono_shift = DL8_MONO_SFT, 1060 .enable_reg = AFE_DAC_CON0, 1061 .enable_shift = DL8_ON_SFT, 1062 .hd_reg = AFE_DL8_CON0, 1063 .hd_shift = DL8_HD_MODE_SFT, 1064 .hd_align_reg = AFE_DL8_CON0, 1065 .hd_align_mshift = DL8_HALIGN_SFT, 1066 .pbuf_reg = AFE_DL8_CON0, 1067 .pbuf_shift = DL8_PBUF_SIZE_SFT, 1068 .minlen_reg = AFE_DL8_CON0, 1069 .minlen_shift = DL8_MINLEN_SFT, 1070 }, 1071 [MT8192_MEMIF_DL9] = { 1072 .name = "DL9", 1073 .id = MT8192_MEMIF_DL9, 1074 .reg_ofs_base = AFE_DL9_BASE, 1075 .reg_ofs_cur = AFE_DL9_CUR, 1076 .reg_ofs_end = AFE_DL9_END, 1077 .reg_ofs_base_msb = AFE_DL9_BASE_MSB, 1078 .reg_ofs_cur_msb = AFE_DL9_CUR_MSB, 1079 .reg_ofs_end_msb = AFE_DL9_END_MSB, 1080 .fs_reg = AFE_DL9_CON0, 1081 .fs_shift = DL9_MODE_SFT, 1082 .fs_maskbit = DL9_MODE_MASK, 1083 .mono_reg = AFE_DL9_CON0, 1084 .mono_shift = DL9_MONO_SFT, 1085 .enable_reg = AFE_DAC_CON0, 1086 .enable_shift = DL9_ON_SFT, 1087 .hd_reg = AFE_DL9_CON0, 1088 .hd_shift = DL9_HD_MODE_SFT, 1089 .hd_align_reg = AFE_DL9_CON0, 1090 .hd_align_mshift = DL9_HALIGN_SFT, 1091 .pbuf_reg = AFE_DL9_CON0, 1092 .pbuf_shift = DL9_PBUF_SIZE_SFT, 1093 .minlen_reg = AFE_DL9_CON0, 1094 .minlen_shift = DL9_MINLEN_SFT, 1095 }, 1096 [MT8192_MEMIF_DAI] = { 1097 .name = "DAI", 1098 .id = MT8192_MEMIF_DAI, 1099 .reg_ofs_base = AFE_DAI_BASE, 1100 .reg_ofs_cur = AFE_DAI_CUR, 1101 .reg_ofs_end = AFE_DAI_END, 1102 .reg_ofs_base_msb = AFE_DAI_BASE_MSB, 1103 .reg_ofs_cur_msb = AFE_DAI_CUR_MSB, 1104 .reg_ofs_end_msb = AFE_DAI_END_MSB, 1105 .fs_reg = AFE_DAI_CON0, 1106 .fs_shift = DAI_MODE_SFT, 1107 .fs_maskbit = DAI_MODE_MASK, 1108 .mono_reg = AFE_DAI_CON0, 1109 .mono_shift = DAI_DUPLICATE_WR_SFT, 1110 .mono_invert = 1, 1111 .enable_reg = AFE_DAC_CON0, 1112 .enable_shift = DAI_ON_SFT, 1113 .hd_reg = AFE_DAI_CON0, 1114 .hd_shift = DAI_HD_MODE_SFT, 1115 .hd_align_reg = AFE_DAI_CON0, 1116 .hd_align_mshift = DAI_HALIGN_SFT, 1117 }, 1118 [MT8192_MEMIF_MOD_DAI] = { 1119 .name = "MOD_DAI", 1120 .id = MT8192_MEMIF_MOD_DAI, 1121 .reg_ofs_base = AFE_MOD_DAI_BASE, 1122 .reg_ofs_cur = AFE_MOD_DAI_CUR, 1123 .reg_ofs_end = AFE_MOD_DAI_END, 1124 .reg_ofs_base_msb = AFE_MOD_DAI_BASE_MSB, 1125 .reg_ofs_cur_msb = AFE_MOD_DAI_CUR_MSB, 1126 .reg_ofs_end_msb = AFE_MOD_DAI_END_MSB, 1127 .fs_reg = AFE_MOD_DAI_CON0, 1128 .fs_shift = MOD_DAI_MODE_SFT, 1129 .fs_maskbit = MOD_DAI_MODE_MASK, 1130 .mono_reg = AFE_MOD_DAI_CON0, 1131 .mono_shift = MOD_DAI_DUPLICATE_WR_SFT, 1132 .mono_invert = 1, 1133 .enable_reg = AFE_DAC_CON0, 1134 .enable_shift = MOD_DAI_ON_SFT, 1135 .hd_reg = AFE_MOD_DAI_CON0, 1136 .hd_shift = MOD_DAI_HD_MODE_SFT, 1137 .hd_align_reg = AFE_MOD_DAI_CON0, 1138 .hd_align_mshift = MOD_DAI_HALIGN_SFT, 1139 }, 1140 [MT8192_MEMIF_DAI2] = { 1141 .name = "DAI2", 1142 .id = MT8192_MEMIF_DAI2, 1143 .reg_ofs_base = AFE_DAI2_BASE, 1144 .reg_ofs_cur = AFE_DAI2_CUR, 1145 .reg_ofs_end = AFE_DAI2_END, 1146 .reg_ofs_base_msb = AFE_DAI2_BASE_MSB, 1147 .reg_ofs_cur_msb = AFE_DAI2_CUR_MSB, 1148 .reg_ofs_end_msb = AFE_DAI2_END_MSB, 1149 .fs_reg = AFE_DAI2_CON0, 1150 .fs_shift = DAI2_MODE_SFT, 1151 .fs_maskbit = DAI2_MODE_MASK, 1152 .mono_reg = AFE_DAI2_CON0, 1153 .mono_shift = DAI2_DUPLICATE_WR_SFT, 1154 .mono_invert = 1, 1155 .enable_reg = AFE_DAC_CON0, 1156 .enable_shift = DAI2_ON_SFT, 1157 .hd_reg = AFE_DAI2_CON0, 1158 .hd_shift = DAI2_HD_MODE_SFT, 1159 .hd_align_reg = AFE_DAI2_CON0, 1160 .hd_align_mshift = DAI2_HALIGN_SFT, 1161 }, 1162 [MT8192_MEMIF_VUL12] = { 1163 .name = "VUL12", 1164 .id = MT8192_MEMIF_VUL12, 1165 .reg_ofs_base = AFE_VUL12_BASE, 1166 .reg_ofs_cur = AFE_VUL12_CUR, 1167 .reg_ofs_end = AFE_VUL12_END, 1168 .reg_ofs_base_msb = AFE_VUL12_BASE_MSB, 1169 .reg_ofs_cur_msb = AFE_VUL12_CUR_MSB, 1170 .reg_ofs_end_msb = AFE_VUL12_END_MSB, 1171 .fs_reg = AFE_VUL12_CON0, 1172 .fs_shift = VUL12_MODE_SFT, 1173 .fs_maskbit = VUL12_MODE_MASK, 1174 .mono_reg = AFE_VUL12_CON0, 1175 .mono_shift = VUL12_MONO_SFT, 1176 .quad_ch_reg = AFE_VUL12_CON0, 1177 .quad_ch_shift = VUL12_4CH_EN_SFT, 1178 .quad_ch_mask = VUL12_4CH_EN_MASK, 1179 .enable_reg = AFE_DAC_CON0, 1180 .enable_shift = VUL12_ON_SFT, 1181 .hd_reg = AFE_VUL12_CON0, 1182 .hd_shift = VUL12_HD_MODE_SFT, 1183 .hd_align_reg = AFE_VUL12_CON0, 1184 .hd_align_mshift = VUL12_HALIGN_SFT, 1185 }, 1186 [MT8192_MEMIF_VUL2] = { 1187 .name = "VUL2", 1188 .id = MT8192_MEMIF_VUL2, 1189 .reg_ofs_base = AFE_VUL2_BASE, 1190 .reg_ofs_cur = AFE_VUL2_CUR, 1191 .reg_ofs_end = AFE_VUL2_END, 1192 .reg_ofs_base_msb = AFE_VUL2_BASE_MSB, 1193 .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB, 1194 .reg_ofs_end_msb = AFE_VUL2_END_MSB, 1195 .fs_reg = AFE_VUL2_CON0, 1196 .fs_shift = VUL2_MODE_SFT, 1197 .fs_maskbit = VUL2_MODE_MASK, 1198 .mono_reg = AFE_VUL2_CON0, 1199 .mono_shift = VUL2_MONO_SFT, 1200 .enable_reg = AFE_DAC_CON0, 1201 .enable_shift = VUL2_ON_SFT, 1202 .hd_reg = AFE_VUL2_CON0, 1203 .hd_shift = VUL2_HD_MODE_SFT, 1204 .hd_align_reg = AFE_VUL2_CON0, 1205 .hd_align_mshift = VUL2_HALIGN_SFT, 1206 }, 1207 [MT8192_MEMIF_AWB] = { 1208 .name = "AWB", 1209 .id = MT8192_MEMIF_AWB, 1210 .reg_ofs_base = AFE_AWB_BASE, 1211 .reg_ofs_cur = AFE_AWB_CUR, 1212 .reg_ofs_end = AFE_AWB_END, 1213 .reg_ofs_base_msb = AFE_AWB_BASE_MSB, 1214 .reg_ofs_cur_msb = AFE_AWB_CUR_MSB, 1215 .reg_ofs_end_msb = AFE_AWB_END_MSB, 1216 .fs_reg = AFE_AWB_CON0, 1217 .fs_shift = AWB_MODE_SFT, 1218 .fs_maskbit = AWB_MODE_MASK, 1219 .mono_reg = AFE_AWB_CON0, 1220 .mono_shift = AWB_MONO_SFT, 1221 .enable_reg = AFE_DAC_CON0, 1222 .enable_shift = AWB_ON_SFT, 1223 .hd_reg = AFE_AWB_CON0, 1224 .hd_shift = AWB_HD_MODE_SFT, 1225 .hd_align_reg = AFE_AWB_CON0, 1226 .hd_align_mshift = AWB_HALIGN_SFT, 1227 }, 1228 [MT8192_MEMIF_AWB2] = { 1229 .name = "AWB2", 1230 .id = MT8192_MEMIF_AWB2, 1231 .reg_ofs_base = AFE_AWB2_BASE, 1232 .reg_ofs_cur = AFE_AWB2_CUR, 1233 .reg_ofs_end = AFE_AWB2_END, 1234 .reg_ofs_base_msb = AFE_AWB2_BASE_MSB, 1235 .reg_ofs_cur_msb = AFE_AWB2_CUR_MSB, 1236 .reg_ofs_end_msb = AFE_AWB2_END_MSB, 1237 .fs_reg = AFE_AWB2_CON0, 1238 .fs_shift = AWB2_MODE_SFT, 1239 .fs_maskbit = AWB2_MODE_MASK, 1240 .mono_reg = AFE_AWB2_CON0, 1241 .mono_shift = AWB2_MONO_SFT, 1242 .enable_reg = AFE_DAC_CON0, 1243 .enable_shift = AWB2_ON_SFT, 1244 .hd_reg = AFE_AWB2_CON0, 1245 .hd_shift = AWB2_HD_MODE_SFT, 1246 .hd_align_reg = AFE_AWB2_CON0, 1247 .hd_align_mshift = AWB2_HALIGN_SFT, 1248 }, 1249 [MT8192_MEMIF_VUL3] = { 1250 .name = "VUL3", 1251 .id = MT8192_MEMIF_VUL3, 1252 .reg_ofs_base = AFE_VUL3_BASE, 1253 .reg_ofs_cur = AFE_VUL3_CUR, 1254 .reg_ofs_end = AFE_VUL3_END, 1255 .reg_ofs_base_msb = AFE_VUL3_BASE_MSB, 1256 .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB, 1257 .reg_ofs_end_msb = AFE_VUL3_END_MSB, 1258 .fs_reg = AFE_VUL3_CON0, 1259 .fs_shift = VUL3_MODE_SFT, 1260 .fs_maskbit = VUL3_MODE_MASK, 1261 .mono_reg = AFE_VUL3_CON0, 1262 .mono_shift = VUL3_MONO_SFT, 1263 .enable_reg = AFE_DAC_CON0, 1264 .enable_shift = VUL3_ON_SFT, 1265 .hd_reg = AFE_VUL3_CON0, 1266 .hd_shift = VUL3_HD_MODE_SFT, 1267 .hd_align_reg = AFE_VUL3_CON0, 1268 .hd_align_mshift = VUL3_HALIGN_SFT, 1269 }, 1270 [MT8192_MEMIF_VUL4] = { 1271 .name = "VUL4", 1272 .id = MT8192_MEMIF_VUL4, 1273 .reg_ofs_base = AFE_VUL4_BASE, 1274 .reg_ofs_cur = AFE_VUL4_CUR, 1275 .reg_ofs_end = AFE_VUL4_END, 1276 .reg_ofs_base_msb = AFE_VUL4_BASE_MSB, 1277 .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB, 1278 .reg_ofs_end_msb = AFE_VUL4_END_MSB, 1279 .fs_reg = AFE_VUL4_CON0, 1280 .fs_shift = VUL4_MODE_SFT, 1281 .fs_maskbit = VUL4_MODE_MASK, 1282 .mono_reg = AFE_VUL4_CON0, 1283 .mono_shift = VUL4_MONO_SFT, 1284 .enable_reg = AFE_DAC_CON0, 1285 .enable_shift = VUL4_ON_SFT, 1286 .hd_reg = AFE_VUL4_CON0, 1287 .hd_shift = VUL4_HD_MODE_SFT, 1288 .hd_align_reg = AFE_VUL4_CON0, 1289 .hd_align_mshift = VUL4_HALIGN_SFT, 1290 }, 1291 [MT8192_MEMIF_VUL5] = { 1292 .name = "VUL5", 1293 .id = MT8192_MEMIF_VUL5, 1294 .reg_ofs_base = AFE_VUL5_BASE, 1295 .reg_ofs_cur = AFE_VUL5_CUR, 1296 .reg_ofs_end = AFE_VUL5_END, 1297 .reg_ofs_base_msb = AFE_VUL5_BASE_MSB, 1298 .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB, 1299 .reg_ofs_end_msb = AFE_VUL5_END_MSB, 1300 .fs_reg = AFE_VUL5_CON0, 1301 .fs_shift = VUL5_MODE_SFT, 1302 .fs_maskbit = VUL5_MODE_MASK, 1303 .mono_reg = AFE_VUL5_CON0, 1304 .mono_shift = VUL5_MONO_SFT, 1305 .enable_reg = AFE_DAC_CON0, 1306 .enable_shift = VUL5_ON_SFT, 1307 .hd_reg = AFE_VUL5_CON0, 1308 .hd_shift = VUL5_HD_MODE_SFT, 1309 .hd_align_reg = AFE_VUL5_CON0, 1310 .hd_align_mshift = VUL5_HALIGN_SFT, 1311 }, 1312 [MT8192_MEMIF_VUL6] = { 1313 .name = "VUL6", 1314 .id = MT8192_MEMIF_VUL6, 1315 .reg_ofs_base = AFE_VUL6_BASE, 1316 .reg_ofs_cur = AFE_VUL6_CUR, 1317 .reg_ofs_end = AFE_VUL6_END, 1318 .reg_ofs_base_msb = AFE_VUL6_BASE_MSB, 1319 .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB, 1320 .reg_ofs_end_msb = AFE_VUL6_END_MSB, 1321 .fs_reg = AFE_VUL6_CON0, 1322 .fs_shift = VUL6_MODE_SFT, 1323 .fs_maskbit = VUL6_MODE_MASK, 1324 .mono_reg = AFE_VUL6_CON0, 1325 .mono_shift = VUL6_MONO_SFT, 1326 .enable_reg = AFE_DAC_CON0, 1327 .enable_shift = VUL6_ON_SFT, 1328 .hd_reg = AFE_VUL6_CON0, 1329 .hd_shift = VUL6_HD_MODE_SFT, 1330 .hd_align_reg = AFE_VUL6_CON0, 1331 .hd_align_mshift = VUL6_HALIGN_SFT, 1332 }, 1333 [MT8192_MEMIF_HDMI] = { 1334 .name = "HDMI", 1335 .id = MT8192_MEMIF_HDMI, 1336 .reg_ofs_base = AFE_HDMI_OUT_BASE, 1337 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 1338 .reg_ofs_end = AFE_HDMI_OUT_END, 1339 .reg_ofs_base_msb = AFE_HDMI_OUT_BASE_MSB, 1340 .reg_ofs_cur_msb = AFE_HDMI_OUT_CUR_MSB, 1341 .reg_ofs_end_msb = AFE_HDMI_OUT_END_MSB, 1342 .fs_reg = -1, 1343 .fs_shift = -1, 1344 .fs_maskbit = -1, 1345 .mono_reg = -1, 1346 .mono_shift = -1, 1347 .enable_reg = AFE_DAC_CON0, 1348 .enable_shift = HDMI_OUT_ON_SFT, 1349 .hd_reg = AFE_HDMI_OUT_CON0, 1350 .hd_shift = HDMI_OUT_HD_MODE_SFT, 1351 .hd_align_reg = AFE_HDMI_OUT_CON0, 1352 .hd_align_mshift = HDMI_OUT_HALIGN_SFT, 1353 .pbuf_reg = AFE_HDMI_OUT_CON0, 1354 .minlen_reg = AFE_HDMI_OUT_CON0, 1355 .minlen_shift = HDMI_OUT_MINLEN_SFT, 1356 }, 1357 }; 1358 1359 static const struct mtk_base_irq_data irq_data[MT8192_IRQ_NUM] = { 1360 [MT8192_IRQ_0] = { 1361 .id = MT8192_IRQ_0, 1362 .irq_cnt_reg = AFE_IRQ_MCU_CNT0, 1363 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1364 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1365 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1366 .irq_fs_shift = IRQ0_MCU_MODE_SFT, 1367 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK, 1368 .irq_en_reg = AFE_IRQ_MCU_CON0, 1369 .irq_en_shift = IRQ0_MCU_ON_SFT, 1370 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1371 .irq_clr_shift = IRQ0_MCU_CLR_SFT, 1372 }, 1373 [MT8192_IRQ_1] = { 1374 .id = MT8192_IRQ_1, 1375 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 1376 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1377 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1378 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1379 .irq_fs_shift = IRQ1_MCU_MODE_SFT, 1380 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK, 1381 .irq_en_reg = AFE_IRQ_MCU_CON0, 1382 .irq_en_shift = IRQ1_MCU_ON_SFT, 1383 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1384 .irq_clr_shift = IRQ1_MCU_CLR_SFT, 1385 }, 1386 [MT8192_IRQ_2] = { 1387 .id = MT8192_IRQ_2, 1388 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 1389 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1390 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1391 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1392 .irq_fs_shift = IRQ2_MCU_MODE_SFT, 1393 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK, 1394 .irq_en_reg = AFE_IRQ_MCU_CON0, 1395 .irq_en_shift = IRQ2_MCU_ON_SFT, 1396 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1397 .irq_clr_shift = IRQ2_MCU_CLR_SFT, 1398 }, 1399 [MT8192_IRQ_3] = { 1400 .id = MT8192_IRQ_3, 1401 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 1402 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1403 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1404 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1405 .irq_fs_shift = IRQ3_MCU_MODE_SFT, 1406 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK, 1407 .irq_en_reg = AFE_IRQ_MCU_CON0, 1408 .irq_en_shift = IRQ3_MCU_ON_SFT, 1409 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1410 .irq_clr_shift = IRQ3_MCU_CLR_SFT, 1411 }, 1412 [MT8192_IRQ_4] = { 1413 .id = MT8192_IRQ_4, 1414 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 1415 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1416 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1417 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1418 .irq_fs_shift = IRQ4_MCU_MODE_SFT, 1419 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK, 1420 .irq_en_reg = AFE_IRQ_MCU_CON0, 1421 .irq_en_shift = IRQ4_MCU_ON_SFT, 1422 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1423 .irq_clr_shift = IRQ4_MCU_CLR_SFT, 1424 }, 1425 [MT8192_IRQ_5] = { 1426 .id = MT8192_IRQ_5, 1427 .irq_cnt_reg = AFE_IRQ_MCU_CNT5, 1428 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1429 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1430 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1431 .irq_fs_shift = IRQ5_MCU_MODE_SFT, 1432 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK, 1433 .irq_en_reg = AFE_IRQ_MCU_CON0, 1434 .irq_en_shift = IRQ5_MCU_ON_SFT, 1435 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1436 .irq_clr_shift = IRQ5_MCU_CLR_SFT, 1437 }, 1438 [MT8192_IRQ_6] = { 1439 .id = MT8192_IRQ_6, 1440 .irq_cnt_reg = AFE_IRQ_MCU_CNT6, 1441 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1442 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1443 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1444 .irq_fs_shift = IRQ6_MCU_MODE_SFT, 1445 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK, 1446 .irq_en_reg = AFE_IRQ_MCU_CON0, 1447 .irq_en_shift = IRQ6_MCU_ON_SFT, 1448 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1449 .irq_clr_shift = IRQ6_MCU_CLR_SFT, 1450 }, 1451 [MT8192_IRQ_7] = { 1452 .id = MT8192_IRQ_7, 1453 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 1454 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1455 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1456 .irq_fs_reg = AFE_IRQ_MCU_CON1, 1457 .irq_fs_shift = IRQ7_MCU_MODE_SFT, 1458 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK, 1459 .irq_en_reg = AFE_IRQ_MCU_CON0, 1460 .irq_en_shift = IRQ7_MCU_ON_SFT, 1461 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1462 .irq_clr_shift = IRQ7_MCU_CLR_SFT, 1463 }, 1464 [MT8192_IRQ_8] = { 1465 .id = MT8192_IRQ_8, 1466 .irq_cnt_reg = AFE_IRQ_MCU_CNT8, 1467 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1468 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1469 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1470 .irq_fs_shift = IRQ8_MCU_MODE_SFT, 1471 .irq_fs_maskbit = IRQ8_MCU_MODE_MASK, 1472 .irq_en_reg = AFE_IRQ_MCU_CON0, 1473 .irq_en_shift = IRQ8_MCU_ON_SFT, 1474 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1475 .irq_clr_shift = IRQ8_MCU_CLR_SFT, 1476 }, 1477 [MT8192_IRQ_9] = { 1478 .id = MT8192_IRQ_9, 1479 .irq_cnt_reg = AFE_IRQ_MCU_CNT9, 1480 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1481 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1482 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1483 .irq_fs_shift = IRQ9_MCU_MODE_SFT, 1484 .irq_fs_maskbit = IRQ9_MCU_MODE_MASK, 1485 .irq_en_reg = AFE_IRQ_MCU_CON0, 1486 .irq_en_shift = IRQ9_MCU_ON_SFT, 1487 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1488 .irq_clr_shift = IRQ9_MCU_CLR_SFT, 1489 }, 1490 [MT8192_IRQ_10] = { 1491 .id = MT8192_IRQ_10, 1492 .irq_cnt_reg = AFE_IRQ_MCU_CNT10, 1493 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1494 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1495 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1496 .irq_fs_shift = IRQ10_MCU_MODE_SFT, 1497 .irq_fs_maskbit = IRQ10_MCU_MODE_MASK, 1498 .irq_en_reg = AFE_IRQ_MCU_CON0, 1499 .irq_en_shift = IRQ10_MCU_ON_SFT, 1500 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1501 .irq_clr_shift = IRQ10_MCU_CLR_SFT, 1502 }, 1503 [MT8192_IRQ_11] = { 1504 .id = MT8192_IRQ_11, 1505 .irq_cnt_reg = AFE_IRQ_MCU_CNT11, 1506 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1507 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1508 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1509 .irq_fs_shift = IRQ11_MCU_MODE_SFT, 1510 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK, 1511 .irq_en_reg = AFE_IRQ_MCU_CON0, 1512 .irq_en_shift = IRQ11_MCU_ON_SFT, 1513 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1514 .irq_clr_shift = IRQ11_MCU_CLR_SFT, 1515 }, 1516 [MT8192_IRQ_12] = { 1517 .id = MT8192_IRQ_12, 1518 .irq_cnt_reg = AFE_IRQ_MCU_CNT12, 1519 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1520 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1521 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1522 .irq_fs_shift = IRQ12_MCU_MODE_SFT, 1523 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK, 1524 .irq_en_reg = AFE_IRQ_MCU_CON0, 1525 .irq_en_shift = IRQ12_MCU_ON_SFT, 1526 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1527 .irq_clr_shift = IRQ12_MCU_CLR_SFT, 1528 }, 1529 [MT8192_IRQ_13] = { 1530 .id = MT8192_IRQ_13, 1531 .irq_cnt_reg = AFE_IRQ_MCU_CNT13, 1532 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1533 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1534 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1535 .irq_fs_shift = IRQ13_MCU_MODE_SFT, 1536 .irq_fs_maskbit = IRQ13_MCU_MODE_MASK, 1537 .irq_en_reg = AFE_IRQ_MCU_CON0, 1538 .irq_en_shift = IRQ13_MCU_ON_SFT, 1539 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1540 .irq_clr_shift = IRQ13_MCU_CLR_SFT, 1541 }, 1542 [MT8192_IRQ_14] = { 1543 .id = MT8192_IRQ_14, 1544 .irq_cnt_reg = AFE_IRQ_MCU_CNT14, 1545 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1546 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1547 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1548 .irq_fs_shift = IRQ14_MCU_MODE_SFT, 1549 .irq_fs_maskbit = IRQ14_MCU_MODE_MASK, 1550 .irq_en_reg = AFE_IRQ_MCU_CON0, 1551 .irq_en_shift = IRQ14_MCU_ON_SFT, 1552 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1553 .irq_clr_shift = IRQ14_MCU_CLR_SFT, 1554 }, 1555 [MT8192_IRQ_15] = { 1556 .id = MT8192_IRQ_15, 1557 .irq_cnt_reg = AFE_IRQ_MCU_CNT15, 1558 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1559 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1560 .irq_fs_reg = AFE_IRQ_MCU_CON2, 1561 .irq_fs_shift = IRQ15_MCU_MODE_SFT, 1562 .irq_fs_maskbit = IRQ15_MCU_MODE_MASK, 1563 .irq_en_reg = AFE_IRQ_MCU_CON0, 1564 .irq_en_shift = IRQ15_MCU_ON_SFT, 1565 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1566 .irq_clr_shift = IRQ15_MCU_CLR_SFT, 1567 }, 1568 [MT8192_IRQ_16] = { 1569 .id = MT8192_IRQ_16, 1570 .irq_cnt_reg = AFE_IRQ_MCU_CNT16, 1571 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1572 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1573 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1574 .irq_fs_shift = IRQ16_MCU_MODE_SFT, 1575 .irq_fs_maskbit = IRQ16_MCU_MODE_MASK, 1576 .irq_en_reg = AFE_IRQ_MCU_CON0, 1577 .irq_en_shift = IRQ16_MCU_ON_SFT, 1578 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1579 .irq_clr_shift = IRQ16_MCU_CLR_SFT, 1580 }, 1581 [MT8192_IRQ_17] = { 1582 .id = MT8192_IRQ_17, 1583 .irq_cnt_reg = AFE_IRQ_MCU_CNT17, 1584 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1585 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1586 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1587 .irq_fs_shift = IRQ17_MCU_MODE_SFT, 1588 .irq_fs_maskbit = IRQ17_MCU_MODE_MASK, 1589 .irq_en_reg = AFE_IRQ_MCU_CON0, 1590 .irq_en_shift = IRQ17_MCU_ON_SFT, 1591 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1592 .irq_clr_shift = IRQ17_MCU_CLR_SFT, 1593 }, 1594 [MT8192_IRQ_18] = { 1595 .id = MT8192_IRQ_18, 1596 .irq_cnt_reg = AFE_IRQ_MCU_CNT18, 1597 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1598 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1599 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1600 .irq_fs_shift = IRQ18_MCU_MODE_SFT, 1601 .irq_fs_maskbit = IRQ18_MCU_MODE_MASK, 1602 .irq_en_reg = AFE_IRQ_MCU_CON0, 1603 .irq_en_shift = IRQ18_MCU_ON_SFT, 1604 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1605 .irq_clr_shift = IRQ18_MCU_CLR_SFT, 1606 }, 1607 [MT8192_IRQ_19] = { 1608 .id = MT8192_IRQ_19, 1609 .irq_cnt_reg = AFE_IRQ_MCU_CNT19, 1610 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1611 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1612 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1613 .irq_fs_shift = IRQ19_MCU_MODE_SFT, 1614 .irq_fs_maskbit = IRQ19_MCU_MODE_MASK, 1615 .irq_en_reg = AFE_IRQ_MCU_CON0, 1616 .irq_en_shift = IRQ19_MCU_ON_SFT, 1617 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1618 .irq_clr_shift = IRQ19_MCU_CLR_SFT, 1619 }, 1620 [MT8192_IRQ_20] = { 1621 .id = MT8192_IRQ_20, 1622 .irq_cnt_reg = AFE_IRQ_MCU_CNT20, 1623 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1624 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1625 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1626 .irq_fs_shift = IRQ20_MCU_MODE_SFT, 1627 .irq_fs_maskbit = IRQ20_MCU_MODE_MASK, 1628 .irq_en_reg = AFE_IRQ_MCU_CON0, 1629 .irq_en_shift = IRQ20_MCU_ON_SFT, 1630 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1631 .irq_clr_shift = IRQ20_MCU_CLR_SFT, 1632 }, 1633 [MT8192_IRQ_21] = { 1634 .id = MT8192_IRQ_21, 1635 .irq_cnt_reg = AFE_IRQ_MCU_CNT21, 1636 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1637 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1638 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1639 .irq_fs_shift = IRQ21_MCU_MODE_SFT, 1640 .irq_fs_maskbit = IRQ21_MCU_MODE_MASK, 1641 .irq_en_reg = AFE_IRQ_MCU_CON0, 1642 .irq_en_shift = IRQ21_MCU_ON_SFT, 1643 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1644 .irq_clr_shift = IRQ21_MCU_CLR_SFT, 1645 }, 1646 [MT8192_IRQ_22] = { 1647 .id = MT8192_IRQ_22, 1648 .irq_cnt_reg = AFE_IRQ_MCU_CNT22, 1649 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1650 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1651 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1652 .irq_fs_shift = IRQ22_MCU_MODE_SFT, 1653 .irq_fs_maskbit = IRQ22_MCU_MODE_MASK, 1654 .irq_en_reg = AFE_IRQ_MCU_CON0, 1655 .irq_en_shift = IRQ22_MCU_ON_SFT, 1656 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1657 .irq_clr_shift = IRQ22_MCU_CLR_SFT, 1658 }, 1659 [MT8192_IRQ_23] = { 1660 .id = MT8192_IRQ_23, 1661 .irq_cnt_reg = AFE_IRQ_MCU_CNT23, 1662 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1663 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1664 .irq_fs_reg = AFE_IRQ_MCU_CON3, 1665 .irq_fs_shift = IRQ23_MCU_MODE_SFT, 1666 .irq_fs_maskbit = IRQ23_MCU_MODE_MASK, 1667 .irq_en_reg = AFE_IRQ_MCU_CON0, 1668 .irq_en_shift = IRQ23_MCU_ON_SFT, 1669 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1670 .irq_clr_shift = IRQ23_MCU_CLR_SFT, 1671 }, 1672 [MT8192_IRQ_24] = { 1673 .id = MT8192_IRQ_24, 1674 .irq_cnt_reg = AFE_IRQ_MCU_CNT24, 1675 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1676 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1677 .irq_fs_reg = AFE_IRQ_MCU_CON4, 1678 .irq_fs_shift = IRQ24_MCU_MODE_SFT, 1679 .irq_fs_maskbit = IRQ24_MCU_MODE_MASK, 1680 .irq_en_reg = AFE_IRQ_MCU_CON0, 1681 .irq_en_shift = IRQ24_MCU_ON_SFT, 1682 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1683 .irq_clr_shift = IRQ24_MCU_CLR_SFT, 1684 }, 1685 [MT8192_IRQ_25] = { 1686 .id = MT8192_IRQ_25, 1687 .irq_cnt_reg = AFE_IRQ_MCU_CNT25, 1688 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1689 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1690 .irq_fs_reg = AFE_IRQ_MCU_CON4, 1691 .irq_fs_shift = IRQ25_MCU_MODE_SFT, 1692 .irq_fs_maskbit = IRQ25_MCU_MODE_MASK, 1693 .irq_en_reg = AFE_IRQ_MCU_CON0, 1694 .irq_en_shift = IRQ25_MCU_ON_SFT, 1695 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1696 .irq_clr_shift = IRQ25_MCU_CLR_SFT, 1697 }, 1698 [MT8192_IRQ_26] = { 1699 .id = MT8192_IRQ_26, 1700 .irq_cnt_reg = AFE_IRQ_MCU_CNT26, 1701 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1702 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1703 .irq_fs_reg = AFE_IRQ_MCU_CON4, 1704 .irq_fs_shift = IRQ26_MCU_MODE_SFT, 1705 .irq_fs_maskbit = IRQ26_MCU_MODE_MASK, 1706 .irq_en_reg = AFE_IRQ_MCU_CON0, 1707 .irq_en_shift = IRQ26_MCU_ON_SFT, 1708 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1709 .irq_clr_shift = IRQ26_MCU_CLR_SFT, 1710 }, 1711 [MT8192_IRQ_31] = { 1712 .id = MT8192_IRQ_31, 1713 .irq_cnt_reg = AFE_IRQ_MCU_CNT31, 1714 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 1715 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 1716 .irq_fs_reg = -1, 1717 .irq_fs_shift = -1, 1718 .irq_fs_maskbit = -1, 1719 .irq_en_reg = AFE_IRQ_MCU_CON0, 1720 .irq_en_shift = IRQ31_MCU_ON_SFT, 1721 .irq_clr_reg = AFE_IRQ_MCU_CLR, 1722 .irq_clr_shift = IRQ31_MCU_CLR_SFT, 1723 }, 1724 }; 1725 1726 static const int memif_irq_usage[MT8192_MEMIF_NUM] = { 1727 [MT8192_MEMIF_DL1] = MT8192_IRQ_0, 1728 [MT8192_MEMIF_DL2] = MT8192_IRQ_1, 1729 [MT8192_MEMIF_DL3] = MT8192_IRQ_2, 1730 [MT8192_MEMIF_DL4] = MT8192_IRQ_3, 1731 [MT8192_MEMIF_DL5] = MT8192_IRQ_4, 1732 [MT8192_MEMIF_DL6] = MT8192_IRQ_5, 1733 [MT8192_MEMIF_DL7] = MT8192_IRQ_6, 1734 [MT8192_MEMIF_DL8] = MT8192_IRQ_7, 1735 [MT8192_MEMIF_DL9] = MT8192_IRQ_8, 1736 [MT8192_MEMIF_DL12] = MT8192_IRQ_9, 1737 [MT8192_MEMIF_DAI] = MT8192_IRQ_10, 1738 [MT8192_MEMIF_MOD_DAI] = MT8192_IRQ_11, 1739 [MT8192_MEMIF_DAI2] = MT8192_IRQ_12, 1740 [MT8192_MEMIF_VUL12] = MT8192_IRQ_13, 1741 [MT8192_MEMIF_VUL2] = MT8192_IRQ_14, 1742 [MT8192_MEMIF_AWB] = MT8192_IRQ_15, 1743 [MT8192_MEMIF_AWB2] = MT8192_IRQ_16, 1744 [MT8192_MEMIF_VUL3] = MT8192_IRQ_17, 1745 [MT8192_MEMIF_VUL4] = MT8192_IRQ_18, 1746 [MT8192_MEMIF_VUL5] = MT8192_IRQ_19, 1747 [MT8192_MEMIF_VUL6] = MT8192_IRQ_20, 1748 [MT8192_MEMIF_HDMI] = MT8192_IRQ_31, 1749 }; 1750 1751 static bool mt8192_is_volatile_reg(struct device *dev, unsigned int reg) 1752 { 1753 /* these auto-gen reg has read-only bit, so put it as volatile */ 1754 /* volatile reg cannot be cached, so cannot be set when power off */ 1755 switch (reg) { 1756 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */ 1757 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */ 1758 case AUDIO_TOP_CON2: 1759 case AUDIO_TOP_CON3: 1760 case AFE_DL1_CUR_MSB: 1761 case AFE_DL1_CUR: 1762 case AFE_DL1_END: 1763 case AFE_DL2_CUR_MSB: 1764 case AFE_DL2_CUR: 1765 case AFE_DL2_END: 1766 case AFE_DL3_CUR_MSB: 1767 case AFE_DL3_CUR: 1768 case AFE_DL3_END: 1769 case AFE_DL4_CUR_MSB: 1770 case AFE_DL4_CUR: 1771 case AFE_DL4_END: 1772 case AFE_DL12_CUR_MSB: 1773 case AFE_DL12_CUR: 1774 case AFE_DL12_END: 1775 case AFE_ADDA_SRC_DEBUG_MON0: 1776 case AFE_ADDA_SRC_DEBUG_MON1: 1777 case AFE_ADDA_UL_SRC_MON0: 1778 case AFE_ADDA_UL_SRC_MON1: 1779 case AFE_SECURE_CON0: 1780 case AFE_SRAM_BOUND: 1781 case AFE_SECURE_CON1: 1782 case AFE_VUL_CUR_MSB: 1783 case AFE_VUL_CUR: 1784 case AFE_VUL_END: 1785 case AFE_ADDA_3RD_DAC_DL_SDM_FIFO_MON: 1786 case AFE_ADDA_3RD_DAC_DL_SRC_LCH_MON: 1787 case AFE_ADDA_3RD_DAC_DL_SRC_RCH_MON: 1788 case AFE_ADDA_3RD_DAC_DL_SDM_OUT_MON: 1789 case AFE_SIDETONE_MON: 1790 case AFE_SIDETONE_CON0: 1791 case AFE_SIDETONE_COEFF: 1792 case AFE_VUL2_CUR_MSB: 1793 case AFE_VUL2_CUR: 1794 case AFE_VUL2_END: 1795 case AFE_VUL3_CUR_MSB: 1796 case AFE_VUL3_CUR: 1797 case AFE_VUL3_END: 1798 case AFE_I2S_MON: 1799 case AFE_DAC_MON: 1800 case AFE_IRQ0_MCU_CNT_MON: 1801 case AFE_IRQ6_MCU_CNT_MON: 1802 case AFE_VUL4_CUR_MSB: 1803 case AFE_VUL4_CUR: 1804 case AFE_VUL4_END: 1805 case AFE_VUL12_CUR_MSB: 1806 case AFE_VUL12_CUR: 1807 case AFE_VUL12_END: 1808 case AFE_IRQ3_MCU_CNT_MON: 1809 case AFE_IRQ4_MCU_CNT_MON: 1810 case AFE_IRQ_MCU_STATUS: 1811 case AFE_IRQ_MCU_CLR: 1812 case AFE_IRQ_MCU_MON2: 1813 case AFE_IRQ1_MCU_CNT_MON: 1814 case AFE_IRQ2_MCU_CNT_MON: 1815 case AFE_IRQ5_MCU_CNT_MON: 1816 case AFE_IRQ7_MCU_CNT_MON: 1817 case AFE_IRQ_MCU_MISS_CLR: 1818 case AFE_GAIN1_CUR: 1819 case AFE_GAIN2_CUR: 1820 case AFE_SRAM_DELSEL_CON1: 1821 case PCM_INTF_CON2: 1822 case FPGA_CFG0: 1823 case FPGA_CFG1: 1824 case FPGA_CFG2: 1825 case FPGA_CFG3: 1826 case AUDIO_TOP_DBG_MON0: 1827 case AUDIO_TOP_DBG_MON1: 1828 case AFE_IRQ8_MCU_CNT_MON: 1829 case AFE_IRQ11_MCU_CNT_MON: 1830 case AFE_IRQ12_MCU_CNT_MON: 1831 case AFE_IRQ9_MCU_CNT_MON: 1832 case AFE_IRQ10_MCU_CNT_MON: 1833 case AFE_IRQ13_MCU_CNT_MON: 1834 case AFE_IRQ14_MCU_CNT_MON: 1835 case AFE_IRQ15_MCU_CNT_MON: 1836 case AFE_IRQ16_MCU_CNT_MON: 1837 case AFE_IRQ17_MCU_CNT_MON: 1838 case AFE_IRQ18_MCU_CNT_MON: 1839 case AFE_IRQ19_MCU_CNT_MON: 1840 case AFE_IRQ20_MCU_CNT_MON: 1841 case AFE_IRQ21_MCU_CNT_MON: 1842 case AFE_IRQ22_MCU_CNT_MON: 1843 case AFE_IRQ23_MCU_CNT_MON: 1844 case AFE_IRQ24_MCU_CNT_MON: 1845 case AFE_IRQ25_MCU_CNT_MON: 1846 case AFE_IRQ26_MCU_CNT_MON: 1847 case AFE_IRQ31_MCU_CNT_MON: 1848 case AFE_CBIP_MON0: 1849 case AFE_CBIP_SLV_MUX_MON0: 1850 case AFE_CBIP_SLV_DECODER_MON0: 1851 case AFE_ADDA6_MTKAIF_MON0: 1852 case AFE_ADDA6_MTKAIF_MON1: 1853 case AFE_AWB_CUR_MSB: 1854 case AFE_AWB_CUR: 1855 case AFE_AWB_END: 1856 case AFE_AWB2_CUR_MSB: 1857 case AFE_AWB2_CUR: 1858 case AFE_AWB2_END: 1859 case AFE_DAI_CUR_MSB: 1860 case AFE_DAI_CUR: 1861 case AFE_DAI_END: 1862 case AFE_DAI2_CUR_MSB: 1863 case AFE_DAI2_CUR: 1864 case AFE_DAI2_END: 1865 case AFE_ADDA6_SRC_DEBUG_MON0: 1866 case AFE_ADD6A_UL_SRC_MON0: 1867 case AFE_ADDA6_UL_SRC_MON1: 1868 case AFE_MOD_DAI_CUR_MSB: 1869 case AFE_MOD_DAI_CUR: 1870 case AFE_MOD_DAI_END: 1871 case AFE_HDMI_OUT_CUR_MSB: 1872 case AFE_HDMI_OUT_CUR: 1873 case AFE_HDMI_OUT_END: 1874 case AFE_AWB_RCH_MON: 1875 case AFE_AWB_LCH_MON: 1876 case AFE_VUL_RCH_MON: 1877 case AFE_VUL_LCH_MON: 1878 case AFE_VUL12_RCH_MON: 1879 case AFE_VUL12_LCH_MON: 1880 case AFE_VUL2_RCH_MON: 1881 case AFE_VUL2_LCH_MON: 1882 case AFE_DAI_DATA_MON: 1883 case AFE_MOD_DAI_DATA_MON: 1884 case AFE_DAI2_DATA_MON: 1885 case AFE_AWB2_RCH_MON: 1886 case AFE_AWB2_LCH_MON: 1887 case AFE_VUL3_RCH_MON: 1888 case AFE_VUL3_LCH_MON: 1889 case AFE_VUL4_RCH_MON: 1890 case AFE_VUL4_LCH_MON: 1891 case AFE_VUL5_RCH_MON: 1892 case AFE_VUL5_LCH_MON: 1893 case AFE_VUL6_RCH_MON: 1894 case AFE_VUL6_LCH_MON: 1895 case AFE_DL1_RCH_MON: 1896 case AFE_DL1_LCH_MON: 1897 case AFE_DL2_RCH_MON: 1898 case AFE_DL2_LCH_MON: 1899 case AFE_DL12_RCH1_MON: 1900 case AFE_DL12_LCH1_MON: 1901 case AFE_DL12_RCH2_MON: 1902 case AFE_DL12_LCH2_MON: 1903 case AFE_DL3_RCH_MON: 1904 case AFE_DL3_LCH_MON: 1905 case AFE_DL4_RCH_MON: 1906 case AFE_DL4_LCH_MON: 1907 case AFE_DL5_RCH_MON: 1908 case AFE_DL5_LCH_MON: 1909 case AFE_DL6_RCH_MON: 1910 case AFE_DL6_LCH_MON: 1911 case AFE_DL7_RCH_MON: 1912 case AFE_DL7_LCH_MON: 1913 case AFE_DL8_RCH_MON: 1914 case AFE_DL8_LCH_MON: 1915 case AFE_VUL5_CUR_MSB: 1916 case AFE_VUL5_CUR: 1917 case AFE_VUL5_END: 1918 case AFE_VUL6_CUR_MSB: 1919 case AFE_VUL6_CUR: 1920 case AFE_VUL6_END: 1921 case AFE_ADDA_DL_SDM_FIFO_MON: 1922 case AFE_ADDA_DL_SRC_LCH_MON: 1923 case AFE_ADDA_DL_SRC_RCH_MON: 1924 case AFE_ADDA_DL_SDM_OUT_MON: 1925 case AFE_CONNSYS_I2S_MON: 1926 case AFE_ASRC_2CH_CON0: 1927 case AFE_ASRC_2CH_CON2: 1928 case AFE_ASRC_2CH_CON3: 1929 case AFE_ASRC_2CH_CON4: 1930 case AFE_ASRC_2CH_CON5: 1931 case AFE_ASRC_2CH_CON7: 1932 case AFE_ASRC_2CH_CON8: 1933 case AFE_ASRC_2CH_CON12: 1934 case AFE_ASRC_2CH_CON13: 1935 case AFE_DL9_CUR_MSB: 1936 case AFE_DL9_CUR: 1937 case AFE_DL9_END: 1938 case AFE_ADDA_MTKAIF_MON0: 1939 case AFE_ADDA_MTKAIF_MON1: 1940 case AFE_DL_NLE_R_MON0: 1941 case AFE_DL_NLE_R_MON1: 1942 case AFE_DL_NLE_R_MON2: 1943 case AFE_DL_NLE_L_MON0: 1944 case AFE_DL_NLE_L_MON1: 1945 case AFE_DL_NLE_L_MON2: 1946 case AFE_GENERAL1_ASRC_2CH_CON0: 1947 case AFE_GENERAL1_ASRC_2CH_CON2: 1948 case AFE_GENERAL1_ASRC_2CH_CON3: 1949 case AFE_GENERAL1_ASRC_2CH_CON4: 1950 case AFE_GENERAL1_ASRC_2CH_CON5: 1951 case AFE_GENERAL1_ASRC_2CH_CON7: 1952 case AFE_GENERAL1_ASRC_2CH_CON8: 1953 case AFE_GENERAL1_ASRC_2CH_CON12: 1954 case AFE_GENERAL1_ASRC_2CH_CON13: 1955 case AFE_GENERAL2_ASRC_2CH_CON0: 1956 case AFE_GENERAL2_ASRC_2CH_CON2: 1957 case AFE_GENERAL2_ASRC_2CH_CON3: 1958 case AFE_GENERAL2_ASRC_2CH_CON4: 1959 case AFE_GENERAL2_ASRC_2CH_CON5: 1960 case AFE_GENERAL2_ASRC_2CH_CON7: 1961 case AFE_GENERAL2_ASRC_2CH_CON8: 1962 case AFE_GENERAL2_ASRC_2CH_CON12: 1963 case AFE_GENERAL2_ASRC_2CH_CON13: 1964 case AFE_DL9_RCH_MON: 1965 case AFE_DL9_LCH_MON: 1966 case AFE_DL5_CUR_MSB: 1967 case AFE_DL5_CUR: 1968 case AFE_DL5_END: 1969 case AFE_DL6_CUR_MSB: 1970 case AFE_DL6_CUR: 1971 case AFE_DL6_END: 1972 case AFE_DL7_CUR_MSB: 1973 case AFE_DL7_CUR: 1974 case AFE_DL7_END: 1975 case AFE_DL8_CUR_MSB: 1976 case AFE_DL8_CUR: 1977 case AFE_DL8_END: 1978 case AFE_PROT_SIDEBAND_MON: 1979 case AFE_DOMAIN_SIDEBAND0_MON: 1980 case AFE_DOMAIN_SIDEBAND1_MON: 1981 case AFE_DOMAIN_SIDEBAND2_MON: 1982 case AFE_DOMAIN_SIDEBAND3_MON: 1983 case AFE_APLL1_TUNER_CFG: /* [20:31] is monitor */ 1984 case AFE_APLL2_TUNER_CFG: /* [20:31] is monitor */ 1985 case AFE_DAC_CON0: 1986 case AFE_IRQ_MCU_CON0: 1987 case AFE_IRQ_MCU_EN: 1988 return true; 1989 default: 1990 return false; 1991 }; 1992 } 1993 1994 static const struct regmap_config mt8192_afe_regmap_config = { 1995 .reg_bits = 32, 1996 .reg_stride = 4, 1997 .val_bits = 32, 1998 .volatile_reg = mt8192_is_volatile_reg, 1999 .max_register = AFE_MAX_REGISTER, 2000 .num_reg_defaults_raw = AFE_MAX_REGISTER, 2001 .cache_type = REGCACHE_FLAT, 2002 }; 2003 2004 static irqreturn_t mt8192_afe_irq_handler(int irq_id, void *dev) 2005 { 2006 struct mtk_base_afe *afe = dev; 2007 struct mtk_base_afe_irq *irq; 2008 unsigned int status; 2009 unsigned int status_mcu; 2010 unsigned int mcu_en; 2011 int ret; 2012 int i; 2013 2014 /* get irq that is sent to MCU */ 2015 regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 2016 2017 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 2018 /* only care IRQ which is sent to MCU */ 2019 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; 2020 2021 if (ret || status_mcu == 0) { 2022 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", 2023 __func__, ret, status, mcu_en); 2024 2025 goto err_irq; 2026 } 2027 2028 for (i = 0; i < MT8192_MEMIF_NUM; i++) { 2029 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2030 2031 if (!memif->substream) 2032 continue; 2033 2034 if (memif->irq_usage < 0) 2035 continue; 2036 2037 irq = &afe->irqs[memif->irq_usage]; 2038 2039 if (status_mcu & (1 << irq->irq_data->irq_en_shift)) 2040 snd_pcm_period_elapsed(memif->substream); 2041 } 2042 2043 err_irq: 2044 /* clear irq */ 2045 regmap_write(afe->regmap, 2046 AFE_IRQ_MCU_CLR, 2047 status_mcu); 2048 2049 return IRQ_HANDLED; 2050 } 2051 2052 static int mt8192_afe_runtime_suspend(struct device *dev) 2053 { 2054 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2055 struct mt8192_afe_private *afe_priv = afe->platform_priv; 2056 unsigned int value; 2057 int ret; 2058 2059 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2060 goto skip_regmap; 2061 2062 /* disable AFE */ 2063 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x0); 2064 2065 ret = regmap_read_poll_timeout(afe->regmap, 2066 AFE_DAC_MON, 2067 value, 2068 (value & AFE_ON_RETM_MASK_SFT) == 0, 2069 20, 2070 1 * 1000 * 1000); 2071 if (ret) 2072 dev_warn(afe->dev, "%s(), ret %d\n", __func__, ret); 2073 2074 /* make sure all irq status are cleared */ 2075 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff); 2076 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff); 2077 2078 /* reset sgen */ 2079 regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0); 2080 regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2, 2081 INNER_LOOP_BACK_MODE_MASK_SFT, 2082 0x3f << INNER_LOOP_BACK_MODE_SFT); 2083 2084 /* cache only */ 2085 regcache_cache_only(afe->regmap, true); 2086 regcache_mark_dirty(afe->regmap); 2087 2088 skip_regmap: 2089 mt8192_afe_disable_clock(afe); 2090 return 0; 2091 } 2092 2093 static int mt8192_afe_runtime_resume(struct device *dev) 2094 { 2095 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2096 struct mt8192_afe_private *afe_priv = afe->platform_priv; 2097 int ret; 2098 2099 ret = mt8192_afe_enable_clock(afe); 2100 if (ret) 2101 return ret; 2102 2103 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2104 goto skip_regmap; 2105 2106 regcache_cache_only(afe->regmap, false); 2107 regcache_sync(afe->regmap); 2108 2109 /* enable audio sys DCM for power saving */ 2110 regmap_update_bits(afe_priv->infracfg, 2111 PERI_BUS_DCM_CTRL, 0x1 << 29, 0x1 << 29); 2112 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29); 2113 2114 /* force cpu use 8_24 format when writing 32bit data */ 2115 regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, 2116 CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); 2117 2118 /* set all output port to 24bit */ 2119 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff); 2120 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff); 2121 2122 /* enable AFE */ 2123 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AFE_ON_MASK_SFT, 0x1); 2124 2125 skip_regmap: 2126 return 0; 2127 } 2128 2129 static int mt8192_dai_memif_register(struct mtk_base_afe *afe) 2130 { 2131 struct mtk_base_afe_dai *dai; 2132 2133 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2134 if (!dai) 2135 return -ENOMEM; 2136 2137 list_add(&dai->list, &afe->sub_dais); 2138 2139 dai->dai_drivers = mt8192_memif_dai_driver; 2140 dai->num_dai_drivers = ARRAY_SIZE(mt8192_memif_dai_driver); 2141 2142 dai->dapm_widgets = mt8192_memif_widgets; 2143 dai->num_dapm_widgets = ARRAY_SIZE(mt8192_memif_widgets); 2144 dai->dapm_routes = mt8192_memif_routes; 2145 dai->num_dapm_routes = ARRAY_SIZE(mt8192_memif_routes); 2146 return 0; 2147 } 2148 2149 typedef int (*dai_register_cb)(struct mtk_base_afe *); 2150 static const dai_register_cb dai_register_cbs[] = { 2151 mt8192_dai_adda_register, 2152 mt8192_dai_i2s_register, 2153 mt8192_dai_pcm_register, 2154 mt8192_dai_tdm_register, 2155 mt8192_dai_memif_register, 2156 }; 2157 2158 static int mt8192_afe_pcm_dev_probe(struct platform_device *pdev) 2159 { 2160 struct mtk_base_afe *afe; 2161 struct mt8192_afe_private *afe_priv; 2162 struct device *dev = &pdev->dev; 2163 struct reset_control *rstc; 2164 int i, ret, irq_id; 2165 2166 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 2167 if (ret) 2168 return ret; 2169 2170 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 2171 if (!afe) 2172 return -ENOMEM; 2173 platform_set_drvdata(pdev, afe); 2174 2175 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), 2176 GFP_KERNEL); 2177 if (!afe->platform_priv) 2178 return -ENOMEM; 2179 afe_priv = afe->platform_priv; 2180 2181 afe->dev = dev; 2182 2183 ret = of_reserved_mem_device_init(dev); 2184 if (ret) { 2185 dev_info(dev, "no reserved memory found, pre-allocating buffers instead\n"); 2186 afe->preallocate_buffers = true; 2187 } 2188 2189 /* init audio related clock */ 2190 ret = mt8192_init_clock(afe); 2191 if (ret) { 2192 dev_err(dev, "init clock error\n"); 2193 return ret; 2194 } 2195 2196 /* reset controller to reset audio regs before regmap cache */ 2197 rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 2198 if (IS_ERR(rstc)) 2199 return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n"); 2200 2201 ret = reset_control_reset(rstc); 2202 if (ret) 2203 return dev_err_probe(dev, ret, "failed to trigger audio reset\n"); 2204 2205 ret = devm_pm_runtime_enable(dev); 2206 if (ret) 2207 return ret; 2208 2209 /* regmap init */ 2210 afe->regmap = syscon_node_to_regmap(dev->parent->of_node); 2211 if (IS_ERR(afe->regmap)) 2212 return dev_err_probe(dev, PTR_ERR(afe->regmap), 2213 "could not get regmap from parent"); 2214 2215 ret = regmap_attach_dev(dev, afe->regmap, &mt8192_afe_regmap_config); 2216 if (ret) 2217 return dev_err_probe(dev, ret, "regmap_attach_dev fail\n"); 2218 2219 /* enable clock for regcache get default value from hw */ 2220 afe_priv->pm_runtime_bypass_reg_ctl = true; 2221 pm_runtime_get_sync(dev); 2222 2223 ret = regmap_reinit_cache(afe->regmap, &mt8192_afe_regmap_config); 2224 if (ret) 2225 return dev_err_probe(dev, ret, "regmap_reinit_cache fail\n"); 2226 2227 pm_runtime_put_sync(dev); 2228 afe_priv->pm_runtime_bypass_reg_ctl = false; 2229 2230 regcache_cache_only(afe->regmap, true); 2231 regcache_mark_dirty(afe->regmap); 2232 2233 /* init memif */ 2234 afe->memif_size = MT8192_MEMIF_NUM; 2235 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), 2236 GFP_KERNEL); 2237 if (!afe->memif) 2238 return -ENOMEM; 2239 2240 for (i = 0; i < afe->memif_size; i++) { 2241 afe->memif[i].data = &memif_data[i]; 2242 afe->memif[i].irq_usage = memif_irq_usage[i]; 2243 afe->memif[i].const_irq = 1; 2244 } 2245 2246 mutex_init(&afe->irq_alloc_lock); /* needed when dynamic irq */ 2247 2248 /* init irq */ 2249 afe->irqs_size = MT8192_IRQ_NUM; 2250 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 2251 GFP_KERNEL); 2252 if (!afe->irqs) 2253 return -ENOMEM; 2254 2255 for (i = 0; i < afe->irqs_size; i++) 2256 afe->irqs[i].irq_data = &irq_data[i]; 2257 2258 /* request irq */ 2259 irq_id = platform_get_irq(pdev, 0); 2260 if (irq_id < 0) 2261 return irq_id; 2262 2263 ret = devm_request_irq(dev, irq_id, mt8192_afe_irq_handler, 2264 IRQF_TRIGGER_NONE, "asys-isr", (void *)afe); 2265 if (ret) 2266 return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n"); 2267 2268 /* init sub_dais */ 2269 INIT_LIST_HEAD(&afe->sub_dais); 2270 2271 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 2272 ret = dai_register_cbs[i](afe); 2273 if (ret) 2274 return dev_err_probe(afe->dev, ret, "dai %d register fail", i); 2275 } 2276 2277 /* init dai_driver and component_driver */ 2278 ret = mtk_afe_combine_sub_dai(afe); 2279 if (ret) 2280 return dev_err_probe(afe->dev, ret, "mtk_afe_combine_sub_dai fail\n"); 2281 2282 /* others */ 2283 afe->mtk_afe_hardware = &mt8192_afe_hardware; 2284 afe->memif_fs = mt8192_memif_fs; 2285 afe->irq_fs = mt8192_irq_fs; 2286 afe->get_dai_fs = mt8192_get_dai_fs; 2287 afe->get_memif_pbuf_size = mt8192_get_memif_pbuf_size; 2288 afe->memif_32bit_supported = 1; 2289 2290 afe->runtime_resume = mt8192_afe_runtime_resume; 2291 afe->runtime_suspend = mt8192_afe_runtime_suspend; 2292 2293 /* register platform */ 2294 ret = devm_snd_soc_register_component(dev, 2295 &mtk_afe_pcm_platform, 2296 afe->dai_drivers, 2297 afe->num_dai_drivers); 2298 if (ret) 2299 return dev_err_probe(dev, ret, "Couldn't register AFE component\n"); 2300 2301 return 0; 2302 } 2303 2304 static void mt8192_afe_pcm_dev_remove(struct platform_device *pdev) 2305 { 2306 struct mtk_base_afe *afe = platform_get_drvdata(pdev); 2307 2308 pm_runtime_disable(&pdev->dev); 2309 if (!pm_runtime_status_suspended(&pdev->dev)) 2310 mt8192_afe_runtime_suspend(&pdev->dev); 2311 2312 /* disable afe clock */ 2313 mt8192_afe_disable_clock(afe); 2314 } 2315 2316 static const struct of_device_id mt8192_afe_pcm_dt_match[] = { 2317 { .compatible = "mediatek,mt8192-audio", }, 2318 {}, 2319 }; 2320 MODULE_DEVICE_TABLE(of, mt8192_afe_pcm_dt_match); 2321 2322 static const struct dev_pm_ops mt8192_afe_pm_ops = { 2323 RUNTIME_PM_OPS(mt8192_afe_runtime_suspend, 2324 mt8192_afe_runtime_resume, NULL) 2325 }; 2326 2327 static struct platform_driver mt8192_afe_pcm_driver = { 2328 .driver = { 2329 .name = "mt8192-audio", 2330 .of_match_table = mt8192_afe_pcm_dt_match, 2331 .pm = pm_ptr(&mt8192_afe_pm_ops), 2332 }, 2333 .probe = mt8192_afe_pcm_dev_probe, 2334 .remove = mt8192_afe_pcm_dev_remove, 2335 }; 2336 2337 module_platform_driver(mt8192_afe_pcm_driver); 2338 2339 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8192"); 2340 MODULE_AUTHOR("Shane Chien <shane.chien@mediatek.com>"); 2341 MODULE_LICENSE("GPL v2"); 2342