1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI eTDM Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/pcm_params.h> 15 #include "mt8188-afe-clk.h" 16 #include "mt8188-afe-common.h" 17 #include "mt8188-reg.h" 18 19 #define MT8188_ETDM_MAX_CHANNELS 16 20 #define MT8188_ETDM_NORMAL_MAX_BCK_RATE 24576000 21 #define ETDM_TO_DAI_ID(x) ((x) + MT8188_AFE_IO_ETDM_START) 22 #define ENUM_TO_STR(x) #x 23 24 enum { 25 MTK_DAI_ETDM_FORMAT_I2S = 0, 26 MTK_DAI_ETDM_FORMAT_LJ, 27 MTK_DAI_ETDM_FORMAT_RJ, 28 MTK_DAI_ETDM_FORMAT_EIAJ, 29 MTK_DAI_ETDM_FORMAT_DSPA, 30 MTK_DAI_ETDM_FORMAT_DSPB, 31 }; 32 33 enum { 34 MTK_DAI_ETDM_DATA_ONE_PIN = 0, 35 MTK_DAI_ETDM_DATA_MULTI_PIN, 36 }; 37 38 enum { 39 ETDM_IN, 40 ETDM_OUT, 41 }; 42 43 enum { 44 COWORK_ETDM_NONE = 0, 45 COWORK_ETDM_IN1_M = 2, 46 COWORK_ETDM_IN1_S = 3, 47 COWORK_ETDM_IN2_M = 4, 48 COWORK_ETDM_IN2_S = 5, 49 COWORK_ETDM_OUT1_M = 10, 50 COWORK_ETDM_OUT1_S = 11, 51 COWORK_ETDM_OUT2_M = 12, 52 COWORK_ETDM_OUT2_S = 13, 53 COWORK_ETDM_OUT3_M = 14, 54 COWORK_ETDM_OUT3_S = 15, 55 }; 56 57 enum { 58 ETDM_RELATCH_TIMING_A1A2SYS, 59 ETDM_RELATCH_TIMING_A3SYS, 60 ETDM_RELATCH_TIMING_A4SYS, 61 }; 62 63 enum { 64 ETDM_SYNC_NONE, 65 ETDM_SYNC_FROM_IN1 = 2, 66 ETDM_SYNC_FROM_IN2 = 4, 67 ETDM_SYNC_FROM_OUT1 = 10, 68 ETDM_SYNC_FROM_OUT2 = 12, 69 ETDM_SYNC_FROM_OUT3 = 14, 70 }; 71 72 struct etdm_con_reg { 73 unsigned int con0; 74 unsigned int con1; 75 unsigned int con2; 76 unsigned int con3; 77 unsigned int con4; 78 unsigned int con5; 79 }; 80 81 struct mtk_dai_etdm_rate { 82 unsigned int rate; 83 unsigned int reg_value; 84 }; 85 86 struct mtk_dai_etdm_priv { 87 unsigned int clock_mode; 88 unsigned int data_mode; 89 bool slave_mode; 90 bool lrck_inv; 91 bool bck_inv; 92 unsigned int format; 93 unsigned int slots; 94 unsigned int lrck_width; 95 unsigned int mclk_freq; 96 unsigned int mclk_fixed_apll; 97 unsigned int mclk_apll; 98 unsigned int mclk_dir; 99 int cowork_source_id; //dai id 100 unsigned int cowork_slv_count; 101 int cowork_slv_id[MT8188_AFE_IO_ETDM_NUM - 1]; //dai_id 102 bool in_disable_ch[MT8188_ETDM_MAX_CHANNELS]; 103 unsigned int en_ref_cnt; 104 bool is_prepared; 105 }; 106 107 static const struct mtk_dai_etdm_rate mt8188_etdm_rates[] = { 108 { .rate = 8000, .reg_value = 0, }, 109 { .rate = 12000, .reg_value = 1, }, 110 { .rate = 16000, .reg_value = 2, }, 111 { .rate = 24000, .reg_value = 3, }, 112 { .rate = 32000, .reg_value = 4, }, 113 { .rate = 48000, .reg_value = 5, }, 114 { .rate = 96000, .reg_value = 7, }, 115 { .rate = 192000, .reg_value = 9, }, 116 { .rate = 384000, .reg_value = 11, }, 117 { .rate = 11025, .reg_value = 16, }, 118 { .rate = 22050, .reg_value = 17, }, 119 { .rate = 44100, .reg_value = 18, }, 120 { .rate = 88200, .reg_value = 19, }, 121 { .rate = 176400, .reg_value = 20, }, 122 { .rate = 352800, .reg_value = 21, }, 123 }; 124 125 static int get_etdm_fs_timing(unsigned int rate) 126 { 127 int i; 128 129 for (i = 0; i < ARRAY_SIZE(mt8188_etdm_rates); i++) 130 if (mt8188_etdm_rates[i].rate == rate) 131 return mt8188_etdm_rates[i].reg_value; 132 133 return -EINVAL; 134 } 135 136 static unsigned int get_etdm_ch_fixup(unsigned int channels) 137 { 138 if (channels > 16) 139 return 24; 140 else if (channels > 8) 141 return 16; 142 else if (channels > 4) 143 return 8; 144 else if (channels > 2) 145 return 4; 146 else 147 return 2; 148 } 149 150 static int get_etdm_reg(unsigned int dai_id, struct etdm_con_reg *etdm_reg) 151 { 152 switch (dai_id) { 153 case MT8188_AFE_IO_ETDM1_IN: 154 etdm_reg->con0 = ETDM_IN1_CON0; 155 etdm_reg->con1 = ETDM_IN1_CON1; 156 etdm_reg->con2 = ETDM_IN1_CON2; 157 etdm_reg->con3 = ETDM_IN1_CON3; 158 etdm_reg->con4 = ETDM_IN1_CON4; 159 etdm_reg->con5 = ETDM_IN1_CON5; 160 break; 161 case MT8188_AFE_IO_ETDM2_IN: 162 etdm_reg->con0 = ETDM_IN2_CON0; 163 etdm_reg->con1 = ETDM_IN2_CON1; 164 etdm_reg->con2 = ETDM_IN2_CON2; 165 etdm_reg->con3 = ETDM_IN2_CON3; 166 etdm_reg->con4 = ETDM_IN2_CON4; 167 etdm_reg->con5 = ETDM_IN2_CON5; 168 break; 169 case MT8188_AFE_IO_ETDM1_OUT: 170 etdm_reg->con0 = ETDM_OUT1_CON0; 171 etdm_reg->con1 = ETDM_OUT1_CON1; 172 etdm_reg->con2 = ETDM_OUT1_CON2; 173 etdm_reg->con3 = ETDM_OUT1_CON3; 174 etdm_reg->con4 = ETDM_OUT1_CON4; 175 etdm_reg->con5 = ETDM_OUT1_CON5; 176 break; 177 case MT8188_AFE_IO_ETDM2_OUT: 178 etdm_reg->con0 = ETDM_OUT2_CON0; 179 etdm_reg->con1 = ETDM_OUT2_CON1; 180 etdm_reg->con2 = ETDM_OUT2_CON2; 181 etdm_reg->con3 = ETDM_OUT2_CON3; 182 etdm_reg->con4 = ETDM_OUT2_CON4; 183 etdm_reg->con5 = ETDM_OUT2_CON5; 184 break; 185 case MT8188_AFE_IO_ETDM3_OUT: 186 case MT8188_AFE_IO_DPTX: 187 etdm_reg->con0 = ETDM_OUT3_CON0; 188 etdm_reg->con1 = ETDM_OUT3_CON1; 189 etdm_reg->con2 = ETDM_OUT3_CON2; 190 etdm_reg->con3 = ETDM_OUT3_CON3; 191 etdm_reg->con4 = ETDM_OUT3_CON4; 192 etdm_reg->con5 = ETDM_OUT3_CON5; 193 break; 194 default: 195 return -EINVAL; 196 } 197 return 0; 198 } 199 200 static int get_etdm_dir(unsigned int dai_id) 201 { 202 switch (dai_id) { 203 case MT8188_AFE_IO_ETDM1_IN: 204 case MT8188_AFE_IO_ETDM2_IN: 205 return ETDM_IN; 206 case MT8188_AFE_IO_ETDM1_OUT: 207 case MT8188_AFE_IO_ETDM2_OUT: 208 case MT8188_AFE_IO_ETDM3_OUT: 209 return ETDM_OUT; 210 default: 211 return -EINVAL; 212 } 213 } 214 215 static int get_etdm_wlen(unsigned int bitwidth) 216 { 217 return bitwidth <= 16 ? 16 : 32; 218 } 219 220 static bool is_valid_etdm_dai(int dai_id) 221 { 222 switch (dai_id) { 223 case MT8188_AFE_IO_ETDM1_IN: 224 fallthrough; 225 case MT8188_AFE_IO_ETDM2_IN: 226 fallthrough; 227 case MT8188_AFE_IO_ETDM1_OUT: 228 fallthrough; 229 case MT8188_AFE_IO_ETDM2_OUT: 230 fallthrough; 231 case MT8188_AFE_IO_DPTX: 232 fallthrough; 233 case MT8188_AFE_IO_ETDM3_OUT: 234 return true; 235 default: 236 return false; 237 } 238 } 239 240 static int is_cowork_mode(struct snd_soc_dai *dai) 241 { 242 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 243 struct mt8188_afe_private *afe_priv = afe->platform_priv; 244 struct mtk_dai_etdm_priv *etdm_data; 245 246 if (!is_valid_etdm_dai(dai->id)) 247 return -EINVAL; 248 etdm_data = afe_priv->dai_priv[dai->id]; 249 250 return (etdm_data->cowork_slv_count > 0 || 251 etdm_data->cowork_source_id != COWORK_ETDM_NONE); 252 } 253 254 static int sync_to_dai_id(int source_sel) 255 { 256 switch (source_sel) { 257 case ETDM_SYNC_FROM_IN1: 258 return MT8188_AFE_IO_ETDM1_IN; 259 case ETDM_SYNC_FROM_IN2: 260 return MT8188_AFE_IO_ETDM2_IN; 261 case ETDM_SYNC_FROM_OUT1: 262 return MT8188_AFE_IO_ETDM1_OUT; 263 case ETDM_SYNC_FROM_OUT2: 264 return MT8188_AFE_IO_ETDM2_OUT; 265 case ETDM_SYNC_FROM_OUT3: 266 return MT8188_AFE_IO_ETDM3_OUT; 267 default: 268 return 0; 269 } 270 } 271 272 static int get_etdm_cowork_master_id(struct snd_soc_dai *dai) 273 { 274 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 275 struct mt8188_afe_private *afe_priv = afe->platform_priv; 276 struct mtk_dai_etdm_priv *etdm_data; 277 int dai_id; 278 279 if (!is_valid_etdm_dai(dai->id)) 280 return -EINVAL; 281 etdm_data = afe_priv->dai_priv[dai->id]; 282 dai_id = etdm_data->cowork_source_id; 283 284 if (dai_id == COWORK_ETDM_NONE) 285 dai_id = dai->id; 286 287 return dai_id; 288 } 289 290 static int mtk_dai_etdm_get_cg_id_by_dai_id(int dai_id) 291 { 292 switch (dai_id) { 293 case MT8188_AFE_IO_DPTX: 294 return MT8188_CLK_AUD_HDMI_OUT; 295 case MT8188_AFE_IO_ETDM1_IN: 296 return MT8188_CLK_AUD_TDM_IN; 297 case MT8188_AFE_IO_ETDM2_IN: 298 return MT8188_CLK_AUD_I2SIN; 299 case MT8188_AFE_IO_ETDM1_OUT: 300 return MT8188_CLK_AUD_TDM_OUT; 301 case MT8188_AFE_IO_ETDM2_OUT: 302 return MT8188_CLK_AUD_I2S_OUT; 303 case MT8188_AFE_IO_ETDM3_OUT: 304 return MT8188_CLK_AUD_HDMI_OUT; 305 default: 306 return -EINVAL; 307 } 308 } 309 310 static int mtk_dai_etdm_get_clk_id_by_dai_id(int dai_id) 311 { 312 switch (dai_id) { 313 case MT8188_AFE_IO_DPTX: 314 return MT8188_CLK_TOP_DPTX_M_SEL; 315 case MT8188_AFE_IO_ETDM1_IN: 316 return MT8188_CLK_TOP_I2SI1_M_SEL; 317 case MT8188_AFE_IO_ETDM2_IN: 318 return MT8188_CLK_TOP_I2SI2_M_SEL; 319 case MT8188_AFE_IO_ETDM1_OUT: 320 return MT8188_CLK_TOP_I2SO1_M_SEL; 321 case MT8188_AFE_IO_ETDM2_OUT: 322 return MT8188_CLK_TOP_I2SO2_M_SEL; 323 case MT8188_AFE_IO_ETDM3_OUT: 324 default: 325 return -EINVAL; 326 } 327 } 328 329 static int mtk_dai_etdm_get_clkdiv_id_by_dai_id(int dai_id) 330 { 331 switch (dai_id) { 332 case MT8188_AFE_IO_DPTX: 333 return MT8188_CLK_TOP_APLL12_DIV9; 334 case MT8188_AFE_IO_ETDM1_IN: 335 return MT8188_CLK_TOP_APLL12_DIV0; 336 case MT8188_AFE_IO_ETDM2_IN: 337 return MT8188_CLK_TOP_APLL12_DIV1; 338 case MT8188_AFE_IO_ETDM1_OUT: 339 return MT8188_CLK_TOP_APLL12_DIV2; 340 case MT8188_AFE_IO_ETDM2_OUT: 341 return MT8188_CLK_TOP_APLL12_DIV3; 342 case MT8188_AFE_IO_ETDM3_OUT: 343 default: 344 return -EINVAL; 345 } 346 } 347 348 static int mtk_dai_etdm_enable_mclk(struct mtk_base_afe *afe, int dai_id) 349 { 350 struct mt8188_afe_private *afe_priv = afe->platform_priv; 351 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 352 353 if (clkdiv_id < 0) 354 return -EINVAL; 355 356 mt8188_afe_enable_clk(afe, afe_priv->clk[clkdiv_id]); 357 358 return 0; 359 } 360 361 static int mtk_dai_etdm_disable_mclk(struct mtk_base_afe *afe, int dai_id) 362 { 363 struct mt8188_afe_private *afe_priv = afe->platform_priv; 364 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 365 366 if (clkdiv_id < 0) 367 return -EINVAL; 368 369 mt8188_afe_disable_clk(afe, afe_priv->clk[clkdiv_id]); 370 371 return 0; 372 } 373 374 static const struct snd_kcontrol_new mtk_dai_etdm_o048_mix[] = { 375 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN48, 20, 1, 0), 376 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN48, 22, 1, 0), 377 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN48_1, 14, 1, 0), 378 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN48_2, 6, 1, 0), 379 }; 380 381 static const struct snd_kcontrol_new mtk_dai_etdm_o049_mix[] = { 382 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN49, 21, 1, 0), 383 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN49, 23, 1, 0), 384 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN49_1, 15, 1, 0), 385 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN49_2, 7, 1, 0), 386 }; 387 388 static const struct snd_kcontrol_new mtk_dai_etdm_o050_mix[] = { 389 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN50, 24, 1, 0), 390 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN50_1, 16, 1, 0), 391 }; 392 393 static const struct snd_kcontrol_new mtk_dai_etdm_o051_mix[] = { 394 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN51, 25, 1, 0), 395 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN51_1, 17, 1, 0), 396 }; 397 398 static const struct snd_kcontrol_new mtk_dai_etdm_o052_mix[] = { 399 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN52, 26, 1, 0), 400 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN52_1, 18, 1, 0), 401 }; 402 403 static const struct snd_kcontrol_new mtk_dai_etdm_o053_mix[] = { 404 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN53, 27, 1, 0), 405 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN53_1, 19, 1, 0), 406 }; 407 408 static const struct snd_kcontrol_new mtk_dai_etdm_o054_mix[] = { 409 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN54, 28, 1, 0), 410 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN54_1, 20, 1, 0), 411 }; 412 413 static const struct snd_kcontrol_new mtk_dai_etdm_o055_mix[] = { 414 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN55, 29, 1, 0), 415 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN55_1, 21, 1, 0), 416 }; 417 418 static const struct snd_kcontrol_new mtk_dai_etdm_o056_mix[] = { 419 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN56, 30, 1, 0), 420 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN56_1, 22, 1, 0), 421 }; 422 423 static const struct snd_kcontrol_new mtk_dai_etdm_o057_mix[] = { 424 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN57, 31, 1, 0), 425 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN57_1, 23, 1, 0), 426 }; 427 428 static const struct snd_kcontrol_new mtk_dai_etdm_o058_mix[] = { 429 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN58_1, 0, 1, 0), 430 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN58_1, 24, 1, 0), 431 }; 432 433 static const struct snd_kcontrol_new mtk_dai_etdm_o059_mix[] = { 434 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN59_1, 1, 1, 0), 435 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN59_1, 25, 1, 0), 436 }; 437 438 static const struct snd_kcontrol_new mtk_dai_etdm_o060_mix[] = { 439 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN60_1, 2, 1, 0), 440 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN60_1, 26, 1, 0), 441 }; 442 443 static const struct snd_kcontrol_new mtk_dai_etdm_o061_mix[] = { 444 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN61_1, 3, 1, 0), 445 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN61_1, 27, 1, 0), 446 }; 447 448 static const struct snd_kcontrol_new mtk_dai_etdm_o062_mix[] = { 449 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN62_1, 4, 1, 0), 450 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN62_1, 28, 1, 0), 451 }; 452 453 static const struct snd_kcontrol_new mtk_dai_etdm_o063_mix[] = { 454 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN63_1, 5, 1, 0), 455 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN63_1, 29, 1, 0), 456 }; 457 458 static const struct snd_kcontrol_new mtk_dai_etdm_o072_mix[] = { 459 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN72, 20, 1, 0), 460 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN72, 22, 1, 0), 461 SOC_DAPM_SINGLE_AUTODISABLE("I046 Switch", AFE_CONN72_1, 14, 1, 0), 462 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN72_2, 6, 1, 0), 463 }; 464 465 static const struct snd_kcontrol_new mtk_dai_etdm_o073_mix[] = { 466 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN73, 21, 1, 0), 467 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN73, 23, 1, 0), 468 SOC_DAPM_SINGLE_AUTODISABLE("I047 Switch", AFE_CONN73_1, 15, 1, 0), 469 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN73_2, 7, 1, 0), 470 }; 471 472 static const struct snd_kcontrol_new mtk_dai_etdm_o074_mix[] = { 473 SOC_DAPM_SINGLE_AUTODISABLE("I024 Switch", AFE_CONN74, 24, 1, 0), 474 SOC_DAPM_SINGLE_AUTODISABLE("I048 Switch", AFE_CONN74_1, 16, 1, 0), 475 }; 476 477 static const struct snd_kcontrol_new mtk_dai_etdm_o075_mix[] = { 478 SOC_DAPM_SINGLE_AUTODISABLE("I025 Switch", AFE_CONN75, 25, 1, 0), 479 SOC_DAPM_SINGLE_AUTODISABLE("I049 Switch", AFE_CONN75_1, 17, 1, 0), 480 }; 481 482 static const struct snd_kcontrol_new mtk_dai_etdm_o076_mix[] = { 483 SOC_DAPM_SINGLE_AUTODISABLE("I026 Switch", AFE_CONN76, 26, 1, 0), 484 SOC_DAPM_SINGLE_AUTODISABLE("I050 Switch", AFE_CONN76_1, 18, 1, 0), 485 }; 486 487 static const struct snd_kcontrol_new mtk_dai_etdm_o077_mix[] = { 488 SOC_DAPM_SINGLE_AUTODISABLE("I027 Switch", AFE_CONN77, 27, 1, 0), 489 SOC_DAPM_SINGLE_AUTODISABLE("I051 Switch", AFE_CONN77_1, 19, 1, 0), 490 }; 491 492 static const struct snd_kcontrol_new mtk_dai_etdm_o078_mix[] = { 493 SOC_DAPM_SINGLE_AUTODISABLE("I028 Switch", AFE_CONN78, 28, 1, 0), 494 SOC_DAPM_SINGLE_AUTODISABLE("I052 Switch", AFE_CONN78_1, 20, 1, 0), 495 }; 496 497 static const struct snd_kcontrol_new mtk_dai_etdm_o079_mix[] = { 498 SOC_DAPM_SINGLE_AUTODISABLE("I029 Switch", AFE_CONN79, 29, 1, 0), 499 SOC_DAPM_SINGLE_AUTODISABLE("I053 Switch", AFE_CONN79_1, 21, 1, 0), 500 }; 501 502 static const struct snd_kcontrol_new mtk_dai_etdm_o080_mix[] = { 503 SOC_DAPM_SINGLE_AUTODISABLE("I030 Switch", AFE_CONN80, 30, 1, 0), 504 SOC_DAPM_SINGLE_AUTODISABLE("I054 Switch", AFE_CONN80_1, 22, 1, 0), 505 }; 506 507 static const struct snd_kcontrol_new mtk_dai_etdm_o081_mix[] = { 508 SOC_DAPM_SINGLE_AUTODISABLE("I031 Switch", AFE_CONN81, 31, 1, 0), 509 SOC_DAPM_SINGLE_AUTODISABLE("I055 Switch", AFE_CONN81_1, 23, 1, 0), 510 }; 511 512 static const struct snd_kcontrol_new mtk_dai_etdm_o082_mix[] = { 513 SOC_DAPM_SINGLE_AUTODISABLE("I032 Switch", AFE_CONN82_1, 0, 1, 0), 514 SOC_DAPM_SINGLE_AUTODISABLE("I056 Switch", AFE_CONN82_1, 24, 1, 0), 515 }; 516 517 static const struct snd_kcontrol_new mtk_dai_etdm_o083_mix[] = { 518 SOC_DAPM_SINGLE_AUTODISABLE("I033 Switch", AFE_CONN83_1, 1, 1, 0), 519 SOC_DAPM_SINGLE_AUTODISABLE("I057 Switch", AFE_CONN83_1, 25, 1, 0), 520 }; 521 522 static const struct snd_kcontrol_new mtk_dai_etdm_o084_mix[] = { 523 SOC_DAPM_SINGLE_AUTODISABLE("I034 Switch", AFE_CONN84_1, 2, 1, 0), 524 SOC_DAPM_SINGLE_AUTODISABLE("I058 Switch", AFE_CONN84_1, 26, 1, 0), 525 }; 526 527 static const struct snd_kcontrol_new mtk_dai_etdm_o085_mix[] = { 528 SOC_DAPM_SINGLE_AUTODISABLE("I035 Switch", AFE_CONN85_1, 3, 1, 0), 529 SOC_DAPM_SINGLE_AUTODISABLE("I059 Switch", AFE_CONN85_1, 27, 1, 0), 530 }; 531 532 static const struct snd_kcontrol_new mtk_dai_etdm_o086_mix[] = { 533 SOC_DAPM_SINGLE_AUTODISABLE("I036 Switch", AFE_CONN86_1, 4, 1, 0), 534 SOC_DAPM_SINGLE_AUTODISABLE("I060 Switch", AFE_CONN86_1, 28, 1, 0), 535 }; 536 537 static const struct snd_kcontrol_new mtk_dai_etdm_o087_mix[] = { 538 SOC_DAPM_SINGLE_AUTODISABLE("I037 Switch", AFE_CONN87_1, 5, 1, 0), 539 SOC_DAPM_SINGLE_AUTODISABLE("I061 Switch", AFE_CONN87_1, 29, 1, 0), 540 }; 541 542 static const char * const mt8188_etdm_clk_src_sel_text[] = { 543 "26m", 544 "a1sys_a2sys", 545 "a3sys", 546 "a4sys", 547 }; 548 549 static SOC_ENUM_SINGLE_EXT_DECL(etdmout_clk_src_enum, 550 mt8188_etdm_clk_src_sel_text); 551 552 static const char * const hdmitx_dptx_mux_map[] = { 553 "Disconnect", "Connect", 554 }; 555 556 static int hdmitx_dptx_mux_map_value[] = { 557 0, 1, 558 }; 559 560 /* HDMI_OUT_MUX */ 561 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(hdmi_out_mux_map_enum, 562 SND_SOC_NOPM, 563 0, 564 1, 565 hdmitx_dptx_mux_map, 566 hdmitx_dptx_mux_map_value); 567 568 static const struct snd_kcontrol_new hdmi_out_mux_control = 569 SOC_DAPM_ENUM("HDMI_OUT_MUX", hdmi_out_mux_map_enum); 570 571 /* DPTX_OUT_MUX */ 572 static SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(dptx_out_mux_map_enum, 573 SND_SOC_NOPM, 574 0, 575 1, 576 hdmitx_dptx_mux_map, 577 hdmitx_dptx_mux_map_value); 578 579 static const struct snd_kcontrol_new dptx_out_mux_control = 580 SOC_DAPM_ENUM("DPTX_OUT_MUX", dptx_out_mux_map_enum); 581 582 /* HDMI_CH0_MUX ~ HDMI_CH7_MUX */ 583 static const char *const afe_conn_hdmi_mux_map[] = { 584 "CH0", "CH1", "CH2", "CH3", "CH4", "CH5", "CH6", "CH7", 585 }; 586 587 static int afe_conn_hdmi_mux_map_value[] = { 588 0, 1, 2, 3, 4, 5, 6, 7, 589 }; 590 591 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch0_mux_map_enum, 592 AFE_TDMOUT_CONN0, 593 0, 594 0xf, 595 afe_conn_hdmi_mux_map, 596 afe_conn_hdmi_mux_map_value); 597 598 static const struct snd_kcontrol_new hdmi_ch0_mux_control = 599 SOC_DAPM_ENUM("HDMI_CH0_MUX", hdmi_ch0_mux_map_enum); 600 601 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch1_mux_map_enum, 602 AFE_TDMOUT_CONN0, 603 4, 604 0xf, 605 afe_conn_hdmi_mux_map, 606 afe_conn_hdmi_mux_map_value); 607 608 static const struct snd_kcontrol_new hdmi_ch1_mux_control = 609 SOC_DAPM_ENUM("HDMI_CH1_MUX", hdmi_ch1_mux_map_enum); 610 611 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch2_mux_map_enum, 612 AFE_TDMOUT_CONN0, 613 8, 614 0xf, 615 afe_conn_hdmi_mux_map, 616 afe_conn_hdmi_mux_map_value); 617 618 static const struct snd_kcontrol_new hdmi_ch2_mux_control = 619 SOC_DAPM_ENUM("HDMI_CH2_MUX", hdmi_ch2_mux_map_enum); 620 621 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch3_mux_map_enum, 622 AFE_TDMOUT_CONN0, 623 12, 624 0xf, 625 afe_conn_hdmi_mux_map, 626 afe_conn_hdmi_mux_map_value); 627 628 static const struct snd_kcontrol_new hdmi_ch3_mux_control = 629 SOC_DAPM_ENUM("HDMI_CH3_MUX", hdmi_ch3_mux_map_enum); 630 631 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch4_mux_map_enum, 632 AFE_TDMOUT_CONN0, 633 16, 634 0xf, 635 afe_conn_hdmi_mux_map, 636 afe_conn_hdmi_mux_map_value); 637 638 static const struct snd_kcontrol_new hdmi_ch4_mux_control = 639 SOC_DAPM_ENUM("HDMI_CH4_MUX", hdmi_ch4_mux_map_enum); 640 641 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch5_mux_map_enum, 642 AFE_TDMOUT_CONN0, 643 20, 644 0xf, 645 afe_conn_hdmi_mux_map, 646 afe_conn_hdmi_mux_map_value); 647 648 static const struct snd_kcontrol_new hdmi_ch5_mux_control = 649 SOC_DAPM_ENUM("HDMI_CH5_MUX", hdmi_ch5_mux_map_enum); 650 651 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch6_mux_map_enum, 652 AFE_TDMOUT_CONN0, 653 24, 654 0xf, 655 afe_conn_hdmi_mux_map, 656 afe_conn_hdmi_mux_map_value); 657 658 static const struct snd_kcontrol_new hdmi_ch6_mux_control = 659 SOC_DAPM_ENUM("HDMI_CH6_MUX", hdmi_ch6_mux_map_enum); 660 661 static SOC_VALUE_ENUM_SINGLE_DECL(hdmi_ch7_mux_map_enum, 662 AFE_TDMOUT_CONN0, 663 28, 664 0xf, 665 afe_conn_hdmi_mux_map, 666 afe_conn_hdmi_mux_map_value); 667 668 static const struct snd_kcontrol_new hdmi_ch7_mux_control = 669 SOC_DAPM_ENUM("HDMI_CH7_MUX", hdmi_ch7_mux_map_enum); 670 671 static int mt8188_etdm_clk_src_sel_put(struct snd_kcontrol *kcontrol, 672 struct snd_ctl_elem_value *ucontrol) 673 { 674 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 675 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; 676 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 677 unsigned int source = ucontrol->value.enumerated.item[0]; 678 unsigned int val; 679 unsigned int old_val; 680 unsigned int mask; 681 unsigned int reg; 682 683 if (source >= e->items) 684 return -EINVAL; 685 686 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 687 reg = ETDM_OUT1_CON4; 688 mask = ETDM_OUT_CON4_CLOCK_MASK; 689 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 690 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 691 reg = ETDM_OUT2_CON4; 692 mask = ETDM_OUT_CON4_CLOCK_MASK; 693 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 694 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 695 reg = ETDM_OUT3_CON4; 696 mask = ETDM_OUT_CON4_CLOCK_MASK; 697 val = FIELD_PREP(ETDM_OUT_CON4_CLOCK_MASK, source); 698 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 699 reg = ETDM_IN1_CON2; 700 mask = ETDM_IN_CON2_CLOCK_MASK; 701 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 702 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 703 reg = ETDM_IN2_CON2; 704 mask = ETDM_IN_CON2_CLOCK_MASK; 705 val = FIELD_PREP(ETDM_IN_CON2_CLOCK_MASK, source); 706 } else { 707 return -EINVAL; 708 } 709 710 regmap_read(afe->regmap, reg, &old_val); 711 old_val &= mask; 712 if (old_val == val) 713 return 0; 714 715 regmap_update_bits(afe->regmap, reg, mask, val); 716 717 return 1; 718 } 719 720 static int mt8188_etdm_clk_src_sel_get(struct snd_kcontrol *kcontrol, 721 struct snd_ctl_elem_value *ucontrol) 722 { 723 struct snd_soc_component *component = 724 snd_soc_kcontrol_component(kcontrol); 725 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 726 unsigned int value; 727 unsigned int reg; 728 unsigned int mask; 729 unsigned int shift; 730 731 if (!strcmp(kcontrol->id.name, "ETDM_OUT1_Clock_Source")) { 732 reg = ETDM_OUT1_CON4; 733 mask = ETDM_OUT_CON4_CLOCK_MASK; 734 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 735 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT2_Clock_Source")) { 736 reg = ETDM_OUT2_CON4; 737 mask = ETDM_OUT_CON4_CLOCK_MASK; 738 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 739 } else if (!strcmp(kcontrol->id.name, "ETDM_OUT3_Clock_Source")) { 740 reg = ETDM_OUT3_CON4; 741 mask = ETDM_OUT_CON4_CLOCK_MASK; 742 shift = ETDM_OUT_CON4_CLOCK_SHIFT; 743 } else if (!strcmp(kcontrol->id.name, "ETDM_IN1_Clock_Source")) { 744 reg = ETDM_IN1_CON2; 745 mask = ETDM_IN_CON2_CLOCK_MASK; 746 shift = ETDM_IN_CON2_CLOCK_SHIFT; 747 } else if (!strcmp(kcontrol->id.name, "ETDM_IN2_Clock_Source")) { 748 reg = ETDM_IN2_CON2; 749 mask = ETDM_IN_CON2_CLOCK_MASK; 750 shift = ETDM_IN_CON2_CLOCK_SHIFT; 751 } else { 752 return -EINVAL; 753 } 754 755 regmap_read(afe->regmap, reg, &value); 756 757 value &= mask; 758 value >>= shift; 759 ucontrol->value.enumerated.item[0] = value; 760 return 0; 761 } 762 763 static const struct snd_kcontrol_new mtk_dai_etdm_controls[] = { 764 SOC_ENUM_EXT("ETDM_OUT1_Clock_Source", etdmout_clk_src_enum, 765 mt8188_etdm_clk_src_sel_get, 766 mt8188_etdm_clk_src_sel_put), 767 SOC_ENUM_EXT("ETDM_OUT2_Clock_Source", etdmout_clk_src_enum, 768 mt8188_etdm_clk_src_sel_get, 769 mt8188_etdm_clk_src_sel_put), 770 SOC_ENUM_EXT("ETDM_OUT3_Clock_Source", etdmout_clk_src_enum, 771 mt8188_etdm_clk_src_sel_get, 772 mt8188_etdm_clk_src_sel_put), 773 SOC_ENUM_EXT("ETDM_IN1_Clock_Source", etdmout_clk_src_enum, 774 mt8188_etdm_clk_src_sel_get, 775 mt8188_etdm_clk_src_sel_put), 776 SOC_ENUM_EXT("ETDM_IN2_Clock_Source", etdmout_clk_src_enum, 777 mt8188_etdm_clk_src_sel_get, 778 mt8188_etdm_clk_src_sel_put), 779 }; 780 781 static const struct snd_soc_dapm_widget mtk_dai_etdm_widgets[] = { 782 /* eTDM_IN2 */ 783 SND_SOC_DAPM_MIXER("I012", SND_SOC_NOPM, 0, 0, NULL, 0), 784 SND_SOC_DAPM_MIXER("I013", SND_SOC_NOPM, 0, 0, NULL, 0), 785 SND_SOC_DAPM_MIXER("I014", SND_SOC_NOPM, 0, 0, NULL, 0), 786 SND_SOC_DAPM_MIXER("I015", SND_SOC_NOPM, 0, 0, NULL, 0), 787 SND_SOC_DAPM_MIXER("I016", SND_SOC_NOPM, 0, 0, NULL, 0), 788 SND_SOC_DAPM_MIXER("I017", SND_SOC_NOPM, 0, 0, NULL, 0), 789 SND_SOC_DAPM_MIXER("I018", SND_SOC_NOPM, 0, 0, NULL, 0), 790 SND_SOC_DAPM_MIXER("I019", SND_SOC_NOPM, 0, 0, NULL, 0), 791 SND_SOC_DAPM_MIXER("I188", SND_SOC_NOPM, 0, 0, NULL, 0), 792 SND_SOC_DAPM_MIXER("I189", SND_SOC_NOPM, 0, 0, NULL, 0), 793 SND_SOC_DAPM_MIXER("I190", SND_SOC_NOPM, 0, 0, NULL, 0), 794 SND_SOC_DAPM_MIXER("I191", SND_SOC_NOPM, 0, 0, NULL, 0), 795 SND_SOC_DAPM_MIXER("I192", SND_SOC_NOPM, 0, 0, NULL, 0), 796 SND_SOC_DAPM_MIXER("I193", SND_SOC_NOPM, 0, 0, NULL, 0), 797 SND_SOC_DAPM_MIXER("I194", SND_SOC_NOPM, 0, 0, NULL, 0), 798 SND_SOC_DAPM_MIXER("I195", SND_SOC_NOPM, 0, 0, NULL, 0), 799 800 /* eTDM_IN1 */ 801 SND_SOC_DAPM_MIXER("I072", SND_SOC_NOPM, 0, 0, NULL, 0), 802 SND_SOC_DAPM_MIXER("I073", SND_SOC_NOPM, 0, 0, NULL, 0), 803 SND_SOC_DAPM_MIXER("I074", SND_SOC_NOPM, 0, 0, NULL, 0), 804 SND_SOC_DAPM_MIXER("I075", SND_SOC_NOPM, 0, 0, NULL, 0), 805 SND_SOC_DAPM_MIXER("I076", SND_SOC_NOPM, 0, 0, NULL, 0), 806 SND_SOC_DAPM_MIXER("I077", SND_SOC_NOPM, 0, 0, NULL, 0), 807 SND_SOC_DAPM_MIXER("I078", SND_SOC_NOPM, 0, 0, NULL, 0), 808 SND_SOC_DAPM_MIXER("I079", SND_SOC_NOPM, 0, 0, NULL, 0), 809 SND_SOC_DAPM_MIXER("I080", SND_SOC_NOPM, 0, 0, NULL, 0), 810 SND_SOC_DAPM_MIXER("I081", SND_SOC_NOPM, 0, 0, NULL, 0), 811 SND_SOC_DAPM_MIXER("I082", SND_SOC_NOPM, 0, 0, NULL, 0), 812 SND_SOC_DAPM_MIXER("I083", SND_SOC_NOPM, 0, 0, NULL, 0), 813 SND_SOC_DAPM_MIXER("I084", SND_SOC_NOPM, 0, 0, NULL, 0), 814 SND_SOC_DAPM_MIXER("I085", SND_SOC_NOPM, 0, 0, NULL, 0), 815 SND_SOC_DAPM_MIXER("I086", SND_SOC_NOPM, 0, 0, NULL, 0), 816 SND_SOC_DAPM_MIXER("I087", SND_SOC_NOPM, 0, 0, NULL, 0), 817 818 /* eTDM_OUT2 */ 819 SND_SOC_DAPM_MIXER("O048", SND_SOC_NOPM, 0, 0, 820 mtk_dai_etdm_o048_mix, ARRAY_SIZE(mtk_dai_etdm_o048_mix)), 821 SND_SOC_DAPM_MIXER("O049", SND_SOC_NOPM, 0, 0, 822 mtk_dai_etdm_o049_mix, ARRAY_SIZE(mtk_dai_etdm_o049_mix)), 823 SND_SOC_DAPM_MIXER("O050", SND_SOC_NOPM, 0, 0, 824 mtk_dai_etdm_o050_mix, ARRAY_SIZE(mtk_dai_etdm_o050_mix)), 825 SND_SOC_DAPM_MIXER("O051", SND_SOC_NOPM, 0, 0, 826 mtk_dai_etdm_o051_mix, ARRAY_SIZE(mtk_dai_etdm_o051_mix)), 827 SND_SOC_DAPM_MIXER("O052", SND_SOC_NOPM, 0, 0, 828 mtk_dai_etdm_o052_mix, ARRAY_SIZE(mtk_dai_etdm_o052_mix)), 829 SND_SOC_DAPM_MIXER("O053", SND_SOC_NOPM, 0, 0, 830 mtk_dai_etdm_o053_mix, ARRAY_SIZE(mtk_dai_etdm_o053_mix)), 831 SND_SOC_DAPM_MIXER("O054", SND_SOC_NOPM, 0, 0, 832 mtk_dai_etdm_o054_mix, ARRAY_SIZE(mtk_dai_etdm_o054_mix)), 833 SND_SOC_DAPM_MIXER("O055", SND_SOC_NOPM, 0, 0, 834 mtk_dai_etdm_o055_mix, ARRAY_SIZE(mtk_dai_etdm_o055_mix)), 835 SND_SOC_DAPM_MIXER("O056", SND_SOC_NOPM, 0, 0, 836 mtk_dai_etdm_o056_mix, ARRAY_SIZE(mtk_dai_etdm_o056_mix)), 837 SND_SOC_DAPM_MIXER("O057", SND_SOC_NOPM, 0, 0, 838 mtk_dai_etdm_o057_mix, ARRAY_SIZE(mtk_dai_etdm_o057_mix)), 839 SND_SOC_DAPM_MIXER("O058", SND_SOC_NOPM, 0, 0, 840 mtk_dai_etdm_o058_mix, ARRAY_SIZE(mtk_dai_etdm_o058_mix)), 841 SND_SOC_DAPM_MIXER("O059", SND_SOC_NOPM, 0, 0, 842 mtk_dai_etdm_o059_mix, ARRAY_SIZE(mtk_dai_etdm_o059_mix)), 843 SND_SOC_DAPM_MIXER("O060", SND_SOC_NOPM, 0, 0, 844 mtk_dai_etdm_o060_mix, ARRAY_SIZE(mtk_dai_etdm_o060_mix)), 845 SND_SOC_DAPM_MIXER("O061", SND_SOC_NOPM, 0, 0, 846 mtk_dai_etdm_o061_mix, ARRAY_SIZE(mtk_dai_etdm_o061_mix)), 847 SND_SOC_DAPM_MIXER("O062", SND_SOC_NOPM, 0, 0, 848 mtk_dai_etdm_o062_mix, ARRAY_SIZE(mtk_dai_etdm_o062_mix)), 849 SND_SOC_DAPM_MIXER("O063", SND_SOC_NOPM, 0, 0, 850 mtk_dai_etdm_o063_mix, ARRAY_SIZE(mtk_dai_etdm_o063_mix)), 851 852 /* eTDM_OUT1 */ 853 SND_SOC_DAPM_MIXER("O072", SND_SOC_NOPM, 0, 0, 854 mtk_dai_etdm_o072_mix, ARRAY_SIZE(mtk_dai_etdm_o072_mix)), 855 SND_SOC_DAPM_MIXER("O073", SND_SOC_NOPM, 0, 0, 856 mtk_dai_etdm_o073_mix, ARRAY_SIZE(mtk_dai_etdm_o073_mix)), 857 SND_SOC_DAPM_MIXER("O074", SND_SOC_NOPM, 0, 0, 858 mtk_dai_etdm_o074_mix, ARRAY_SIZE(mtk_dai_etdm_o074_mix)), 859 SND_SOC_DAPM_MIXER("O075", SND_SOC_NOPM, 0, 0, 860 mtk_dai_etdm_o075_mix, ARRAY_SIZE(mtk_dai_etdm_o075_mix)), 861 SND_SOC_DAPM_MIXER("O076", SND_SOC_NOPM, 0, 0, 862 mtk_dai_etdm_o076_mix, ARRAY_SIZE(mtk_dai_etdm_o076_mix)), 863 SND_SOC_DAPM_MIXER("O077", SND_SOC_NOPM, 0, 0, 864 mtk_dai_etdm_o077_mix, ARRAY_SIZE(mtk_dai_etdm_o077_mix)), 865 SND_SOC_DAPM_MIXER("O078", SND_SOC_NOPM, 0, 0, 866 mtk_dai_etdm_o078_mix, ARRAY_SIZE(mtk_dai_etdm_o078_mix)), 867 SND_SOC_DAPM_MIXER("O079", SND_SOC_NOPM, 0, 0, 868 mtk_dai_etdm_o079_mix, ARRAY_SIZE(mtk_dai_etdm_o079_mix)), 869 SND_SOC_DAPM_MIXER("O080", SND_SOC_NOPM, 0, 0, 870 mtk_dai_etdm_o080_mix, ARRAY_SIZE(mtk_dai_etdm_o080_mix)), 871 SND_SOC_DAPM_MIXER("O081", SND_SOC_NOPM, 0, 0, 872 mtk_dai_etdm_o081_mix, ARRAY_SIZE(mtk_dai_etdm_o081_mix)), 873 SND_SOC_DAPM_MIXER("O082", SND_SOC_NOPM, 0, 0, 874 mtk_dai_etdm_o082_mix, ARRAY_SIZE(mtk_dai_etdm_o082_mix)), 875 SND_SOC_DAPM_MIXER("O083", SND_SOC_NOPM, 0, 0, 876 mtk_dai_etdm_o083_mix, ARRAY_SIZE(mtk_dai_etdm_o083_mix)), 877 SND_SOC_DAPM_MIXER("O084", SND_SOC_NOPM, 0, 0, 878 mtk_dai_etdm_o084_mix, ARRAY_SIZE(mtk_dai_etdm_o084_mix)), 879 SND_SOC_DAPM_MIXER("O085", SND_SOC_NOPM, 0, 0, 880 mtk_dai_etdm_o085_mix, ARRAY_SIZE(mtk_dai_etdm_o085_mix)), 881 SND_SOC_DAPM_MIXER("O086", SND_SOC_NOPM, 0, 0, 882 mtk_dai_etdm_o086_mix, ARRAY_SIZE(mtk_dai_etdm_o086_mix)), 883 SND_SOC_DAPM_MIXER("O087", SND_SOC_NOPM, 0, 0, 884 mtk_dai_etdm_o087_mix, ARRAY_SIZE(mtk_dai_etdm_o087_mix)), 885 886 /* eTDM_OUT3 */ 887 SND_SOC_DAPM_MUX("HDMI_OUT_MUX", SND_SOC_NOPM, 0, 0, 888 &hdmi_out_mux_control), 889 SND_SOC_DAPM_MUX("DPTX_OUT_MUX", SND_SOC_NOPM, 0, 0, 890 &dptx_out_mux_control), 891 892 SND_SOC_DAPM_MUX("HDMI_CH0_MUX", SND_SOC_NOPM, 0, 0, 893 &hdmi_ch0_mux_control), 894 SND_SOC_DAPM_MUX("HDMI_CH1_MUX", SND_SOC_NOPM, 0, 0, 895 &hdmi_ch1_mux_control), 896 SND_SOC_DAPM_MUX("HDMI_CH2_MUX", SND_SOC_NOPM, 0, 0, 897 &hdmi_ch2_mux_control), 898 SND_SOC_DAPM_MUX("HDMI_CH3_MUX", SND_SOC_NOPM, 0, 0, 899 &hdmi_ch3_mux_control), 900 SND_SOC_DAPM_MUX("HDMI_CH4_MUX", SND_SOC_NOPM, 0, 0, 901 &hdmi_ch4_mux_control), 902 SND_SOC_DAPM_MUX("HDMI_CH5_MUX", SND_SOC_NOPM, 0, 0, 903 &hdmi_ch5_mux_control), 904 SND_SOC_DAPM_MUX("HDMI_CH6_MUX", SND_SOC_NOPM, 0, 0, 905 &hdmi_ch6_mux_control), 906 SND_SOC_DAPM_MUX("HDMI_CH7_MUX", SND_SOC_NOPM, 0, 0, 907 &hdmi_ch7_mux_control), 908 909 SND_SOC_DAPM_INPUT("ETDM_INPUT"), 910 SND_SOC_DAPM_OUTPUT("ETDM_OUTPUT"), 911 }; 912 913 static const struct snd_soc_dapm_route mtk_dai_etdm_routes[] = { 914 {"I012", NULL, "ETDM2_IN"}, 915 {"I013", NULL, "ETDM2_IN"}, 916 {"I014", NULL, "ETDM2_IN"}, 917 {"I015", NULL, "ETDM2_IN"}, 918 {"I016", NULL, "ETDM2_IN"}, 919 {"I017", NULL, "ETDM2_IN"}, 920 {"I018", NULL, "ETDM2_IN"}, 921 {"I019", NULL, "ETDM2_IN"}, 922 {"I188", NULL, "ETDM2_IN"}, 923 {"I189", NULL, "ETDM2_IN"}, 924 {"I190", NULL, "ETDM2_IN"}, 925 {"I191", NULL, "ETDM2_IN"}, 926 {"I192", NULL, "ETDM2_IN"}, 927 {"I193", NULL, "ETDM2_IN"}, 928 {"I194", NULL, "ETDM2_IN"}, 929 {"I195", NULL, "ETDM2_IN"}, 930 931 {"I072", NULL, "ETDM1_IN"}, 932 {"I073", NULL, "ETDM1_IN"}, 933 {"I074", NULL, "ETDM1_IN"}, 934 {"I075", NULL, "ETDM1_IN"}, 935 {"I076", NULL, "ETDM1_IN"}, 936 {"I077", NULL, "ETDM1_IN"}, 937 {"I078", NULL, "ETDM1_IN"}, 938 {"I079", NULL, "ETDM1_IN"}, 939 {"I080", NULL, "ETDM1_IN"}, 940 {"I081", NULL, "ETDM1_IN"}, 941 {"I082", NULL, "ETDM1_IN"}, 942 {"I083", NULL, "ETDM1_IN"}, 943 {"I084", NULL, "ETDM1_IN"}, 944 {"I085", NULL, "ETDM1_IN"}, 945 {"I086", NULL, "ETDM1_IN"}, 946 {"I087", NULL, "ETDM1_IN"}, 947 948 {"UL8", NULL, "ETDM1_IN"}, 949 {"UL3", NULL, "ETDM2_IN"}, 950 951 {"ETDM2_OUT", NULL, "O048"}, 952 {"ETDM2_OUT", NULL, "O049"}, 953 {"ETDM2_OUT", NULL, "O050"}, 954 {"ETDM2_OUT", NULL, "O051"}, 955 {"ETDM2_OUT", NULL, "O052"}, 956 {"ETDM2_OUT", NULL, "O053"}, 957 {"ETDM2_OUT", NULL, "O054"}, 958 {"ETDM2_OUT", NULL, "O055"}, 959 {"ETDM2_OUT", NULL, "O056"}, 960 {"ETDM2_OUT", NULL, "O057"}, 961 {"ETDM2_OUT", NULL, "O058"}, 962 {"ETDM2_OUT", NULL, "O059"}, 963 {"ETDM2_OUT", NULL, "O060"}, 964 {"ETDM2_OUT", NULL, "O061"}, 965 {"ETDM2_OUT", NULL, "O062"}, 966 {"ETDM2_OUT", NULL, "O063"}, 967 968 {"ETDM1_OUT", NULL, "O072"}, 969 {"ETDM1_OUT", NULL, "O073"}, 970 {"ETDM1_OUT", NULL, "O074"}, 971 {"ETDM1_OUT", NULL, "O075"}, 972 {"ETDM1_OUT", NULL, "O076"}, 973 {"ETDM1_OUT", NULL, "O077"}, 974 {"ETDM1_OUT", NULL, "O078"}, 975 {"ETDM1_OUT", NULL, "O079"}, 976 {"ETDM1_OUT", NULL, "O080"}, 977 {"ETDM1_OUT", NULL, "O081"}, 978 {"ETDM1_OUT", NULL, "O082"}, 979 {"ETDM1_OUT", NULL, "O083"}, 980 {"ETDM1_OUT", NULL, "O084"}, 981 {"ETDM1_OUT", NULL, "O085"}, 982 {"ETDM1_OUT", NULL, "O086"}, 983 {"ETDM1_OUT", NULL, "O087"}, 984 985 {"O048", "I020 Switch", "I020"}, 986 {"O049", "I021 Switch", "I021"}, 987 988 {"O048", "I022 Switch", "I022"}, 989 {"O049", "I023 Switch", "I023"}, 990 {"O050", "I024 Switch", "I024"}, 991 {"O051", "I025 Switch", "I025"}, 992 {"O052", "I026 Switch", "I026"}, 993 {"O053", "I027 Switch", "I027"}, 994 {"O054", "I028 Switch", "I028"}, 995 {"O055", "I029 Switch", "I029"}, 996 {"O056", "I030 Switch", "I030"}, 997 {"O057", "I031 Switch", "I031"}, 998 {"O058", "I032 Switch", "I032"}, 999 {"O059", "I033 Switch", "I033"}, 1000 {"O060", "I034 Switch", "I034"}, 1001 {"O061", "I035 Switch", "I035"}, 1002 {"O062", "I036 Switch", "I036"}, 1003 {"O063", "I037 Switch", "I037"}, 1004 1005 {"O048", "I046 Switch", "I046"}, 1006 {"O049", "I047 Switch", "I047"}, 1007 {"O050", "I048 Switch", "I048"}, 1008 {"O051", "I049 Switch", "I049"}, 1009 {"O052", "I050 Switch", "I050"}, 1010 {"O053", "I051 Switch", "I051"}, 1011 {"O054", "I052 Switch", "I052"}, 1012 {"O055", "I053 Switch", "I053"}, 1013 {"O056", "I054 Switch", "I054"}, 1014 {"O057", "I055 Switch", "I055"}, 1015 {"O058", "I056 Switch", "I056"}, 1016 {"O059", "I057 Switch", "I057"}, 1017 {"O060", "I058 Switch", "I058"}, 1018 {"O061", "I059 Switch", "I059"}, 1019 {"O062", "I060 Switch", "I060"}, 1020 {"O063", "I061 Switch", "I061"}, 1021 1022 {"O048", "I070 Switch", "I070"}, 1023 {"O049", "I071 Switch", "I071"}, 1024 1025 {"O072", "I020 Switch", "I020"}, 1026 {"O073", "I021 Switch", "I021"}, 1027 1028 {"O072", "I022 Switch", "I022"}, 1029 {"O073", "I023 Switch", "I023"}, 1030 {"O074", "I024 Switch", "I024"}, 1031 {"O075", "I025 Switch", "I025"}, 1032 {"O076", "I026 Switch", "I026"}, 1033 {"O077", "I027 Switch", "I027"}, 1034 {"O078", "I028 Switch", "I028"}, 1035 {"O079", "I029 Switch", "I029"}, 1036 {"O080", "I030 Switch", "I030"}, 1037 {"O081", "I031 Switch", "I031"}, 1038 {"O082", "I032 Switch", "I032"}, 1039 {"O083", "I033 Switch", "I033"}, 1040 {"O084", "I034 Switch", "I034"}, 1041 {"O085", "I035 Switch", "I035"}, 1042 {"O086", "I036 Switch", "I036"}, 1043 {"O087", "I037 Switch", "I037"}, 1044 1045 {"O072", "I046 Switch", "I046"}, 1046 {"O073", "I047 Switch", "I047"}, 1047 {"O074", "I048 Switch", "I048"}, 1048 {"O075", "I049 Switch", "I049"}, 1049 {"O076", "I050 Switch", "I050"}, 1050 {"O077", "I051 Switch", "I051"}, 1051 {"O078", "I052 Switch", "I052"}, 1052 {"O079", "I053 Switch", "I053"}, 1053 {"O080", "I054 Switch", "I054"}, 1054 {"O081", "I055 Switch", "I055"}, 1055 {"O082", "I056 Switch", "I056"}, 1056 {"O083", "I057 Switch", "I057"}, 1057 {"O084", "I058 Switch", "I058"}, 1058 {"O085", "I059 Switch", "I059"}, 1059 {"O086", "I060 Switch", "I060"}, 1060 {"O087", "I061 Switch", "I061"}, 1061 1062 {"O072", "I070 Switch", "I070"}, 1063 {"O073", "I071 Switch", "I071"}, 1064 1065 {"HDMI_CH0_MUX", "CH0", "DL10"}, 1066 {"HDMI_CH0_MUX", "CH1", "DL10"}, 1067 {"HDMI_CH0_MUX", "CH2", "DL10"}, 1068 {"HDMI_CH0_MUX", "CH3", "DL10"}, 1069 {"HDMI_CH0_MUX", "CH4", "DL10"}, 1070 {"HDMI_CH0_MUX", "CH5", "DL10"}, 1071 {"HDMI_CH0_MUX", "CH6", "DL10"}, 1072 {"HDMI_CH0_MUX", "CH7", "DL10"}, 1073 1074 {"HDMI_CH1_MUX", "CH0", "DL10"}, 1075 {"HDMI_CH1_MUX", "CH1", "DL10"}, 1076 {"HDMI_CH1_MUX", "CH2", "DL10"}, 1077 {"HDMI_CH1_MUX", "CH3", "DL10"}, 1078 {"HDMI_CH1_MUX", "CH4", "DL10"}, 1079 {"HDMI_CH1_MUX", "CH5", "DL10"}, 1080 {"HDMI_CH1_MUX", "CH6", "DL10"}, 1081 {"HDMI_CH1_MUX", "CH7", "DL10"}, 1082 1083 {"HDMI_CH2_MUX", "CH0", "DL10"}, 1084 {"HDMI_CH2_MUX", "CH1", "DL10"}, 1085 {"HDMI_CH2_MUX", "CH2", "DL10"}, 1086 {"HDMI_CH2_MUX", "CH3", "DL10"}, 1087 {"HDMI_CH2_MUX", "CH4", "DL10"}, 1088 {"HDMI_CH2_MUX", "CH5", "DL10"}, 1089 {"HDMI_CH2_MUX", "CH6", "DL10"}, 1090 {"HDMI_CH2_MUX", "CH7", "DL10"}, 1091 1092 {"HDMI_CH3_MUX", "CH0", "DL10"}, 1093 {"HDMI_CH3_MUX", "CH1", "DL10"}, 1094 {"HDMI_CH3_MUX", "CH2", "DL10"}, 1095 {"HDMI_CH3_MUX", "CH3", "DL10"}, 1096 {"HDMI_CH3_MUX", "CH4", "DL10"}, 1097 {"HDMI_CH3_MUX", "CH5", "DL10"}, 1098 {"HDMI_CH3_MUX", "CH6", "DL10"}, 1099 {"HDMI_CH3_MUX", "CH7", "DL10"}, 1100 1101 {"HDMI_CH4_MUX", "CH0", "DL10"}, 1102 {"HDMI_CH4_MUX", "CH1", "DL10"}, 1103 {"HDMI_CH4_MUX", "CH2", "DL10"}, 1104 {"HDMI_CH4_MUX", "CH3", "DL10"}, 1105 {"HDMI_CH4_MUX", "CH4", "DL10"}, 1106 {"HDMI_CH4_MUX", "CH5", "DL10"}, 1107 {"HDMI_CH4_MUX", "CH6", "DL10"}, 1108 {"HDMI_CH4_MUX", "CH7", "DL10"}, 1109 1110 {"HDMI_CH5_MUX", "CH0", "DL10"}, 1111 {"HDMI_CH5_MUX", "CH1", "DL10"}, 1112 {"HDMI_CH5_MUX", "CH2", "DL10"}, 1113 {"HDMI_CH5_MUX", "CH3", "DL10"}, 1114 {"HDMI_CH5_MUX", "CH4", "DL10"}, 1115 {"HDMI_CH5_MUX", "CH5", "DL10"}, 1116 {"HDMI_CH5_MUX", "CH6", "DL10"}, 1117 {"HDMI_CH5_MUX", "CH7", "DL10"}, 1118 1119 {"HDMI_CH6_MUX", "CH0", "DL10"}, 1120 {"HDMI_CH6_MUX", "CH1", "DL10"}, 1121 {"HDMI_CH6_MUX", "CH2", "DL10"}, 1122 {"HDMI_CH6_MUX", "CH3", "DL10"}, 1123 {"HDMI_CH6_MUX", "CH4", "DL10"}, 1124 {"HDMI_CH6_MUX", "CH5", "DL10"}, 1125 {"HDMI_CH6_MUX", "CH6", "DL10"}, 1126 {"HDMI_CH6_MUX", "CH7", "DL10"}, 1127 1128 {"HDMI_CH7_MUX", "CH0", "DL10"}, 1129 {"HDMI_CH7_MUX", "CH1", "DL10"}, 1130 {"HDMI_CH7_MUX", "CH2", "DL10"}, 1131 {"HDMI_CH7_MUX", "CH3", "DL10"}, 1132 {"HDMI_CH7_MUX", "CH4", "DL10"}, 1133 {"HDMI_CH7_MUX", "CH5", "DL10"}, 1134 {"HDMI_CH7_MUX", "CH6", "DL10"}, 1135 {"HDMI_CH7_MUX", "CH7", "DL10"}, 1136 1137 {"HDMI_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1138 {"HDMI_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1139 {"HDMI_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1140 {"HDMI_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1141 {"HDMI_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1142 {"HDMI_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1143 {"HDMI_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1144 {"HDMI_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1145 1146 {"DPTX_OUT_MUX", "Connect", "HDMI_CH0_MUX"}, 1147 {"DPTX_OUT_MUX", "Connect", "HDMI_CH1_MUX"}, 1148 {"DPTX_OUT_MUX", "Connect", "HDMI_CH2_MUX"}, 1149 {"DPTX_OUT_MUX", "Connect", "HDMI_CH3_MUX"}, 1150 {"DPTX_OUT_MUX", "Connect", "HDMI_CH4_MUX"}, 1151 {"DPTX_OUT_MUX", "Connect", "HDMI_CH5_MUX"}, 1152 {"DPTX_OUT_MUX", "Connect", "HDMI_CH6_MUX"}, 1153 {"DPTX_OUT_MUX", "Connect", "HDMI_CH7_MUX"}, 1154 1155 {"ETDM3_OUT", NULL, "HDMI_OUT_MUX"}, 1156 {"DPTX", NULL, "DPTX_OUT_MUX"}, 1157 1158 {"ETDM_OUTPUT", NULL, "DPTX"}, 1159 {"ETDM_OUTPUT", NULL, "ETDM1_OUT"}, 1160 {"ETDM_OUTPUT", NULL, "ETDM2_OUT"}, 1161 {"ETDM_OUTPUT", NULL, "ETDM3_OUT"}, 1162 {"ETDM1_IN", NULL, "ETDM_INPUT"}, 1163 {"ETDM2_IN", NULL, "ETDM_INPUT"}, 1164 }; 1165 1166 static int mt8188_afe_enable_etdm(struct mtk_base_afe *afe, int dai_id) 1167 { 1168 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1169 struct mtk_dai_etdm_priv *etdm_data; 1170 struct etdm_con_reg etdm_reg; 1171 unsigned long flags; 1172 int ret = 0; 1173 1174 if (!is_valid_etdm_dai(dai_id)) 1175 return -EINVAL; 1176 etdm_data = afe_priv->dai_priv[dai_id]; 1177 1178 dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1179 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1180 etdm_data->en_ref_cnt++; 1181 if (etdm_data->en_ref_cnt == 1) { 1182 ret = get_etdm_reg(dai_id, &etdm_reg); 1183 if (ret < 0) 1184 goto out; 1185 1186 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_EN); 1187 } 1188 1189 out: 1190 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1191 return ret; 1192 } 1193 1194 static int mt8188_afe_disable_etdm(struct mtk_base_afe *afe, int dai_id) 1195 { 1196 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1197 struct mtk_dai_etdm_priv *etdm_data; 1198 struct etdm_con_reg etdm_reg; 1199 unsigned long flags; 1200 int ret = 0; 1201 1202 if (!is_valid_etdm_dai(dai_id)) 1203 return -EINVAL; 1204 etdm_data = afe_priv->dai_priv[dai_id]; 1205 1206 dev_dbg(afe->dev, "%s [%d]%d\n", __func__, dai_id, etdm_data->en_ref_cnt); 1207 spin_lock_irqsave(&afe_priv->afe_ctrl_lock, flags); 1208 if (etdm_data->en_ref_cnt > 0) { 1209 etdm_data->en_ref_cnt--; 1210 if (etdm_data->en_ref_cnt == 0) { 1211 ret = get_etdm_reg(dai_id, &etdm_reg); 1212 if (ret < 0) 1213 goto out; 1214 regmap_clear_bits(afe->regmap, etdm_reg.con0, 1215 ETDM_CON0_EN); 1216 } 1217 } 1218 1219 out: 1220 spin_unlock_irqrestore(&afe_priv->afe_ctrl_lock, flags); 1221 return ret; 1222 } 1223 1224 static int etdm_cowork_slv_sel(int id, int slave_mode) 1225 { 1226 if (slave_mode) { 1227 switch (id) { 1228 case MT8188_AFE_IO_ETDM1_IN: 1229 return COWORK_ETDM_IN1_S; 1230 case MT8188_AFE_IO_ETDM2_IN: 1231 return COWORK_ETDM_IN2_S; 1232 case MT8188_AFE_IO_ETDM1_OUT: 1233 return COWORK_ETDM_OUT1_S; 1234 case MT8188_AFE_IO_ETDM2_OUT: 1235 return COWORK_ETDM_OUT2_S; 1236 case MT8188_AFE_IO_ETDM3_OUT: 1237 return COWORK_ETDM_OUT3_S; 1238 default: 1239 return -EINVAL; 1240 } 1241 } else { 1242 switch (id) { 1243 case MT8188_AFE_IO_ETDM1_IN: 1244 return COWORK_ETDM_IN1_M; 1245 case MT8188_AFE_IO_ETDM2_IN: 1246 return COWORK_ETDM_IN2_M; 1247 case MT8188_AFE_IO_ETDM1_OUT: 1248 return COWORK_ETDM_OUT1_M; 1249 case MT8188_AFE_IO_ETDM2_OUT: 1250 return COWORK_ETDM_OUT2_M; 1251 case MT8188_AFE_IO_ETDM3_OUT: 1252 return COWORK_ETDM_OUT3_M; 1253 default: 1254 return -EINVAL; 1255 } 1256 } 1257 } 1258 1259 static int etdm_cowork_sync_sel(int id) 1260 { 1261 switch (id) { 1262 case MT8188_AFE_IO_ETDM1_IN: 1263 return ETDM_SYNC_FROM_IN1; 1264 case MT8188_AFE_IO_ETDM2_IN: 1265 return ETDM_SYNC_FROM_IN2; 1266 case MT8188_AFE_IO_ETDM1_OUT: 1267 return ETDM_SYNC_FROM_OUT1; 1268 case MT8188_AFE_IO_ETDM2_OUT: 1269 return ETDM_SYNC_FROM_OUT2; 1270 case MT8188_AFE_IO_ETDM3_OUT: 1271 return ETDM_SYNC_FROM_OUT3; 1272 default: 1273 return -EINVAL; 1274 } 1275 } 1276 1277 static int mt8188_etdm_sync_mode_slv(struct mtk_base_afe *afe, int dai_id) 1278 { 1279 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1280 struct mtk_dai_etdm_priv *etdm_data; 1281 unsigned int reg = 0; 1282 unsigned int mask; 1283 unsigned int val; 1284 int cowork_source_sel; 1285 1286 if (!is_valid_etdm_dai(dai_id)) 1287 return -EINVAL; 1288 etdm_data = afe_priv->dai_priv[dai_id]; 1289 1290 cowork_source_sel = etdm_cowork_slv_sel(etdm_data->cowork_source_id, 1291 true); 1292 if (cowork_source_sel < 0) 1293 return cowork_source_sel; 1294 1295 switch (dai_id) { 1296 case MT8188_AFE_IO_ETDM1_IN: 1297 reg = ETDM_COWORK_CON1; 1298 mask = ETDM_IN1_SLAVE_SEL_MASK; 1299 val = FIELD_PREP(ETDM_IN1_SLAVE_SEL_MASK, cowork_source_sel); 1300 break; 1301 case MT8188_AFE_IO_ETDM2_IN: 1302 reg = ETDM_COWORK_CON2; 1303 mask = ETDM_IN2_SLAVE_SEL_MASK; 1304 val = FIELD_PREP(ETDM_IN2_SLAVE_SEL_MASK, cowork_source_sel); 1305 break; 1306 case MT8188_AFE_IO_ETDM1_OUT: 1307 reg = ETDM_COWORK_CON0; 1308 mask = ETDM_OUT1_SLAVE_SEL_MASK; 1309 val = FIELD_PREP(ETDM_OUT1_SLAVE_SEL_MASK, cowork_source_sel); 1310 break; 1311 case MT8188_AFE_IO_ETDM2_OUT: 1312 reg = ETDM_COWORK_CON2; 1313 mask = ETDM_OUT2_SLAVE_SEL_MASK; 1314 val = FIELD_PREP(ETDM_OUT2_SLAVE_SEL_MASK, cowork_source_sel); 1315 break; 1316 case MT8188_AFE_IO_ETDM3_OUT: 1317 reg = ETDM_COWORK_CON2; 1318 mask = ETDM_OUT3_SLAVE_SEL_MASK; 1319 val = FIELD_PREP(ETDM_OUT3_SLAVE_SEL_MASK, cowork_source_sel); 1320 break; 1321 default: 1322 return 0; 1323 } 1324 1325 regmap_update_bits(afe->regmap, reg, mask, val); 1326 1327 return 0; 1328 } 1329 1330 static int mt8188_etdm_sync_mode_mst(struct mtk_base_afe *afe, int dai_id) 1331 { 1332 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1333 struct mtk_dai_etdm_priv *etdm_data; 1334 struct etdm_con_reg etdm_reg; 1335 unsigned int reg = 0; 1336 unsigned int mask; 1337 unsigned int val; 1338 int cowork_source_sel; 1339 int ret; 1340 1341 if (!is_valid_etdm_dai(dai_id)) 1342 return -EINVAL; 1343 etdm_data = afe_priv->dai_priv[dai_id]; 1344 1345 cowork_source_sel = etdm_cowork_sync_sel(etdm_data->cowork_source_id); 1346 if (cowork_source_sel < 0) 1347 return cowork_source_sel; 1348 1349 switch (dai_id) { 1350 case MT8188_AFE_IO_ETDM1_IN: 1351 reg = ETDM_COWORK_CON1; 1352 mask = ETDM_IN1_SYNC_SEL_MASK; 1353 val = FIELD_PREP(ETDM_IN1_SYNC_SEL_MASK, cowork_source_sel); 1354 break; 1355 case MT8188_AFE_IO_ETDM2_IN: 1356 reg = ETDM_COWORK_CON2; 1357 mask = ETDM_IN2_SYNC_SEL_MASK; 1358 val = FIELD_PREP(ETDM_IN2_SYNC_SEL_MASK, cowork_source_sel); 1359 break; 1360 case MT8188_AFE_IO_ETDM1_OUT: 1361 reg = ETDM_COWORK_CON0; 1362 mask = ETDM_OUT1_SYNC_SEL_MASK; 1363 val = FIELD_PREP(ETDM_OUT1_SYNC_SEL_MASK, cowork_source_sel); 1364 break; 1365 case MT8188_AFE_IO_ETDM2_OUT: 1366 reg = ETDM_COWORK_CON2; 1367 mask = ETDM_OUT2_SYNC_SEL_MASK; 1368 val = FIELD_PREP(ETDM_OUT2_SYNC_SEL_MASK, cowork_source_sel); 1369 break; 1370 case MT8188_AFE_IO_ETDM3_OUT: 1371 reg = ETDM_COWORK_CON2; 1372 mask = ETDM_OUT3_SYNC_SEL_MASK; 1373 val = FIELD_PREP(ETDM_OUT3_SYNC_SEL_MASK, cowork_source_sel); 1374 break; 1375 default: 1376 return 0; 1377 } 1378 1379 ret = get_etdm_reg(dai_id, &etdm_reg); 1380 if (ret < 0) 1381 return ret; 1382 1383 regmap_update_bits(afe->regmap, reg, mask, val); 1384 1385 regmap_set_bits(afe->regmap, etdm_reg.con0, ETDM_CON0_SYNC_MODE); 1386 1387 return 0; 1388 } 1389 1390 static int mt8188_etdm_sync_mode_configure(struct mtk_base_afe *afe, int dai_id) 1391 { 1392 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1393 struct mtk_dai_etdm_priv *etdm_data; 1394 1395 if (!is_valid_etdm_dai(dai_id)) 1396 return -EINVAL; 1397 etdm_data = afe_priv->dai_priv[dai_id]; 1398 1399 if (etdm_data->cowork_source_id == COWORK_ETDM_NONE) 1400 return 0; 1401 1402 if (etdm_data->slave_mode) 1403 mt8188_etdm_sync_mode_slv(afe, dai_id); 1404 else 1405 mt8188_etdm_sync_mode_mst(afe, dai_id); 1406 1407 return 0; 1408 } 1409 1410 /* dai ops */ 1411 static int mtk_dai_etdm_startup(struct snd_pcm_substream *substream, 1412 struct snd_soc_dai *dai) 1413 { 1414 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1415 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1416 struct mtk_dai_etdm_priv *mst_etdm_data; 1417 int mst_dai_id; 1418 int slv_dai_id; 1419 int cg_id; 1420 int i; 1421 1422 if (is_cowork_mode(dai)) { 1423 mst_dai_id = get_etdm_cowork_master_id(dai); 1424 if (!is_valid_etdm_dai(mst_dai_id)) 1425 return -EINVAL; 1426 mtk_dai_etdm_enable_mclk(afe, mst_dai_id); 1427 1428 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1429 if (cg_id >= 0) 1430 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1431 1432 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1433 1434 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1435 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1436 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1437 if (cg_id >= 0) 1438 mt8188_afe_enable_clk(afe, 1439 afe_priv->clk[cg_id]); 1440 } 1441 } else { 1442 mtk_dai_etdm_enable_mclk(afe, dai->id); 1443 1444 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1445 if (cg_id >= 0) 1446 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 1447 } 1448 1449 return 0; 1450 } 1451 1452 static void mtk_dai_etdm_shutdown(struct snd_pcm_substream *substream, 1453 struct snd_soc_dai *dai) 1454 { 1455 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1456 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1457 struct mtk_dai_etdm_priv *mst_etdm_data; 1458 int mst_dai_id; 1459 int slv_dai_id; 1460 int cg_id; 1461 int ret; 1462 int i; 1463 1464 if (!is_valid_etdm_dai(dai->id)) 1465 return; 1466 mst_etdm_data = afe_priv->dai_priv[dai->id]; 1467 1468 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1469 mst_etdm_data->is_prepared); 1470 1471 if (mst_etdm_data->is_prepared) { 1472 mst_etdm_data->is_prepared = false; 1473 1474 if (is_cowork_mode(dai)) { 1475 mst_dai_id = get_etdm_cowork_master_id(dai); 1476 if (!is_valid_etdm_dai(mst_dai_id)) 1477 return; 1478 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1479 1480 ret = mt8188_afe_disable_etdm(afe, mst_dai_id); 1481 if (ret) 1482 dev_dbg(afe->dev, "%s disable %d failed\n", 1483 __func__, mst_dai_id); 1484 1485 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1486 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1487 ret = mt8188_afe_disable_etdm(afe, slv_dai_id); 1488 if (ret) 1489 dev_dbg(afe->dev, "%s disable %d failed\n", 1490 __func__, slv_dai_id); 1491 } 1492 } else { 1493 ret = mt8188_afe_disable_etdm(afe, dai->id); 1494 if (ret) 1495 dev_dbg(afe->dev, "%s disable %d failed\n", 1496 __func__, dai->id); 1497 } 1498 } 1499 1500 if (is_cowork_mode(dai)) { 1501 mst_dai_id = get_etdm_cowork_master_id(dai); 1502 if (!is_valid_etdm_dai(mst_dai_id)) 1503 return; 1504 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(mst_dai_id); 1505 if (cg_id >= 0) 1506 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1507 1508 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1509 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1510 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1511 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(slv_dai_id); 1512 if (cg_id >= 0) 1513 mt8188_afe_disable_clk(afe, 1514 afe_priv->clk[cg_id]); 1515 } 1516 mtk_dai_etdm_disable_mclk(afe, mst_dai_id); 1517 } else { 1518 cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 1519 if (cg_id >= 0) 1520 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 1521 1522 mtk_dai_etdm_disable_mclk(afe, dai->id); 1523 } 1524 } 1525 1526 static int mtk_dai_etdm_fifo_mode(struct mtk_base_afe *afe, 1527 int dai_id, unsigned int rate) 1528 { 1529 unsigned int mode = 0; 1530 unsigned int reg = 0; 1531 unsigned int val = 0; 1532 unsigned int mask = (ETDM_IN_AFIFO_MODE_MASK | ETDM_IN_USE_AFIFO); 1533 1534 if (rate != 0) 1535 mode = mt8188_afe_fs_timing(rate); 1536 1537 switch (dai_id) { 1538 case MT8188_AFE_IO_ETDM1_IN: 1539 reg = ETDM_IN1_AFIFO_CON; 1540 if (rate == 0) 1541 mode = MT8188_ETDM_IN1_1X_EN; 1542 break; 1543 case MT8188_AFE_IO_ETDM2_IN: 1544 reg = ETDM_IN2_AFIFO_CON; 1545 if (rate == 0) 1546 mode = MT8188_ETDM_IN2_1X_EN; 1547 break; 1548 default: 1549 return -EINVAL; 1550 } 1551 1552 val = (mode | ETDM_IN_USE_AFIFO); 1553 1554 regmap_update_bits(afe->regmap, reg, mask, val); 1555 return 0; 1556 } 1557 1558 static int mtk_dai_etdm_in_configure(struct mtk_base_afe *afe, 1559 unsigned int rate, 1560 unsigned int channels, 1561 int dai_id) 1562 { 1563 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1564 struct mtk_dai_etdm_priv *etdm_data; 1565 struct etdm_con_reg etdm_reg; 1566 bool slave_mode; 1567 unsigned int data_mode; 1568 unsigned int lrck_width; 1569 unsigned int val = 0; 1570 unsigned int mask = 0; 1571 int ret; 1572 int i; 1573 1574 if (!is_valid_etdm_dai(dai_id)) 1575 return -EINVAL; 1576 etdm_data = afe_priv->dai_priv[dai_id]; 1577 slave_mode = etdm_data->slave_mode; 1578 data_mode = etdm_data->data_mode; 1579 lrck_width = etdm_data->lrck_width; 1580 1581 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1582 __func__, rate, channels, dai_id); 1583 1584 ret = get_etdm_reg(dai_id, &etdm_reg); 1585 if (ret < 0) 1586 return ret; 1587 1588 /* afifo */ 1589 if (slave_mode) 1590 mtk_dai_etdm_fifo_mode(afe, dai_id, 0); 1591 else 1592 mtk_dai_etdm_fifo_mode(afe, dai_id, rate); 1593 1594 /* con1 */ 1595 if (lrck_width > 0) { 1596 mask |= (ETDM_IN_CON1_LRCK_AUTO_MODE | 1597 ETDM_IN_CON1_LRCK_WIDTH_MASK); 1598 val |= FIELD_PREP(ETDM_IN_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1599 } 1600 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1601 1602 mask = 0; 1603 val = 0; 1604 1605 /* con2 */ 1606 if (!slave_mode) { 1607 mask |= ETDM_IN_CON2_UPDATE_GAP_MASK; 1608 if (rate == 352800 || rate == 384000) 1609 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 4); 1610 else 1611 val |= FIELD_PREP(ETDM_IN_CON2_UPDATE_GAP_MASK, 3); 1612 } 1613 mask |= (ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1614 ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK); 1615 if (data_mode == MTK_DAI_ETDM_DATA_MULTI_PIN) { 1616 val |= ETDM_IN_CON2_MULTI_IP_2CH_MODE | 1617 FIELD_PREP(ETDM_IN_CON2_MULTI_IP_TOTAL_CH_MASK, channels - 1); 1618 } 1619 regmap_update_bits(afe->regmap, etdm_reg.con2, mask, val); 1620 1621 mask = 0; 1622 val = 0; 1623 1624 /* con3 */ 1625 mask |= ETDM_IN_CON3_DISABLE_OUT_MASK; 1626 for (i = 0; i < channels; i += 2) { 1627 if (etdm_data->in_disable_ch[i] && 1628 etdm_data->in_disable_ch[i + 1]) 1629 val |= ETDM_IN_CON3_DISABLE_OUT(i >> 1); 1630 } 1631 if (!slave_mode) { 1632 mask |= ETDM_IN_CON3_FS_MASK; 1633 val |= FIELD_PREP(ETDM_IN_CON3_FS_MASK, get_etdm_fs_timing(rate)); 1634 } 1635 regmap_update_bits(afe->regmap, etdm_reg.con3, mask, val); 1636 1637 mask = 0; 1638 val = 0; 1639 1640 /* con4 */ 1641 mask |= (ETDM_IN_CON4_MASTER_LRCK_INV | ETDM_IN_CON4_MASTER_BCK_INV | 1642 ETDM_IN_CON4_SLAVE_LRCK_INV | ETDM_IN_CON4_SLAVE_BCK_INV); 1643 if (slave_mode) { 1644 if (etdm_data->lrck_inv) 1645 val |= ETDM_IN_CON4_SLAVE_LRCK_INV; 1646 if (etdm_data->bck_inv) 1647 val |= ETDM_IN_CON4_SLAVE_BCK_INV; 1648 } else { 1649 if (etdm_data->lrck_inv) 1650 val |= ETDM_IN_CON4_MASTER_LRCK_INV; 1651 if (etdm_data->bck_inv) 1652 val |= ETDM_IN_CON4_MASTER_BCK_INV; 1653 } 1654 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1655 1656 mask = 0; 1657 val = 0; 1658 1659 /* con5 */ 1660 mask |= ETDM_IN_CON5_LR_SWAP_MASK; 1661 mask |= ETDM_IN_CON5_ENABLE_ODD_MASK; 1662 for (i = 0; i < channels; i += 2) { 1663 if (etdm_data->in_disable_ch[i] && 1664 !etdm_data->in_disable_ch[i + 1]) { 1665 val |= ETDM_IN_CON5_LR_SWAP(i >> 1); 1666 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1667 } else if (!etdm_data->in_disable_ch[i] && 1668 etdm_data->in_disable_ch[i + 1]) { 1669 val |= ETDM_IN_CON5_ENABLE_ODD(i >> 1); 1670 } 1671 } 1672 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1673 return 0; 1674 } 1675 1676 static int mtk_dai_etdm_out_configure(struct mtk_base_afe *afe, 1677 unsigned int rate, 1678 unsigned int channels, 1679 int dai_id) 1680 { 1681 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1682 struct mtk_dai_etdm_priv *etdm_data; 1683 struct etdm_con_reg etdm_reg; 1684 bool slave_mode; 1685 unsigned int lrck_width; 1686 unsigned int val = 0; 1687 unsigned int mask = 0; 1688 int fs = 0; 1689 int ret; 1690 1691 if (!is_valid_etdm_dai(dai_id)) 1692 return -EINVAL; 1693 etdm_data = afe_priv->dai_priv[dai_id]; 1694 slave_mode = etdm_data->slave_mode; 1695 lrck_width = etdm_data->lrck_width; 1696 1697 dev_dbg(afe->dev, "%s rate %u channels %u, id %d\n", 1698 __func__, rate, channels, dai_id); 1699 1700 ret = get_etdm_reg(dai_id, &etdm_reg); 1701 if (ret < 0) 1702 return ret; 1703 1704 /* con0 */ 1705 mask = ETDM_OUT_CON0_RELATCH_DOMAIN_MASK; 1706 val = FIELD_PREP(ETDM_OUT_CON0_RELATCH_DOMAIN_MASK, 1707 ETDM_RELATCH_TIMING_A1A2SYS); 1708 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1709 1710 mask = 0; 1711 val = 0; 1712 1713 /* con1 */ 1714 if (lrck_width > 0) { 1715 mask |= (ETDM_OUT_CON1_LRCK_AUTO_MODE | 1716 ETDM_OUT_CON1_LRCK_WIDTH_MASK); 1717 val |= FIELD_PREP(ETDM_OUT_CON1_LRCK_WIDTH_MASK, lrck_width - 1); 1718 } 1719 regmap_update_bits(afe->regmap, etdm_reg.con1, mask, val); 1720 1721 mask = 0; 1722 val = 0; 1723 1724 if (!slave_mode) { 1725 /* con4 */ 1726 mask |= ETDM_OUT_CON4_FS_MASK; 1727 val |= FIELD_PREP(ETDM_OUT_CON4_FS_MASK, get_etdm_fs_timing(rate)); 1728 } 1729 1730 mask |= ETDM_OUT_CON4_RELATCH_EN_MASK; 1731 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) 1732 fs = MT8188_ETDM_OUT1_1X_EN; 1733 else if (dai_id == MT8188_AFE_IO_ETDM2_OUT) 1734 fs = MT8188_ETDM_OUT2_1X_EN; 1735 1736 val |= FIELD_PREP(ETDM_OUT_CON4_RELATCH_EN_MASK, fs); 1737 1738 regmap_update_bits(afe->regmap, etdm_reg.con4, mask, val); 1739 1740 mask = 0; 1741 val = 0; 1742 1743 /* con5 */ 1744 mask |= (ETDM_OUT_CON5_MASTER_LRCK_INV | ETDM_OUT_CON5_MASTER_BCK_INV | 1745 ETDM_OUT_CON5_SLAVE_LRCK_INV | ETDM_OUT_CON5_SLAVE_BCK_INV); 1746 if (slave_mode) { 1747 if (etdm_data->lrck_inv) 1748 val |= ETDM_OUT_CON5_SLAVE_LRCK_INV; 1749 if (etdm_data->bck_inv) 1750 val |= ETDM_OUT_CON5_SLAVE_BCK_INV; 1751 } else { 1752 if (etdm_data->lrck_inv) 1753 val |= ETDM_OUT_CON5_MASTER_LRCK_INV; 1754 if (etdm_data->bck_inv) 1755 val |= ETDM_OUT_CON5_MASTER_BCK_INV; 1756 } 1757 regmap_update_bits(afe->regmap, etdm_reg.con5, mask, val); 1758 1759 return 0; 1760 } 1761 1762 static int mtk_dai_etdm_mclk_configure(struct mtk_base_afe *afe, int dai_id) 1763 { 1764 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1765 struct mtk_dai_etdm_priv *etdm_data; 1766 struct etdm_con_reg etdm_reg; 1767 int clk_id = mtk_dai_etdm_get_clk_id_by_dai_id(dai_id); 1768 int clkdiv_id = mtk_dai_etdm_get_clkdiv_id_by_dai_id(dai_id); 1769 int apll_clk_id; 1770 int apll; 1771 int ret; 1772 1773 if (clk_id < 0 || clkdiv_id < 0) 1774 return -EINVAL; 1775 1776 if (!is_valid_etdm_dai(dai_id)) 1777 return -EINVAL; 1778 etdm_data = afe_priv->dai_priv[dai_id]; 1779 1780 ret = get_etdm_reg(dai_id, &etdm_reg); 1781 if (ret < 0) 1782 return ret; 1783 1784 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1785 regmap_set_bits(afe->regmap, etdm_reg.con1, 1786 ETDM_CON1_MCLK_OUTPUT); 1787 else 1788 regmap_clear_bits(afe->regmap, etdm_reg.con1, 1789 ETDM_CON1_MCLK_OUTPUT); 1790 1791 if (etdm_data->mclk_freq) { 1792 apll = etdm_data->mclk_apll; 1793 apll_clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 1794 if (apll_clk_id < 0) 1795 return apll_clk_id; 1796 1797 /* select apll */ 1798 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[clk_id], 1799 afe_priv->clk[apll_clk_id]); 1800 if (ret) 1801 return ret; 1802 1803 /* set rate */ 1804 ret = mt8188_afe_set_clk_rate(afe, afe_priv->clk[clkdiv_id], 1805 etdm_data->mclk_freq); 1806 if (ret) 1807 return ret; 1808 } else { 1809 if (etdm_data->mclk_dir == SND_SOC_CLOCK_OUT) 1810 dev_dbg(afe->dev, "%s mclk freq = 0\n", __func__); 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int mtk_dai_etdm_configure(struct mtk_base_afe *afe, 1817 unsigned int rate, 1818 unsigned int channels, 1819 unsigned int bit_width, 1820 int dai_id) 1821 { 1822 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1823 struct mtk_dai_etdm_priv *etdm_data; 1824 struct etdm_con_reg etdm_reg; 1825 bool slave_mode; 1826 unsigned int etdm_channels; 1827 unsigned int val = 0; 1828 unsigned int mask = 0; 1829 unsigned int bck; 1830 unsigned int wlen = get_etdm_wlen(bit_width); 1831 int ret; 1832 1833 if (!is_valid_etdm_dai(dai_id)) 1834 return -EINVAL; 1835 etdm_data = afe_priv->dai_priv[dai_id]; 1836 slave_mode = etdm_data->slave_mode; 1837 1838 ret = get_etdm_reg(dai_id, &etdm_reg); 1839 if (ret < 0) 1840 return ret; 1841 1842 dev_dbg(afe->dev, "%s fmt %u data %u lrck %d-%u bck %d, clock %u slv %u\n", 1843 __func__, etdm_data->format, etdm_data->data_mode, 1844 etdm_data->lrck_inv, etdm_data->lrck_width, etdm_data->bck_inv, 1845 etdm_data->clock_mode, etdm_data->slave_mode); 1846 dev_dbg(afe->dev, "%s rate %u channels %u bitwidth %u, id %d\n", 1847 __func__, rate, channels, bit_width, dai_id); 1848 1849 etdm_channels = (etdm_data->data_mode == MTK_DAI_ETDM_DATA_ONE_PIN) ? 1850 get_etdm_ch_fixup(channels) : 2; 1851 1852 bck = rate * etdm_channels * wlen; 1853 if (bck > MT8188_ETDM_NORMAL_MAX_BCK_RATE) { 1854 dev_err(afe->dev, "%s bck rate %u not support\n", 1855 __func__, bck); 1856 return -EINVAL; 1857 } 1858 1859 /* con0 */ 1860 mask |= ETDM_CON0_BIT_LEN_MASK; 1861 val |= FIELD_PREP(ETDM_CON0_BIT_LEN_MASK, bit_width - 1); 1862 mask |= ETDM_CON0_WORD_LEN_MASK; 1863 val |= FIELD_PREP(ETDM_CON0_WORD_LEN_MASK, wlen - 1); 1864 mask |= ETDM_CON0_FORMAT_MASK; 1865 val |= FIELD_PREP(ETDM_CON0_FORMAT_MASK, etdm_data->format); 1866 mask |= ETDM_CON0_CH_NUM_MASK; 1867 val |= FIELD_PREP(ETDM_CON0_CH_NUM_MASK, etdm_channels - 1); 1868 1869 mask |= ETDM_CON0_SLAVE_MODE; 1870 if (slave_mode) { 1871 if (dai_id == MT8188_AFE_IO_ETDM1_OUT) { 1872 dev_err(afe->dev, "%s id %d only support master mode\n", 1873 __func__, dai_id); 1874 return -EINVAL; 1875 } 1876 val |= ETDM_CON0_SLAVE_MODE; 1877 } 1878 regmap_update_bits(afe->regmap, etdm_reg.con0, mask, val); 1879 1880 if (get_etdm_dir(dai_id) == ETDM_IN) 1881 mtk_dai_etdm_in_configure(afe, rate, channels, dai_id); 1882 else 1883 mtk_dai_etdm_out_configure(afe, rate, channels, dai_id); 1884 1885 return 0; 1886 } 1887 1888 static int mtk_dai_etdm_hw_params(struct snd_pcm_substream *substream, 1889 struct snd_pcm_hw_params *params, 1890 struct snd_soc_dai *dai) 1891 { 1892 unsigned int rate = params_rate(params); 1893 unsigned int bit_width = params_width(params); 1894 unsigned int channels = params_channels(params); 1895 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1896 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1897 struct mtk_dai_etdm_priv *mst_etdm_data; 1898 int mst_dai_id; 1899 int slv_dai_id; 1900 int ret; 1901 int i; 1902 1903 dev_dbg(afe->dev, "%s '%s' period %u-%u\n", 1904 __func__, snd_pcm_stream_str(substream), 1905 params_period_size(params), params_periods(params)); 1906 1907 if (is_cowork_mode(dai)) { 1908 mst_dai_id = get_etdm_cowork_master_id(dai); 1909 if (!is_valid_etdm_dai(mst_dai_id)) 1910 return -EINVAL; 1911 1912 ret = mtk_dai_etdm_mclk_configure(afe, mst_dai_id); 1913 if (ret) 1914 return ret; 1915 1916 ret = mtk_dai_etdm_configure(afe, rate, channels, 1917 bit_width, mst_dai_id); 1918 if (ret) 1919 return ret; 1920 1921 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1922 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1923 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1924 ret = mtk_dai_etdm_configure(afe, rate, channels, 1925 bit_width, slv_dai_id); 1926 if (ret) 1927 return ret; 1928 1929 ret = mt8188_etdm_sync_mode_configure(afe, slv_dai_id); 1930 if (ret) 1931 return ret; 1932 } 1933 } else { 1934 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 1935 if (ret) 1936 return ret; 1937 1938 ret = mtk_dai_etdm_configure(afe, rate, channels, 1939 bit_width, dai->id); 1940 if (ret) 1941 return ret; 1942 } 1943 1944 return 0; 1945 } 1946 1947 static int mtk_dai_etdm_prepare(struct snd_pcm_substream *substream, 1948 struct snd_soc_dai *dai) 1949 { 1950 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 1951 struct mt8188_afe_private *afe_priv = afe->platform_priv; 1952 struct mtk_dai_etdm_priv *mst_etdm_data; 1953 int mst_dai_id; 1954 int slv_dai_id; 1955 int ret; 1956 int i; 1957 1958 if (!is_valid_etdm_dai(dai->id)) 1959 return -EINVAL; 1960 mst_etdm_data = afe_priv->dai_priv[dai->id]; 1961 1962 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 1963 mst_etdm_data->is_prepared); 1964 1965 if (mst_etdm_data->is_prepared) 1966 return 0; 1967 1968 mst_etdm_data->is_prepared = true; 1969 1970 if (is_cowork_mode(dai)) { 1971 mst_dai_id = get_etdm_cowork_master_id(dai); 1972 if (!is_valid_etdm_dai(mst_dai_id)) 1973 return -EINVAL; 1974 mst_etdm_data = afe_priv->dai_priv[mst_dai_id]; 1975 1976 for (i = 0; i < mst_etdm_data->cowork_slv_count; i++) { 1977 slv_dai_id = mst_etdm_data->cowork_slv_id[i]; 1978 ret = mt8188_afe_enable_etdm(afe, slv_dai_id); 1979 if (ret) { 1980 dev_dbg(afe->dev, "%s enable %d failed\n", 1981 __func__, slv_dai_id); 1982 1983 return ret; 1984 } 1985 } 1986 1987 ret = mt8188_afe_enable_etdm(afe, mst_dai_id); 1988 if (ret) { 1989 dev_dbg(afe->dev, "%s enable %d failed\n", 1990 __func__, mst_dai_id); 1991 1992 return ret; 1993 } 1994 } else { 1995 ret = mt8188_afe_enable_etdm(afe, dai->id); 1996 if (ret) { 1997 dev_dbg(afe->dev, "%s enable %d failed\n", 1998 __func__, dai->id); 1999 2000 return ret; 2001 } 2002 } 2003 2004 return 0; 2005 } 2006 2007 static int mtk_dai_etdm_cal_mclk(struct mtk_base_afe *afe, int freq, int dai_id) 2008 { 2009 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2010 struct mtk_dai_etdm_priv *etdm_data; 2011 int apll_rate; 2012 int apll; 2013 2014 if (!is_valid_etdm_dai(dai_id)) 2015 return -EINVAL; 2016 etdm_data = afe_priv->dai_priv[dai_id]; 2017 2018 if (freq == 0) { 2019 etdm_data->mclk_freq = freq; 2020 return 0; 2021 } 2022 2023 if (etdm_data->mclk_fixed_apll == 0) 2024 apll = mt8188_afe_get_default_mclk_source_by_rate(freq); 2025 else 2026 apll = etdm_data->mclk_apll; 2027 2028 apll_rate = mt8188_afe_get_mclk_source_rate(afe, apll); 2029 2030 if (freq > apll_rate) { 2031 dev_err(afe->dev, "freq %d > apll rate %d\n", freq, apll_rate); 2032 return -EINVAL; 2033 } 2034 2035 if (apll_rate % freq != 0) { 2036 dev_err(afe->dev, "APLL%d cannot generate freq Hz\n", apll); 2037 return -EINVAL; 2038 } 2039 2040 if (etdm_data->mclk_fixed_apll == 0) 2041 etdm_data->mclk_apll = apll; 2042 etdm_data->mclk_freq = freq; 2043 2044 return 0; 2045 } 2046 2047 static int mtk_dai_etdm_set_sysclk(struct snd_soc_dai *dai, 2048 int clk_id, unsigned int freq, int dir) 2049 { 2050 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2051 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2052 struct mtk_dai_etdm_priv *etdm_data; 2053 int dai_id; 2054 2055 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2056 __func__, dai->id, freq, dir); 2057 if (is_cowork_mode(dai)) 2058 dai_id = get_etdm_cowork_master_id(dai); 2059 else 2060 dai_id = dai->id; 2061 2062 if (!is_valid_etdm_dai(dai_id)) 2063 return -EINVAL; 2064 etdm_data = afe_priv->dai_priv[dai_id]; 2065 etdm_data->mclk_dir = dir; 2066 return mtk_dai_etdm_cal_mclk(afe, freq, dai_id); 2067 } 2068 2069 static int mtk_dai_etdm_set_tdm_slot(struct snd_soc_dai *dai, 2070 unsigned int tx_mask, unsigned int rx_mask, 2071 int slots, int slot_width) 2072 { 2073 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2074 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2075 struct mtk_dai_etdm_priv *etdm_data; 2076 2077 if (!is_valid_etdm_dai(dai->id)) 2078 return -EINVAL; 2079 etdm_data = afe_priv->dai_priv[dai->id]; 2080 2081 dev_dbg(dai->dev, "%s id %d slot_width %d\n", 2082 __func__, dai->id, slot_width); 2083 2084 etdm_data->slots = slots; 2085 etdm_data->lrck_width = slot_width; 2086 return 0; 2087 } 2088 2089 static int mtk_dai_etdm_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 2090 { 2091 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2092 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2093 struct mtk_dai_etdm_priv *etdm_data; 2094 2095 if (!is_valid_etdm_dai(dai->id)) 2096 return -EINVAL; 2097 etdm_data = afe_priv->dai_priv[dai->id]; 2098 2099 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 2100 case SND_SOC_DAIFMT_I2S: 2101 etdm_data->format = MTK_DAI_ETDM_FORMAT_I2S; 2102 break; 2103 case SND_SOC_DAIFMT_LEFT_J: 2104 etdm_data->format = MTK_DAI_ETDM_FORMAT_LJ; 2105 break; 2106 case SND_SOC_DAIFMT_RIGHT_J: 2107 etdm_data->format = MTK_DAI_ETDM_FORMAT_RJ; 2108 break; 2109 case SND_SOC_DAIFMT_DSP_A: 2110 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPA; 2111 break; 2112 case SND_SOC_DAIFMT_DSP_B: 2113 etdm_data->format = MTK_DAI_ETDM_FORMAT_DSPB; 2114 break; 2115 default: 2116 return -EINVAL; 2117 } 2118 2119 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 2120 case SND_SOC_DAIFMT_NB_NF: 2121 etdm_data->bck_inv = false; 2122 etdm_data->lrck_inv = false; 2123 break; 2124 case SND_SOC_DAIFMT_NB_IF: 2125 etdm_data->bck_inv = false; 2126 etdm_data->lrck_inv = true; 2127 break; 2128 case SND_SOC_DAIFMT_IB_NF: 2129 etdm_data->bck_inv = true; 2130 etdm_data->lrck_inv = false; 2131 break; 2132 case SND_SOC_DAIFMT_IB_IF: 2133 etdm_data->bck_inv = true; 2134 etdm_data->lrck_inv = true; 2135 break; 2136 default: 2137 return -EINVAL; 2138 } 2139 2140 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 2141 case SND_SOC_DAIFMT_BC_FC: 2142 etdm_data->slave_mode = true; 2143 break; 2144 case SND_SOC_DAIFMT_BP_FP: 2145 etdm_data->slave_mode = false; 2146 break; 2147 default: 2148 return -EINVAL; 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int mtk_dai_hdmitx_dptx_startup(struct snd_pcm_substream *substream, 2155 struct snd_soc_dai *dai) 2156 { 2157 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2158 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2159 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2160 2161 if (cg_id >= 0) 2162 mt8188_afe_enable_clk(afe, afe_priv->clk[cg_id]); 2163 2164 mtk_dai_etdm_enable_mclk(afe, dai->id); 2165 2166 return 0; 2167 } 2168 2169 static void mtk_dai_hdmitx_dptx_shutdown(struct snd_pcm_substream *substream, 2170 struct snd_soc_dai *dai) 2171 { 2172 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2173 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2174 int cg_id = mtk_dai_etdm_get_cg_id_by_dai_id(dai->id); 2175 struct mtk_dai_etdm_priv *etdm_data; 2176 int ret; 2177 2178 if (!is_valid_etdm_dai(dai->id)) 2179 return; 2180 etdm_data = afe_priv->dai_priv[dai->id]; 2181 2182 if (etdm_data->is_prepared) { 2183 etdm_data->is_prepared = false; 2184 /* disable etdm_out3 */ 2185 ret = mt8188_afe_disable_etdm(afe, dai->id); 2186 if (ret) 2187 dev_dbg(afe->dev, "%s disable failed\n", __func__); 2188 2189 /* disable dptx interface */ 2190 if (dai->id == MT8188_AFE_IO_DPTX) 2191 regmap_clear_bits(afe->regmap, AFE_DPTX_CON, 2192 AFE_DPTX_CON_ON); 2193 } 2194 2195 mtk_dai_etdm_disable_mclk(afe, dai->id); 2196 2197 if (cg_id >= 0) 2198 mt8188_afe_disable_clk(afe, afe_priv->clk[cg_id]); 2199 } 2200 2201 static unsigned int mtk_dai_get_dptx_ch_en(unsigned int channel) 2202 { 2203 switch (channel) { 2204 case 1 ... 2: 2205 return AFE_DPTX_CON_CH_EN_2CH; 2206 case 3 ... 4: 2207 return AFE_DPTX_CON_CH_EN_4CH; 2208 case 5 ... 6: 2209 return AFE_DPTX_CON_CH_EN_6CH; 2210 case 7 ... 8: 2211 return AFE_DPTX_CON_CH_EN_8CH; 2212 default: 2213 return AFE_DPTX_CON_CH_EN_2CH; 2214 } 2215 } 2216 2217 static unsigned int mtk_dai_get_dptx_ch(unsigned int ch) 2218 { 2219 return (ch > 2) ? 2220 AFE_DPTX_CON_CH_NUM_8CH : AFE_DPTX_CON_CH_NUM_2CH; 2221 } 2222 2223 static unsigned int mtk_dai_get_dptx_wlen(snd_pcm_format_t format) 2224 { 2225 return snd_pcm_format_physical_width(format) <= 16 ? 2226 AFE_DPTX_CON_16BIT : AFE_DPTX_CON_24BIT; 2227 } 2228 2229 static int mtk_dai_hdmitx_dptx_hw_params(struct snd_pcm_substream *substream, 2230 struct snd_pcm_hw_params *params, 2231 struct snd_soc_dai *dai) 2232 { 2233 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2234 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2235 struct mtk_dai_etdm_priv *etdm_data; 2236 unsigned int rate = params_rate(params); 2237 unsigned int channels = params_channels(params); 2238 snd_pcm_format_t format = params_format(params); 2239 int width = snd_pcm_format_physical_width(format); 2240 int ret; 2241 2242 if (!is_valid_etdm_dai(dai->id)) 2243 return -EINVAL; 2244 etdm_data = afe_priv->dai_priv[dai->id]; 2245 2246 /* dptx configure */ 2247 if (dai->id == MT8188_AFE_IO_DPTX) { 2248 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2249 AFE_DPTX_CON_CH_EN_MASK, 2250 mtk_dai_get_dptx_ch_en(channels)); 2251 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2252 AFE_DPTX_CON_CH_NUM_MASK, 2253 mtk_dai_get_dptx_ch(channels)); 2254 regmap_update_bits(afe->regmap, AFE_DPTX_CON, 2255 AFE_DPTX_CON_16BIT_MASK, 2256 mtk_dai_get_dptx_wlen(format)); 2257 2258 if (mtk_dai_get_dptx_ch(channels) == AFE_DPTX_CON_CH_NUM_8CH) { 2259 etdm_data->data_mode = MTK_DAI_ETDM_DATA_ONE_PIN; 2260 channels = 8; 2261 } else { 2262 channels = 2; 2263 } 2264 } else { 2265 etdm_data->data_mode = MTK_DAI_ETDM_DATA_MULTI_PIN; 2266 } 2267 2268 ret = mtk_dai_etdm_mclk_configure(afe, dai->id); 2269 if (ret) 2270 return ret; 2271 2272 ret = mtk_dai_etdm_configure(afe, rate, channels, width, dai->id); 2273 2274 return ret; 2275 } 2276 2277 static int mtk_dai_hdmitx_dptx_prepare(struct snd_pcm_substream *substream, 2278 struct snd_soc_dai *dai) 2279 { 2280 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2281 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2282 struct mtk_dai_etdm_priv *etdm_data; 2283 2284 if (!is_valid_etdm_dai(dai->id)) 2285 return -EINVAL; 2286 etdm_data = afe_priv->dai_priv[dai->id]; 2287 2288 dev_dbg(afe->dev, "%s(), dai id %d, prepared %d\n", __func__, dai->id, 2289 etdm_data->is_prepared); 2290 2291 if (etdm_data->is_prepared) 2292 return 0; 2293 2294 etdm_data->is_prepared = true; 2295 2296 /* enable dptx interface */ 2297 if (dai->id == MT8188_AFE_IO_DPTX) 2298 regmap_set_bits(afe->regmap, AFE_DPTX_CON, AFE_DPTX_CON_ON); 2299 2300 /* enable etdm_out3 */ 2301 return mt8188_afe_enable_etdm(afe, dai->id); 2302 } 2303 2304 static int mtk_dai_hdmitx_dptx_set_sysclk(struct snd_soc_dai *dai, 2305 int clk_id, 2306 unsigned int freq, 2307 int dir) 2308 { 2309 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 2310 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2311 struct mtk_dai_etdm_priv *etdm_data; 2312 2313 if (!is_valid_etdm_dai(dai->id)) 2314 return -EINVAL; 2315 etdm_data = afe_priv->dai_priv[dai->id]; 2316 2317 dev_dbg(dai->dev, "%s id %d freq %u, dir %d\n", 2318 __func__, dai->id, freq, dir); 2319 2320 etdm_data->mclk_dir = dir; 2321 return mtk_dai_etdm_cal_mclk(afe, freq, dai->id); 2322 } 2323 2324 static const struct snd_soc_dai_ops mtk_dai_etdm_ops = { 2325 .startup = mtk_dai_etdm_startup, 2326 .shutdown = mtk_dai_etdm_shutdown, 2327 .hw_params = mtk_dai_etdm_hw_params, 2328 .prepare = mtk_dai_etdm_prepare, 2329 .set_sysclk = mtk_dai_etdm_set_sysclk, 2330 .set_fmt = mtk_dai_etdm_set_fmt, 2331 .set_tdm_slot = mtk_dai_etdm_set_tdm_slot, 2332 }; 2333 2334 static const struct snd_soc_dai_ops mtk_dai_hdmitx_dptx_ops = { 2335 .startup = mtk_dai_hdmitx_dptx_startup, 2336 .shutdown = mtk_dai_hdmitx_dptx_shutdown, 2337 .hw_params = mtk_dai_hdmitx_dptx_hw_params, 2338 .prepare = mtk_dai_hdmitx_dptx_prepare, 2339 .set_sysclk = mtk_dai_hdmitx_dptx_set_sysclk, 2340 .set_fmt = mtk_dai_etdm_set_fmt, 2341 }; 2342 2343 /* dai driver */ 2344 #define MTK_ETDM_RATES (SNDRV_PCM_RATE_8000_192000) 2345 2346 #define MTK_ETDM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 2347 SNDRV_PCM_FMTBIT_S24_LE |\ 2348 SNDRV_PCM_FMTBIT_S32_LE) 2349 2350 static struct snd_soc_dai_driver mtk_dai_etdm_driver[] = { 2351 { 2352 .name = "DPTX", 2353 .id = MT8188_AFE_IO_DPTX, 2354 .playback = { 2355 .stream_name = "DPTX", 2356 .channels_min = 1, 2357 .channels_max = 8, 2358 .rates = MTK_ETDM_RATES, 2359 .formats = MTK_ETDM_FORMATS, 2360 }, 2361 .ops = &mtk_dai_hdmitx_dptx_ops, 2362 }, 2363 { 2364 .name = "ETDM1_IN", 2365 .id = MT8188_AFE_IO_ETDM1_IN, 2366 .capture = { 2367 .stream_name = "ETDM1_IN", 2368 .channels_min = 1, 2369 .channels_max = 16, 2370 .rates = MTK_ETDM_RATES, 2371 .formats = MTK_ETDM_FORMATS, 2372 }, 2373 .ops = &mtk_dai_etdm_ops, 2374 }, 2375 { 2376 .name = "ETDM2_IN", 2377 .id = MT8188_AFE_IO_ETDM2_IN, 2378 .capture = { 2379 .stream_name = "ETDM2_IN", 2380 .channels_min = 1, 2381 .channels_max = 16, 2382 .rates = MTK_ETDM_RATES, 2383 .formats = MTK_ETDM_FORMATS, 2384 }, 2385 .ops = &mtk_dai_etdm_ops, 2386 }, 2387 { 2388 .name = "ETDM1_OUT", 2389 .id = MT8188_AFE_IO_ETDM1_OUT, 2390 .playback = { 2391 .stream_name = "ETDM1_OUT", 2392 .channels_min = 1, 2393 .channels_max = 16, 2394 .rates = MTK_ETDM_RATES, 2395 .formats = MTK_ETDM_FORMATS, 2396 }, 2397 .ops = &mtk_dai_etdm_ops, 2398 }, 2399 { 2400 .name = "ETDM2_OUT", 2401 .id = MT8188_AFE_IO_ETDM2_OUT, 2402 .playback = { 2403 .stream_name = "ETDM2_OUT", 2404 .channels_min = 1, 2405 .channels_max = 16, 2406 .rates = MTK_ETDM_RATES, 2407 .formats = MTK_ETDM_FORMATS, 2408 }, 2409 .ops = &mtk_dai_etdm_ops, 2410 }, 2411 { 2412 .name = "ETDM3_OUT", 2413 .id = MT8188_AFE_IO_ETDM3_OUT, 2414 .playback = { 2415 .stream_name = "ETDM3_OUT", 2416 .channels_min = 1, 2417 .channels_max = 8, 2418 .rates = MTK_ETDM_RATES, 2419 .formats = MTK_ETDM_FORMATS, 2420 }, 2421 .ops = &mtk_dai_hdmitx_dptx_ops, 2422 }, 2423 }; 2424 2425 static void mt8188_etdm_update_sync_info(struct mtk_base_afe *afe) 2426 { 2427 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2428 struct mtk_dai_etdm_priv *etdm_data; 2429 struct mtk_dai_etdm_priv *mst_data; 2430 int mst_dai_id; 2431 int i; 2432 2433 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2434 etdm_data = afe_priv->dai_priv[i]; 2435 if (etdm_data->cowork_source_id != COWORK_ETDM_NONE) { 2436 mst_dai_id = etdm_data->cowork_source_id; 2437 mst_data = afe_priv->dai_priv[mst_dai_id]; 2438 if (mst_data->cowork_source_id != COWORK_ETDM_NONE) 2439 dev_err(afe->dev, "%s [%d] wrong sync source\n", 2440 __func__, i); 2441 mst_data->cowork_slv_id[mst_data->cowork_slv_count] = i; 2442 mst_data->cowork_slv_count++; 2443 } 2444 } 2445 } 2446 2447 static void mt8188_dai_etdm_parse_of(struct mtk_base_afe *afe) 2448 { 2449 const struct device_node *of_node = afe->dev->of_node; 2450 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2451 struct mtk_dai_etdm_priv *etdm_data; 2452 char prop[48]; 2453 u8 disable_chn[MT8188_ETDM_MAX_CHANNELS]; 2454 int max_chn = MT8188_ETDM_MAX_CHANNELS; 2455 unsigned int sync_id; 2456 u32 sel; 2457 int ret; 2458 int dai_id; 2459 int i, j; 2460 struct { 2461 const char *name; 2462 const unsigned int sync_id; 2463 } of_afe_etdms[MT8188_AFE_IO_ETDM_NUM] = { 2464 {"etdm-in1", ETDM_SYNC_FROM_IN1}, 2465 {"etdm-in2", ETDM_SYNC_FROM_IN2}, 2466 {"etdm-out1", ETDM_SYNC_FROM_OUT1}, 2467 {"etdm-out2", ETDM_SYNC_FROM_OUT2}, 2468 {"etdm-out3", ETDM_SYNC_FROM_OUT3}, 2469 }; 2470 2471 for (i = 0; i < MT8188_AFE_IO_ETDM_NUM; i++) { 2472 dai_id = ETDM_TO_DAI_ID(i); 2473 etdm_data = afe_priv->dai_priv[dai_id]; 2474 2475 snprintf(prop, sizeof(prop), "mediatek,%s-multi-pin-mode", 2476 of_afe_etdms[i].name); 2477 2478 etdm_data->data_mode = of_property_read_bool(of_node, prop); 2479 2480 snprintf(prop, sizeof(prop), "mediatek,%s-cowork-source", 2481 of_afe_etdms[i].name); 2482 2483 ret = of_property_read_u32(of_node, prop, &sel); 2484 if (ret == 0) { 2485 if (sel >= MT8188_AFE_IO_ETDM_NUM) { 2486 dev_err(afe->dev, "%s invalid id=%d\n", 2487 __func__, sel); 2488 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2489 } else { 2490 sync_id = of_afe_etdms[sel].sync_id; 2491 etdm_data->cowork_source_id = 2492 sync_to_dai_id(sync_id); 2493 } 2494 } else { 2495 etdm_data->cowork_source_id = COWORK_ETDM_NONE; 2496 } 2497 } 2498 2499 /* etdm in only */ 2500 for (i = 0; i < 2; i++) { 2501 dai_id = ETDM_TO_DAI_ID(i); 2502 etdm_data = afe_priv->dai_priv[dai_id]; 2503 2504 snprintf(prop, sizeof(prop), "mediatek,%s-chn-disabled", 2505 of_afe_etdms[i].name); 2506 2507 ret = of_property_read_variable_u8_array(of_node, prop, 2508 disable_chn, 2509 1, max_chn); 2510 if (ret < 0) 2511 continue; 2512 2513 for (j = 0; j < ret; j++) { 2514 if (disable_chn[j] >= MT8188_ETDM_MAX_CHANNELS) 2515 dev_err(afe->dev, "%s [%d] invalid chn %u\n", 2516 __func__, j, disable_chn[j]); 2517 else 2518 etdm_data->in_disable_ch[disable_chn[j]] = true; 2519 } 2520 } 2521 mt8188_etdm_update_sync_info(afe); 2522 } 2523 2524 static int init_etdm_priv_data(struct mtk_base_afe *afe) 2525 { 2526 struct mt8188_afe_private *afe_priv = afe->platform_priv; 2527 struct mtk_dai_etdm_priv *etdm_priv; 2528 int i; 2529 2530 for (i = MT8188_AFE_IO_ETDM_START; i < MT8188_AFE_IO_ETDM_END; i++) { 2531 etdm_priv = devm_kzalloc(afe->dev, 2532 sizeof(struct mtk_dai_etdm_priv), 2533 GFP_KERNEL); 2534 if (!etdm_priv) 2535 return -ENOMEM; 2536 2537 afe_priv->dai_priv[i] = etdm_priv; 2538 } 2539 2540 afe_priv->dai_priv[MT8188_AFE_IO_DPTX] = 2541 afe_priv->dai_priv[MT8188_AFE_IO_ETDM3_OUT]; 2542 2543 mt8188_dai_etdm_parse_of(afe); 2544 return 0; 2545 } 2546 2547 int mt8188_dai_etdm_register(struct mtk_base_afe *afe) 2548 { 2549 struct mtk_base_afe_dai *dai; 2550 2551 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2552 if (!dai) 2553 return -ENOMEM; 2554 2555 list_add(&dai->list, &afe->sub_dais); 2556 2557 dai->dai_drivers = mtk_dai_etdm_driver; 2558 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_etdm_driver); 2559 2560 dai->dapm_widgets = mtk_dai_etdm_widgets; 2561 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_etdm_widgets); 2562 dai->dapm_routes = mtk_dai_etdm_routes; 2563 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_etdm_routes); 2564 dai->controls = mtk_dai_etdm_controls; 2565 dai->num_controls = ARRAY_SIZE(mtk_dai_etdm_controls); 2566 2567 return init_etdm_priv_data(afe); 2568 } 2569