1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI ADDA Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include "mt8188-afe-clk.h" 15 #include "mt8188-afe-common.h" 16 #include "mt8188-reg.h" 17 18 #define ADDA_HIRES_THRES 48000 19 20 enum { 21 SUPPLY_SEQ_ADDA_DL_ON, 22 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 23 SUPPLY_SEQ_ADDA_UL_ON, 24 SUPPLY_SEQ_ADDA_AFE_ON, 25 }; 26 27 enum { 28 MTK_AFE_ADDA_DL_RATE_8K = 0, 29 MTK_AFE_ADDA_DL_RATE_11K = 1, 30 MTK_AFE_ADDA_DL_RATE_12K = 2, 31 MTK_AFE_ADDA_DL_RATE_16K = 3, 32 MTK_AFE_ADDA_DL_RATE_22K = 4, 33 MTK_AFE_ADDA_DL_RATE_24K = 5, 34 MTK_AFE_ADDA_DL_RATE_32K = 6, 35 MTK_AFE_ADDA_DL_RATE_44K = 7, 36 MTK_AFE_ADDA_DL_RATE_48K = 8, 37 MTK_AFE_ADDA_DL_RATE_96K = 9, 38 MTK_AFE_ADDA_DL_RATE_192K = 10, 39 }; 40 41 enum { 42 MTK_AFE_ADDA_UL_RATE_8K = 0, 43 MTK_AFE_ADDA_UL_RATE_16K = 1, 44 MTK_AFE_ADDA_UL_RATE_32K = 2, 45 MTK_AFE_ADDA_UL_RATE_48K = 3, 46 MTK_AFE_ADDA_UL_RATE_96K = 4, 47 MTK_AFE_ADDA_UL_RATE_192K = 5, 48 }; 49 50 enum { 51 DELAY_DATA_MISO1 = 0, 52 DELAY_DATA_MISO0 = 1, 53 }; 54 55 struct mtk_dai_adda_priv { 56 bool hires_required; 57 }; 58 59 static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe, 60 unsigned int rate) 61 { 62 switch (rate) { 63 case 8000: 64 return MTK_AFE_ADDA_DL_RATE_8K; 65 case 11025: 66 return MTK_AFE_ADDA_DL_RATE_11K; 67 case 12000: 68 return MTK_AFE_ADDA_DL_RATE_12K; 69 case 16000: 70 return MTK_AFE_ADDA_DL_RATE_16K; 71 case 22050: 72 return MTK_AFE_ADDA_DL_RATE_22K; 73 case 24000: 74 return MTK_AFE_ADDA_DL_RATE_24K; 75 case 32000: 76 return MTK_AFE_ADDA_DL_RATE_32K; 77 case 44100: 78 return MTK_AFE_ADDA_DL_RATE_44K; 79 case 48000: 80 return MTK_AFE_ADDA_DL_RATE_48K; 81 case 96000: 82 return MTK_AFE_ADDA_DL_RATE_96K; 83 case 192000: 84 return MTK_AFE_ADDA_DL_RATE_192K; 85 default: 86 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 87 __func__, rate); 88 return MTK_AFE_ADDA_DL_RATE_48K; 89 } 90 } 91 92 static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe, 93 unsigned int rate) 94 { 95 switch (rate) { 96 case 8000: 97 return MTK_AFE_ADDA_UL_RATE_8K; 98 case 16000: 99 return MTK_AFE_ADDA_UL_RATE_16K; 100 case 32000: 101 return MTK_AFE_ADDA_UL_RATE_32K; 102 case 48000: 103 return MTK_AFE_ADDA_UL_RATE_48K; 104 case 96000: 105 return MTK_AFE_ADDA_UL_RATE_96K; 106 case 192000: 107 return MTK_AFE_ADDA_UL_RATE_192K; 108 default: 109 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 110 __func__, rate); 111 return MTK_AFE_ADDA_UL_RATE_48K; 112 } 113 } 114 115 static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe) 116 { 117 struct mt8188_afe_private *afe_priv = afe->platform_priv; 118 struct mtkaif_param *param = &afe_priv->mtkaif_params; 119 int delay_data; 120 int delay_cycle; 121 unsigned int mask = 0; 122 unsigned int val = 0; 123 124 /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */ 125 regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 126 MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 127 128 regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2); 129 130 if (!param->mtkaif_calibration_ok) { 131 dev_info(afe->dev, "%s(), calibration fail\n", __func__); 132 return 0; 133 } 134 135 /* set delay for ch1, ch2 */ 136 if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >= 137 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) { 138 delay_data = DELAY_DATA_MISO1; 139 delay_cycle = 140 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] - 141 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]; 142 } else { 143 delay_data = DELAY_DATA_MISO0; 144 delay_cycle = 145 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] - 146 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0]; 147 } 148 149 val = 0; 150 mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 151 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle); 152 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data); 153 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val); 154 155 return 0; 156 } 157 158 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 159 struct snd_kcontrol *kcontrol, 160 int event) 161 { 162 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 163 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 164 165 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 166 __func__, w->name, event); 167 168 switch (event) { 169 case SND_SOC_DAPM_PRE_PMU: 170 mt8188_adda_mtkaif_init(afe); 171 break; 172 default: 173 break; 174 } 175 176 return 0; 177 } 178 179 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 180 struct snd_kcontrol *kcontrol, 181 int event) 182 { 183 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 184 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 185 186 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 187 __func__, w->name, event); 188 189 switch (event) { 190 case SND_SOC_DAPM_POST_PMD: 191 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 192 usleep_range(125, 135); 193 break; 194 default: 195 break; 196 } 197 198 return 0; 199 } 200 201 static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic) 202 { 203 unsigned int reg = AFE_ADDA_UL_SRC_CON0; 204 unsigned int val; 205 206 val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | 207 UL_MODE_3P25M_CH2_CTL); 208 209 /* turn on dmic, ch1, ch2 */ 210 if (dmic) 211 regmap_set_bits(afe->regmap, reg, val); 212 else 213 regmap_clear_bits(afe->regmap, reg, val); 214 } 215 216 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 217 struct snd_kcontrol *kcontrol, 218 int event) 219 { 220 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 221 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 222 struct mt8188_afe_private *afe_priv = afe->platform_priv; 223 struct mtkaif_param *param = &afe_priv->mtkaif_params; 224 225 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 226 __func__, w->name, event); 227 228 switch (event) { 229 case SND_SOC_DAPM_PRE_PMU: 230 mtk_adda_ul_mictype(afe, param->mtkaif_dmic_on); 231 break; 232 case SND_SOC_DAPM_POST_PMD: 233 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 234 usleep_range(125, 135); 235 break; 236 default: 237 break; 238 } 239 240 return 0; 241 } 242 243 static struct mtk_dai_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe, 244 const char *name) 245 { 246 struct mt8188_afe_private *afe_priv = afe->platform_priv; 247 248 if (strstr(name, "aud_adc_hires")) 249 return afe_priv->dai_priv[MT8188_AFE_IO_UL_SRC]; 250 else if (strstr(name, "aud_dac_hires")) 251 return afe_priv->dai_priv[MT8188_AFE_IO_DL_SRC]; 252 else 253 return NULL; 254 } 255 256 static int mtk_afe_adda_hires_connect(struct snd_soc_dapm_widget *source, 257 struct snd_soc_dapm_widget *sink) 258 { 259 struct snd_soc_dapm_widget *w = source; 260 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 261 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 262 struct mtk_dai_adda_priv *adda_priv; 263 264 adda_priv = get_adda_priv_by_name(afe, w->name); 265 266 if (!adda_priv) { 267 dev_dbg(afe->dev, "adda_priv == NULL"); 268 return 0; 269 } 270 271 return (adda_priv->hires_required) ? 1 : 0; 272 } 273 274 static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = { 275 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0), 276 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0), 277 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0), 278 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0), 279 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0), 280 }; 281 282 static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = { 283 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0), 284 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0), 285 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0), 286 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0), 287 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0), 288 }; 289 290 static const char * const adda_dlgain_mux_map[] = { 291 "Bypass", "Connect", 292 }; 293 294 static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum, 295 SND_SOC_NOPM, 0, 296 adda_dlgain_mux_map); 297 298 static const struct snd_kcontrol_new adda_dlgain_mux_control = 299 SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum); 300 301 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 302 SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0), 303 SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0), 304 305 SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0, 306 mtk_dai_adda_o176_mix, 307 ARRAY_SIZE(mtk_dai_adda_o176_mix)), 308 SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0, 309 mtk_dai_adda_o177_mix, 310 ARRAY_SIZE(mtk_dai_adda_o177_mix)), 311 312 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 313 AFE_ADDA_UL_DL_CON0, 314 ADDA_AFE_ON_SHIFT, 0, 315 NULL, 316 0), 317 318 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 319 AFE_ADDA_DL_SRC2_CON0, 320 DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0, 321 mtk_adda_dl_event, 322 SND_SOC_DAPM_POST_PMD), 323 324 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 325 AFE_ADDA_UL_SRC_CON0, 326 UL_SRC_ON_TMP_CTL_SHIFT, 0, 327 mtk_adda_ul_event, 328 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 329 330 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 331 SND_SOC_NOPM, 332 0, 0, 333 mtk_adda_mtkaif_cfg_event, 334 SND_SOC_DAPM_PRE_PMU), 335 336 SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0, 337 &adda_dlgain_mux_control), 338 339 SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0, 340 DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0), 341 342 SND_SOC_DAPM_INPUT("ADDA_INPUT"), 343 SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"), 344 345 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"), 346 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"), 347 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"), 348 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"), 349 }; 350 351 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 352 {"ADDA Capture", NULL, "ADDA Enable"}, 353 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 354 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 355 {"ADDA Capture", NULL, "aud_adc"}, 356 {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adda_hires_connect}, 357 358 {"I168", NULL, "ADDA Capture"}, 359 {"I169", NULL, "ADDA Capture"}, 360 361 {"ADDA Playback", NULL, "ADDA Enable"}, 362 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 363 {"ADDA Playback", NULL, "aud_dac"}, 364 {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_adda_hires_connect}, 365 366 {"DL_GAIN", NULL, "O176"}, 367 {"DL_GAIN", NULL, "O177"}, 368 369 {"DL_GAIN_MUX", "Bypass", "O176"}, 370 {"DL_GAIN_MUX", "Bypass", "O177"}, 371 {"DL_GAIN_MUX", "Connect", "DL_GAIN"}, 372 373 {"ADDA Playback", NULL, "DL_GAIN_MUX"}, 374 375 {"O176", "I000 Switch", "I000"}, 376 {"O177", "I001 Switch", "I001"}, 377 378 {"O176", "I002 Switch", "I002"}, 379 {"O177", "I003 Switch", "I003"}, 380 381 {"O176", "I020 Switch", "I020"}, 382 {"O177", "I021 Switch", "I021"}, 383 384 {"O176", "I022 Switch", "I022"}, 385 {"O177", "I023 Switch", "I023"}, 386 387 {"O176", "I070 Switch", "I070"}, 388 {"O177", "I071 Switch", "I071"}, 389 390 {"ADDA Capture", NULL, "ADDA_INPUT"}, 391 {"ADDA_OUTPUT", NULL, "ADDA Playback"}, 392 }; 393 394 static int mt8188_adda_dmic_get(struct snd_kcontrol *kcontrol, 395 struct snd_ctl_elem_value *ucontrol) 396 { 397 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 398 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 399 struct mt8188_afe_private *afe_priv = afe->platform_priv; 400 struct mtkaif_param *param = &afe_priv->mtkaif_params; 401 402 ucontrol->value.integer.value[0] = param->mtkaif_dmic_on; 403 return 0; 404 } 405 406 static int mt8188_adda_dmic_set(struct snd_kcontrol *kcontrol, 407 struct snd_ctl_elem_value *ucontrol) 408 { 409 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 410 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 411 struct mt8188_afe_private *afe_priv = afe->platform_priv; 412 struct mtkaif_param *param = &afe_priv->mtkaif_params; 413 int dmic_on; 414 415 dmic_on = !!ucontrol->value.integer.value[0]; 416 417 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 418 __func__, kcontrol->id.name, dmic_on); 419 420 if (param->mtkaif_dmic_on == dmic_on) 421 return 0; 422 423 param->mtkaif_dmic_on = dmic_on; 424 return 1; 425 } 426 427 static const struct snd_kcontrol_new mtk_dai_adda_controls[] = { 428 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 429 DL_2_GAIN_CTL_PRE_SHIFT, 65535, 0), 430 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 431 mt8188_adda_dmic_get, mt8188_adda_dmic_set), 432 }; 433 434 static int mtk_dai_da_configure(struct mtk_base_afe *afe, 435 unsigned int rate, int id) 436 { 437 unsigned int val = 0; 438 unsigned int mask = 0; 439 440 /* set sampling rate */ 441 mask |= DL_2_INPUT_MODE_CTL_MASK; 442 val |= FIELD_PREP(DL_2_INPUT_MODE_CTL_MASK, 443 afe_adda_dl_rate_transform(afe, rate)); 444 445 /* turn off saturation */ 446 mask |= DL_2_CH1_SATURATION_EN_CTL; 447 mask |= DL_2_CH2_SATURATION_EN_CTL; 448 449 /* turn off mute function */ 450 mask |= DL_2_MUTE_CH1_OFF_CTL_PRE; 451 mask |= DL_2_MUTE_CH2_OFF_CTL_PRE; 452 val |= DL_2_MUTE_CH1_OFF_CTL_PRE; 453 val |= DL_2_MUTE_CH2_OFF_CTL_PRE; 454 455 /* set voice input data if input sample rate is 8k or 16k */ 456 mask |= DL_2_VOICE_MODE_CTL_PRE; 457 if (rate == 8000 || rate == 16000) 458 val |= DL_2_VOICE_MODE_CTL_PRE; 459 460 regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val); 461 462 /* new 2nd sdm */ 463 regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, 464 DL_USE_NEW_2ND_SDM); 465 466 return 0; 467 } 468 469 static int mtk_dai_ad_configure(struct mtk_base_afe *afe, 470 unsigned int rate, int id) 471 { 472 unsigned int val; 473 unsigned int mask; 474 475 mask = UL_VOICE_MODE_CTL_MASK; 476 val = FIELD_PREP(UL_VOICE_MODE_CTL_MASK, 477 afe_adda_ul_rate_transform(afe, rate)); 478 479 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 480 mask, val); 481 return 0; 482 } 483 484 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 485 struct snd_pcm_hw_params *params, 486 struct snd_soc_dai *dai) 487 { 488 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 489 struct mt8188_afe_private *afe_priv = afe->platform_priv; 490 struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id]; 491 unsigned int rate = params_rate(params); 492 int id = dai->id; 493 int ret = 0; 494 495 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %u\n", 496 __func__, id, substream->stream, rate); 497 498 adda_priv->hires_required = (rate > ADDA_HIRES_THRES); 499 500 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 501 ret = mtk_dai_da_configure(afe, rate, id); 502 else 503 ret = mtk_dai_ad_configure(afe, rate, id); 504 505 return ret; 506 } 507 508 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 509 .hw_params = mtk_dai_adda_hw_params, 510 }; 511 512 /* dai driver */ 513 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 514 SNDRV_PCM_RATE_96000 |\ 515 SNDRV_PCM_RATE_192000) 516 517 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 518 SNDRV_PCM_RATE_16000 |\ 519 SNDRV_PCM_RATE_32000 |\ 520 SNDRV_PCM_RATE_48000 |\ 521 SNDRV_PCM_RATE_96000 |\ 522 SNDRV_PCM_RATE_192000) 523 524 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 525 SNDRV_PCM_FMTBIT_S24_LE |\ 526 SNDRV_PCM_FMTBIT_S32_LE) 527 528 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 529 { 530 .name = "DL_SRC", 531 .id = MT8188_AFE_IO_DL_SRC, 532 .playback = { 533 .stream_name = "ADDA Playback", 534 .channels_min = 1, 535 .channels_max = 2, 536 .rates = MTK_ADDA_PLAYBACK_RATES, 537 .formats = MTK_ADDA_FORMATS, 538 }, 539 .ops = &mtk_dai_adda_ops, 540 }, 541 { 542 .name = "UL_SRC", 543 .id = MT8188_AFE_IO_UL_SRC, 544 .capture = { 545 .stream_name = "ADDA Capture", 546 .channels_min = 1, 547 .channels_max = 2, 548 .rates = MTK_ADDA_CAPTURE_RATES, 549 .formats = MTK_ADDA_FORMATS, 550 }, 551 .ops = &mtk_dai_adda_ops, 552 }, 553 }; 554 555 static int init_adda_priv_data(struct mtk_base_afe *afe) 556 { 557 struct mt8188_afe_private *afe_priv = afe->platform_priv; 558 struct mtk_dai_adda_priv *adda_priv; 559 int adda_dai_list[] = {MT8188_AFE_IO_DL_SRC, MT8188_AFE_IO_UL_SRC}; 560 int i; 561 562 for (i = 0; i < ARRAY_SIZE(adda_dai_list); i++) { 563 adda_priv = devm_kzalloc(afe->dev, 564 sizeof(struct mtk_dai_adda_priv), 565 GFP_KERNEL); 566 if (!adda_priv) 567 return -ENOMEM; 568 569 afe_priv->dai_priv[adda_dai_list[i]] = adda_priv; 570 } 571 572 return 0; 573 } 574 575 int mt8188_dai_adda_register(struct mtk_base_afe *afe) 576 { 577 struct mtk_base_afe_dai *dai; 578 579 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 580 if (!dai) 581 return -ENOMEM; 582 583 list_add(&dai->list, &afe->sub_dais); 584 585 dai->dai_drivers = mtk_dai_adda_driver; 586 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 587 588 dai->dapm_widgets = mtk_dai_adda_widgets; 589 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 590 dai->dapm_routes = mtk_dai_adda_routes; 591 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 592 dai->controls = mtk_dai_adda_controls; 593 dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls); 594 595 return init_adda_priv_data(afe); 596 } 597