1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek ALSA SoC Audio DAI ADDA Control 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/delay.h> 13 #include <linux/regmap.h> 14 #include "mt8188-afe-clk.h" 15 #include "mt8188-afe-common.h" 16 #include "mt8188-reg.h" 17 18 #define ADDA_HIRES_THRES 48000 19 20 enum { 21 SUPPLY_SEQ_ADDA_DL_ON, 22 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 23 SUPPLY_SEQ_ADDA_UL_ON, 24 SUPPLY_SEQ_ADDA_AFE_ON, 25 }; 26 27 enum { 28 MTK_AFE_ADDA_DL_RATE_8K = 0, 29 MTK_AFE_ADDA_DL_RATE_11K = 1, 30 MTK_AFE_ADDA_DL_RATE_12K = 2, 31 MTK_AFE_ADDA_DL_RATE_16K = 3, 32 MTK_AFE_ADDA_DL_RATE_22K = 4, 33 MTK_AFE_ADDA_DL_RATE_24K = 5, 34 MTK_AFE_ADDA_DL_RATE_32K = 6, 35 MTK_AFE_ADDA_DL_RATE_44K = 7, 36 MTK_AFE_ADDA_DL_RATE_48K = 8, 37 MTK_AFE_ADDA_DL_RATE_96K = 9, 38 MTK_AFE_ADDA_DL_RATE_192K = 10, 39 }; 40 41 enum { 42 MTK_AFE_ADDA_UL_RATE_8K = 0, 43 MTK_AFE_ADDA_UL_RATE_16K = 1, 44 MTK_AFE_ADDA_UL_RATE_32K = 2, 45 MTK_AFE_ADDA_UL_RATE_48K = 3, 46 MTK_AFE_ADDA_UL_RATE_96K = 4, 47 MTK_AFE_ADDA_UL_RATE_192K = 5, 48 }; 49 50 enum { 51 DELAY_DATA_MISO1 = 0, 52 DELAY_DATA_MISO0 = 1, 53 }; 54 55 struct mtk_dai_adda_priv { 56 unsigned int dl_rate; 57 unsigned int ul_rate; 58 }; 59 60 static unsigned int afe_adda_dl_rate_transform(struct mtk_base_afe *afe, 61 unsigned int rate) 62 { 63 switch (rate) { 64 case 8000: 65 return MTK_AFE_ADDA_DL_RATE_8K; 66 case 11025: 67 return MTK_AFE_ADDA_DL_RATE_11K; 68 case 12000: 69 return MTK_AFE_ADDA_DL_RATE_12K; 70 case 16000: 71 return MTK_AFE_ADDA_DL_RATE_16K; 72 case 22050: 73 return MTK_AFE_ADDA_DL_RATE_22K; 74 case 24000: 75 return MTK_AFE_ADDA_DL_RATE_24K; 76 case 32000: 77 return MTK_AFE_ADDA_DL_RATE_32K; 78 case 44100: 79 return MTK_AFE_ADDA_DL_RATE_44K; 80 case 48000: 81 return MTK_AFE_ADDA_DL_RATE_48K; 82 case 96000: 83 return MTK_AFE_ADDA_DL_RATE_96K; 84 case 192000: 85 return MTK_AFE_ADDA_DL_RATE_192K; 86 default: 87 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 88 __func__, rate); 89 return MTK_AFE_ADDA_DL_RATE_48K; 90 } 91 } 92 93 static unsigned int afe_adda_ul_rate_transform(struct mtk_base_afe *afe, 94 unsigned int rate) 95 { 96 switch (rate) { 97 case 8000: 98 return MTK_AFE_ADDA_UL_RATE_8K; 99 case 16000: 100 return MTK_AFE_ADDA_UL_RATE_16K; 101 case 32000: 102 return MTK_AFE_ADDA_UL_RATE_32K; 103 case 48000: 104 return MTK_AFE_ADDA_UL_RATE_48K; 105 case 96000: 106 return MTK_AFE_ADDA_UL_RATE_96K; 107 case 192000: 108 return MTK_AFE_ADDA_UL_RATE_192K; 109 default: 110 dev_info(afe->dev, "%s(), rate %u invalid, use 48kHz!!!\n", 111 __func__, rate); 112 return MTK_AFE_ADDA_UL_RATE_48K; 113 } 114 } 115 116 static int mt8188_adda_mtkaif_init(struct mtk_base_afe *afe) 117 { 118 struct mt8188_afe_private *afe_priv = afe->platform_priv; 119 struct mtkaif_param *param = &afe_priv->mtkaif_params; 120 int delay_data; 121 int delay_cycle; 122 unsigned int mask = 0; 123 unsigned int val = 0; 124 125 /* set rx protocol 2 & mtkaif_rxif_clkinv_adc inverse */ 126 regmap_set_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 127 MTKAIF_RXIF_CLKINV_ADC | MTKAIF_RXIF_PROTOCOL2); 128 129 regmap_set_bits(afe->regmap, AFE_AUD_PAD_TOP, RG_RX_PROTOCOL2); 130 131 if (!param->mtkaif_calibration_ok) { 132 dev_info(afe->dev, "%s(), calibration fail\n", __func__); 133 return 0; 134 } 135 136 /* set delay for ch1, ch2 */ 137 if (param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] >= 138 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]) { 139 delay_data = DELAY_DATA_MISO1; 140 delay_cycle = 141 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0] - 142 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1]; 143 } else { 144 delay_data = DELAY_DATA_MISO0; 145 delay_cycle = 146 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_1] - 147 param->mtkaif_phase_cycle[MT8188_MTKAIF_MISO_0]; 148 } 149 150 val = 0; 151 mask = (MTKAIF_RXIF_DELAY_DATA | MTKAIF_RXIF_DELAY_CYCLE_MASK); 152 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_CYCLE_MASK, delay_cycle); 153 val |= FIELD_PREP(MTKAIF_RXIF_DELAY_DATA, delay_data); 154 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG2, mask, val); 155 156 return 0; 157 } 158 159 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 160 struct snd_kcontrol *kcontrol, 161 int event) 162 { 163 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 164 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 165 166 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 167 __func__, w->name, event); 168 169 switch (event) { 170 case SND_SOC_DAPM_PRE_PMU: 171 mt8188_adda_mtkaif_init(afe); 172 break; 173 default: 174 break; 175 } 176 177 return 0; 178 } 179 180 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 181 struct snd_kcontrol *kcontrol, 182 int event) 183 { 184 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 185 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 186 187 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 188 __func__, w->name, event); 189 190 switch (event) { 191 case SND_SOC_DAPM_POST_PMD: 192 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 193 usleep_range(125, 135); 194 break; 195 default: 196 break; 197 } 198 199 return 0; 200 } 201 202 static void mtk_adda_ul_mictype(struct mtk_base_afe *afe, bool dmic) 203 { 204 unsigned int reg = AFE_ADDA_UL_SRC_CON0; 205 unsigned int val; 206 207 val = (UL_SDM3_LEVEL_CTL | UL_MODE_3P25M_CH1_CTL | 208 UL_MODE_3P25M_CH2_CTL); 209 210 /* turn on dmic, ch1, ch2 */ 211 if (dmic) 212 regmap_set_bits(afe->regmap, reg, val); 213 else 214 regmap_clear_bits(afe->regmap, reg, val); 215 } 216 217 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 218 struct snd_kcontrol *kcontrol, 219 int event) 220 { 221 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 222 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 223 struct mt8188_afe_private *afe_priv = afe->platform_priv; 224 struct mtkaif_param *param = &afe_priv->mtkaif_params; 225 226 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 227 __func__, w->name, event); 228 229 switch (event) { 230 case SND_SOC_DAPM_PRE_PMU: 231 mtk_adda_ul_mictype(afe, param->mtkaif_dmic_on); 232 break; 233 case SND_SOC_DAPM_POST_PMD: 234 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 235 usleep_range(125, 135); 236 break; 237 default: 238 break; 239 } 240 241 return 0; 242 } 243 244 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 245 struct snd_soc_dapm_widget *sink) 246 { 247 struct snd_soc_dapm_widget *w = source; 248 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 249 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 250 struct mt8188_afe_private *afe_priv = afe->platform_priv; 251 struct mtk_dai_adda_priv *adda_priv; 252 253 adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 254 255 if (!adda_priv) { 256 dev_err(afe->dev, "%s adda_priv == NULL", __func__); 257 return 0; 258 } 259 260 return !!(adda_priv->ul_rate > ADDA_HIRES_THRES); 261 } 262 263 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 264 struct snd_soc_dapm_widget *sink) 265 { 266 struct snd_soc_dapm_widget *w = source; 267 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 268 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 269 struct mt8188_afe_private *afe_priv = afe->platform_priv; 270 struct mtk_dai_adda_priv *adda_priv; 271 272 adda_priv = afe_priv->dai_priv[MT8188_AFE_IO_ADDA]; 273 274 if (!adda_priv) { 275 dev_err(afe->dev, "%s adda_priv == NULL", __func__); 276 return 0; 277 } 278 279 return !!(adda_priv->dl_rate > ADDA_HIRES_THRES); 280 } 281 282 static const struct snd_kcontrol_new mtk_dai_adda_o176_mix[] = { 283 SOC_DAPM_SINGLE_AUTODISABLE("I000 Switch", AFE_CONN176, 0, 1, 0), 284 SOC_DAPM_SINGLE_AUTODISABLE("I002 Switch", AFE_CONN176, 2, 1, 0), 285 SOC_DAPM_SINGLE_AUTODISABLE("I020 Switch", AFE_CONN176, 20, 1, 0), 286 SOC_DAPM_SINGLE_AUTODISABLE("I022 Switch", AFE_CONN176, 22, 1, 0), 287 SOC_DAPM_SINGLE_AUTODISABLE("I070 Switch", AFE_CONN176_2, 6, 1, 0), 288 }; 289 290 static const struct snd_kcontrol_new mtk_dai_adda_o177_mix[] = { 291 SOC_DAPM_SINGLE_AUTODISABLE("I001 Switch", AFE_CONN177, 1, 1, 0), 292 SOC_DAPM_SINGLE_AUTODISABLE("I003 Switch", AFE_CONN177, 3, 1, 0), 293 SOC_DAPM_SINGLE_AUTODISABLE("I021 Switch", AFE_CONN177, 21, 1, 0), 294 SOC_DAPM_SINGLE_AUTODISABLE("I023 Switch", AFE_CONN177, 23, 1, 0), 295 SOC_DAPM_SINGLE_AUTODISABLE("I071 Switch", AFE_CONN177_2, 7, 1, 0), 296 }; 297 298 static const char * const adda_dlgain_mux_map[] = { 299 "Bypass", "Connect", 300 }; 301 302 static SOC_ENUM_SINGLE_DECL(adda_dlgain_mux_map_enum, 303 SND_SOC_NOPM, 0, 304 adda_dlgain_mux_map); 305 306 static const struct snd_kcontrol_new adda_dlgain_mux_control = 307 SOC_DAPM_ENUM("DL_GAIN_MUX", adda_dlgain_mux_map_enum); 308 309 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 310 SND_SOC_DAPM_MIXER("I168", SND_SOC_NOPM, 0, 0, NULL, 0), 311 SND_SOC_DAPM_MIXER("I169", SND_SOC_NOPM, 0, 0, NULL, 0), 312 313 SND_SOC_DAPM_MIXER("O176", SND_SOC_NOPM, 0, 0, 314 mtk_dai_adda_o176_mix, 315 ARRAY_SIZE(mtk_dai_adda_o176_mix)), 316 SND_SOC_DAPM_MIXER("O177", SND_SOC_NOPM, 0, 0, 317 mtk_dai_adda_o177_mix, 318 ARRAY_SIZE(mtk_dai_adda_o177_mix)), 319 320 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 321 AFE_ADDA_UL_DL_CON0, 322 ADDA_AFE_ON_SHIFT, 0, 323 NULL, 324 0), 325 326 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 327 AFE_ADDA_DL_SRC2_CON0, 328 DL_2_SRC_ON_TMP_CTRL_PRE_SHIFT, 0, 329 mtk_adda_dl_event, 330 SND_SOC_DAPM_POST_PMD), 331 332 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 333 AFE_ADDA_UL_SRC_CON0, 334 UL_SRC_ON_TMP_CTL_SHIFT, 0, 335 mtk_adda_ul_event, 336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 337 338 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 339 SND_SOC_NOPM, 340 0, 0, 341 mtk_adda_mtkaif_cfg_event, 342 SND_SOC_DAPM_PRE_PMU), 343 344 SND_SOC_DAPM_MUX("DL_GAIN_MUX", SND_SOC_NOPM, 0, 0, 345 &adda_dlgain_mux_control), 346 347 SND_SOC_DAPM_PGA("DL_GAIN", AFE_ADDA_DL_SRC2_CON0, 348 DL_2_GAIN_ON_CTL_PRE_SHIFT, 0, NULL, 0), 349 350 SND_SOC_DAPM_INPUT("ADDA_INPUT"), 351 SND_SOC_DAPM_OUTPUT("ADDA_OUTPUT"), 352 353 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac"), 354 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc"), 355 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires"), 356 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires"), 357 }; 358 359 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 360 {"ADDA Capture", NULL, "ADDA Enable"}, 361 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 362 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 363 {"ADDA Capture", NULL, "aud_adc"}, 364 {"ADDA Capture", NULL, "aud_adc_hires", mtk_afe_adc_hires_connect}, 365 366 {"I168", NULL, "ADDA Capture"}, 367 {"I169", NULL, "ADDA Capture"}, 368 369 {"ADDA Playback", NULL, "ADDA Enable"}, 370 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 371 {"ADDA Playback", NULL, "aud_dac"}, 372 {"ADDA Playback", NULL, "aud_dac_hires", mtk_afe_dac_hires_connect}, 373 374 {"DL_GAIN", NULL, "O176"}, 375 {"DL_GAIN", NULL, "O177"}, 376 377 {"DL_GAIN_MUX", "Bypass", "O176"}, 378 {"DL_GAIN_MUX", "Bypass", "O177"}, 379 {"DL_GAIN_MUX", "Connect", "DL_GAIN"}, 380 381 {"ADDA Playback", NULL, "DL_GAIN_MUX"}, 382 383 {"O176", "I000 Switch", "I000"}, 384 {"O177", "I001 Switch", "I001"}, 385 386 {"O176", "I002 Switch", "I002"}, 387 {"O177", "I003 Switch", "I003"}, 388 389 {"O176", "I020 Switch", "I020"}, 390 {"O177", "I021 Switch", "I021"}, 391 392 {"O176", "I022 Switch", "I022"}, 393 {"O177", "I023 Switch", "I023"}, 394 395 {"O176", "I070 Switch", "I070"}, 396 {"O177", "I071 Switch", "I071"}, 397 398 {"ADDA Capture", NULL, "ADDA_INPUT"}, 399 {"ADDA_OUTPUT", NULL, "ADDA Playback"}, 400 }; 401 402 static int mt8188_adda_dmic_get(struct snd_kcontrol *kcontrol, 403 struct snd_ctl_elem_value *ucontrol) 404 { 405 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 406 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 407 struct mt8188_afe_private *afe_priv = afe->platform_priv; 408 struct mtkaif_param *param = &afe_priv->mtkaif_params; 409 410 ucontrol->value.integer.value[0] = param->mtkaif_dmic_on; 411 return 0; 412 } 413 414 static int mt8188_adda_dmic_set(struct snd_kcontrol *kcontrol, 415 struct snd_ctl_elem_value *ucontrol) 416 { 417 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 418 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 419 struct mt8188_afe_private *afe_priv = afe->platform_priv; 420 struct mtkaif_param *param = &afe_priv->mtkaif_params; 421 int dmic_on; 422 423 dmic_on = !!ucontrol->value.integer.value[0]; 424 425 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 426 __func__, kcontrol->id.name, dmic_on); 427 428 if (param->mtkaif_dmic_on == dmic_on) 429 return 0; 430 431 param->mtkaif_dmic_on = dmic_on; 432 return 1; 433 } 434 435 static const struct snd_kcontrol_new mtk_dai_adda_controls[] = { 436 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 437 DL_2_GAIN_CTL_PRE_SHIFT, 65535, 0), 438 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 439 mt8188_adda_dmic_get, mt8188_adda_dmic_set), 440 }; 441 442 static int mtk_dai_da_configure(struct mtk_base_afe *afe, 443 unsigned int rate, int id) 444 { 445 unsigned int val = 0; 446 unsigned int mask = 0; 447 448 /* set sampling rate */ 449 mask |= DL_2_INPUT_MODE_CTL_MASK; 450 val |= FIELD_PREP(DL_2_INPUT_MODE_CTL_MASK, 451 afe_adda_dl_rate_transform(afe, rate)); 452 453 /* turn off saturation */ 454 mask |= DL_2_CH1_SATURATION_EN_CTL; 455 mask |= DL_2_CH2_SATURATION_EN_CTL; 456 457 /* turn off mute function */ 458 mask |= DL_2_MUTE_CH1_OFF_CTL_PRE; 459 mask |= DL_2_MUTE_CH2_OFF_CTL_PRE; 460 val |= DL_2_MUTE_CH1_OFF_CTL_PRE; 461 val |= DL_2_MUTE_CH2_OFF_CTL_PRE; 462 463 /* set voice input data if input sample rate is 8k or 16k */ 464 mask |= DL_2_VOICE_MODE_CTL_PRE; 465 if (rate == 8000 || rate == 16000) 466 val |= DL_2_VOICE_MODE_CTL_PRE; 467 468 regmap_update_bits(afe->regmap, AFE_ADDA_DL_SRC2_CON0, mask, val); 469 470 /* new 2nd sdm */ 471 regmap_set_bits(afe->regmap, AFE_ADDA_DL_SDM_DCCOMP_CON, 472 DL_USE_NEW_2ND_SDM); 473 474 return 0; 475 } 476 477 static int mtk_dai_ad_configure(struct mtk_base_afe *afe, 478 unsigned int rate, int id) 479 { 480 unsigned int val; 481 unsigned int mask; 482 483 mask = UL_VOICE_MODE_CTL_MASK; 484 val = FIELD_PREP(UL_VOICE_MODE_CTL_MASK, 485 afe_adda_ul_rate_transform(afe, rate)); 486 487 regmap_update_bits(afe->regmap, AFE_ADDA_UL_SRC_CON0, 488 mask, val); 489 return 0; 490 } 491 492 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 493 struct snd_pcm_hw_params *params, 494 struct snd_soc_dai *dai) 495 { 496 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 497 struct mt8188_afe_private *afe_priv = afe->platform_priv; 498 struct mtk_dai_adda_priv *adda_priv = afe_priv->dai_priv[dai->id]; 499 unsigned int rate = params_rate(params); 500 int id = dai->id; 501 int ret = 0; 502 503 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %u\n", 504 __func__, id, substream->stream, rate); 505 506 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 507 adda_priv->dl_rate = rate; 508 ret = mtk_dai_da_configure(afe, rate, id); 509 } else { 510 adda_priv->ul_rate = rate; 511 ret = mtk_dai_ad_configure(afe, rate, id); 512 } 513 514 return ret; 515 } 516 517 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 518 .hw_params = mtk_dai_adda_hw_params, 519 }; 520 521 /* dai driver */ 522 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 523 SNDRV_PCM_RATE_96000 |\ 524 SNDRV_PCM_RATE_192000) 525 526 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 527 SNDRV_PCM_RATE_16000 |\ 528 SNDRV_PCM_RATE_32000 |\ 529 SNDRV_PCM_RATE_48000 |\ 530 SNDRV_PCM_RATE_96000 |\ 531 SNDRV_PCM_RATE_192000) 532 533 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 534 SNDRV_PCM_FMTBIT_S24_LE |\ 535 SNDRV_PCM_FMTBIT_S32_LE) 536 537 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 538 { 539 .name = "ADDA", 540 .id = MT8188_AFE_IO_ADDA, 541 .playback = { 542 .stream_name = "ADDA Playback", 543 .channels_min = 1, 544 .channels_max = 2, 545 .rates = MTK_ADDA_PLAYBACK_RATES, 546 .formats = MTK_ADDA_FORMATS, 547 }, 548 .capture = { 549 .stream_name = "ADDA Capture", 550 .channels_min = 1, 551 .channels_max = 2, 552 .rates = MTK_ADDA_CAPTURE_RATES, 553 .formats = MTK_ADDA_FORMATS, 554 }, 555 .ops = &mtk_dai_adda_ops, 556 }, 557 }; 558 559 static int init_adda_priv_data(struct mtk_base_afe *afe) 560 { 561 struct mt8188_afe_private *afe_priv = afe->platform_priv; 562 struct mtk_dai_adda_priv *adda_priv; 563 564 adda_priv = devm_kzalloc(afe->dev, sizeof(struct mtk_dai_adda_priv), 565 GFP_KERNEL); 566 if (!adda_priv) 567 return -ENOMEM; 568 569 afe_priv->dai_priv[MT8188_AFE_IO_ADDA] = adda_priv; 570 571 return 0; 572 } 573 574 int mt8188_dai_adda_register(struct mtk_base_afe *afe) 575 { 576 struct mtk_base_afe_dai *dai; 577 578 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 579 if (!dai) 580 return -ENOMEM; 581 582 list_add(&dai->list, &afe->sub_dais); 583 584 dai->dai_drivers = mtk_dai_adda_driver; 585 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 586 587 dai->dapm_widgets = mtk_dai_adda_widgets; 588 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 589 dai->dapm_routes = mtk_dai_adda_routes; 590 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 591 dai->controls = mtk_dai_adda_controls; 592 dai->num_controls = ARRAY_SIZE(mtk_dai_adda_controls); 593 594 return init_adda_priv_data(afe); 595 } 596