xref: /linux/sound/soc/mediatek/mt8188/mt8188-audsys-clkid.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1*fdd4e1a2STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */
2*fdd4e1a2STrevor Wu /*
3*fdd4e1a2STrevor Wu  * mt8188-audsys-clkid.h  --  MediaTek 8188 audsys clock id definition
4*fdd4e1a2STrevor Wu  *
5*fdd4e1a2STrevor Wu  * Copyright (c) 2022 MediaTek Inc.
6*fdd4e1a2STrevor Wu  * Author: Chun-Chia Chiu <chun-chia.chiu@mediatek.com>
7*fdd4e1a2STrevor Wu  */
8*fdd4e1a2STrevor Wu 
9*fdd4e1a2STrevor Wu #ifndef _MT8188_AUDSYS_CLKID_H_
10*fdd4e1a2STrevor Wu #define _MT8188_AUDSYS_CLKID_H_
11*fdd4e1a2STrevor Wu 
12*fdd4e1a2STrevor Wu enum{
13*fdd4e1a2STrevor Wu 	CLK_AUD_AFE,
14*fdd4e1a2STrevor Wu 	CLK_AUD_LRCK_CNT,
15*fdd4e1a2STrevor Wu 	CLK_AUD_SPDIFIN_TUNER_APLL,
16*fdd4e1a2STrevor Wu 	CLK_AUD_SPDIFIN_TUNER_DBG,
17*fdd4e1a2STrevor Wu 	CLK_AUD_UL_TML,
18*fdd4e1a2STrevor Wu 	CLK_AUD_APLL1_TUNER,
19*fdd4e1a2STrevor Wu 	CLK_AUD_APLL2_TUNER,
20*fdd4e1a2STrevor Wu 	CLK_AUD_TOP0_SPDF,
21*fdd4e1a2STrevor Wu 	CLK_AUD_APLL,
22*fdd4e1a2STrevor Wu 	CLK_AUD_APLL2,
23*fdd4e1a2STrevor Wu 	CLK_AUD_DAC,
24*fdd4e1a2STrevor Wu 	CLK_AUD_DAC_PREDIS,
25*fdd4e1a2STrevor Wu 	CLK_AUD_TML,
26*fdd4e1a2STrevor Wu 	CLK_AUD_ADC,
27*fdd4e1a2STrevor Wu 	CLK_AUD_DAC_HIRES,
28*fdd4e1a2STrevor Wu 	CLK_AUD_A1SYS_HP,
29*fdd4e1a2STrevor Wu 	CLK_AUD_AFE_DMIC1,
30*fdd4e1a2STrevor Wu 	CLK_AUD_AFE_DMIC2,
31*fdd4e1a2STrevor Wu 	CLK_AUD_AFE_DMIC3,
32*fdd4e1a2STrevor Wu 	CLK_AUD_AFE_DMIC4,
33*fdd4e1a2STrevor Wu 	CLK_AUD_AFE_26M_DMIC_TM,
34*fdd4e1a2STrevor Wu 	CLK_AUD_UL_TML_HIRES,
35*fdd4e1a2STrevor Wu 	CLK_AUD_ADC_HIRES,
36*fdd4e1a2STrevor Wu 	CLK_AUD_LINEIN_TUNER,
37*fdd4e1a2STrevor Wu 	CLK_AUD_EARC_TUNER,
38*fdd4e1a2STrevor Wu 	CLK_AUD_I2SIN,
39*fdd4e1a2STrevor Wu 	CLK_AUD_TDM_IN,
40*fdd4e1a2STrevor Wu 	CLK_AUD_I2S_OUT,
41*fdd4e1a2STrevor Wu 	CLK_AUD_TDM_OUT,
42*fdd4e1a2STrevor Wu 	CLK_AUD_HDMI_OUT,
43*fdd4e1a2STrevor Wu 	CLK_AUD_ASRC11,
44*fdd4e1a2STrevor Wu 	CLK_AUD_ASRC12,
45*fdd4e1a2STrevor Wu 	CLK_AUD_MULTI_IN,
46*fdd4e1a2STrevor Wu 	CLK_AUD_INTDIR,
47*fdd4e1a2STrevor Wu 	CLK_AUD_A1SYS,
48*fdd4e1a2STrevor Wu 	CLK_AUD_A2SYS,
49*fdd4e1a2STrevor Wu 	CLK_AUD_PCMIF,
50*fdd4e1a2STrevor Wu 	CLK_AUD_A3SYS,
51*fdd4e1a2STrevor Wu 	CLK_AUD_A4SYS,
52*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL1,
53*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL2,
54*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL3,
55*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL4,
56*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL5,
57*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL6,
58*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL8,
59*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL9,
60*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_UL10,
61*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL2,
62*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL3,
63*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL6,
64*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL7,
65*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL8,
66*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL10,
67*fdd4e1a2STrevor Wu 	CLK_AUD_MEMIF_DL11,
68*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC0,
69*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC1,
70*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC2,
71*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC3,
72*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC4,
73*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC5,
74*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC6,
75*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC7,
76*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC8,
77*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC9,
78*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC10,
79*fdd4e1a2STrevor Wu 	CLK_AUD_GASRC11,
80*fdd4e1a2STrevor Wu 	CLK_AUD_NR_CLK,
81*fdd4e1a2STrevor Wu };
82*fdd4e1a2STrevor Wu 
83*fdd4e1a2STrevor Wu #endif
84