1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #ifndef _MT8188_AFE_CLK_H_ 12 #define _MT8188_AFE_CLK_H_ 13 14 enum { 15 /* xtal */ 16 MT8188_CLK_XTAL_26M, 17 /* pll */ 18 MT8188_CLK_APMIXED_APLL1, 19 MT8188_CLK_APMIXED_APLL2, 20 /* divider */ 21 MT8188_CLK_TOP_APLL12_DIV0, 22 MT8188_CLK_TOP_APLL12_DIV1, 23 MT8188_CLK_TOP_APLL12_DIV2, 24 MT8188_CLK_TOP_APLL12_DIV3, 25 MT8188_CLK_TOP_APLL12_DIV9, 26 /* mux */ 27 MT8188_CLK_TOP_A1SYS_HP_SEL, 28 MT8188_CLK_TOP_AUD_INTBUS_SEL, 29 MT8188_CLK_TOP_AUDIO_H_SEL, 30 MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 31 MT8188_CLK_TOP_DPTX_M_SEL, 32 MT8188_CLK_TOP_I2SO1_M_SEL, 33 MT8188_CLK_TOP_I2SO2_M_SEL, 34 MT8188_CLK_TOP_I2SI1_M_SEL, 35 MT8188_CLK_TOP_I2SI2_M_SEL, 36 /* clock gate */ 37 MT8188_CLK_ADSP_AUDIO_26M, 38 MT8188_CLK_AUD_AFE, 39 MT8188_CLK_AUD_APLL1_TUNER, 40 MT8188_CLK_AUD_APLL2_TUNER, 41 MT8188_CLK_AUD_TOP0_SPDF, 42 MT8188_CLK_AUD_APLL, 43 MT8188_CLK_AUD_APLL2, 44 MT8188_CLK_AUD_DAC, 45 MT8188_CLK_AUD_ADC, 46 MT8188_CLK_AUD_DAC_HIRES, 47 MT8188_CLK_AUD_A1SYS_HP, 48 MT8188_CLK_AUD_ADC_HIRES, 49 MT8188_CLK_AUD_I2SIN, 50 MT8188_CLK_AUD_TDM_IN, 51 MT8188_CLK_AUD_I2S_OUT, 52 MT8188_CLK_AUD_TDM_OUT, 53 MT8188_CLK_AUD_HDMI_OUT, 54 MT8188_CLK_AUD_ASRC11, 55 MT8188_CLK_AUD_ASRC12, 56 MT8188_CLK_AUD_A1SYS, 57 MT8188_CLK_AUD_A2SYS, 58 MT8188_CLK_AUD_PCMIF, 59 MT8188_CLK_AUD_MEMIF_UL1, 60 MT8188_CLK_AUD_MEMIF_UL2, 61 MT8188_CLK_AUD_MEMIF_UL3, 62 MT8188_CLK_AUD_MEMIF_UL4, 63 MT8188_CLK_AUD_MEMIF_UL5, 64 MT8188_CLK_AUD_MEMIF_UL6, 65 MT8188_CLK_AUD_MEMIF_UL8, 66 MT8188_CLK_AUD_MEMIF_UL9, 67 MT8188_CLK_AUD_MEMIF_UL10, 68 MT8188_CLK_AUD_MEMIF_DL2, 69 MT8188_CLK_AUD_MEMIF_DL3, 70 MT8188_CLK_AUD_MEMIF_DL6, 71 MT8188_CLK_AUD_MEMIF_DL7, 72 MT8188_CLK_AUD_MEMIF_DL8, 73 MT8188_CLK_AUD_MEMIF_DL10, 74 MT8188_CLK_AUD_MEMIF_DL11, 75 MT8188_CLK_NUM, 76 }; 77 78 enum { 79 MT8188_AUD_PLL1, 80 MT8188_AUD_PLL2, 81 MT8188_AUD_PLL3, 82 MT8188_AUD_PLL4, 83 MT8188_AUD_PLL5, 84 MT8188_AUD_PLL_NUM, 85 }; 86 87 enum { 88 MT8188_MCK_SEL_26M, 89 MT8188_MCK_SEL_APLL1, 90 MT8188_MCK_SEL_APLL2, 91 MT8188_MCK_SEL_APLL3, 92 MT8188_MCK_SEL_APLL4, 93 MT8188_MCK_SEL_APLL5, 94 MT8188_MCK_SEL_NUM, 95 }; 96 97 struct mtk_base_afe; 98 99 int mt8188_afe_get_mclk_source_clk_id(int sel); 100 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 101 int mt8188_afe_get_default_mclk_source_by_rate(int rate); 102 int mt8188_afe_init_clock(struct mtk_base_afe *afe); 103 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 104 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 105 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 106 unsigned int rate); 107 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 108 struct clk *parent); 109 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 110 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 111 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 112 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 113 114 #endif 115