1*f6b02647STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2*f6b02647STrevor Wu /* 3*f6b02647STrevor Wu * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition 4*f6b02647STrevor Wu * 5*f6b02647STrevor Wu * Copyright (c) 2022 MediaTek Inc. 6*f6b02647STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7*f6b02647STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8*f6b02647STrevor Wu * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9*f6b02647STrevor Wu */ 10*f6b02647STrevor Wu 11*f6b02647STrevor Wu #ifndef _MT8188_AFE_CLK_H_ 12*f6b02647STrevor Wu #define _MT8188_AFE_CLK_H_ 13*f6b02647STrevor Wu 14*f6b02647STrevor Wu enum { 15*f6b02647STrevor Wu /* xtal */ 16*f6b02647STrevor Wu MT8188_CLK_XTAL_26M, 17*f6b02647STrevor Wu /* pll */ 18*f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL1, 19*f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL2, 20*f6b02647STrevor Wu /* divider */ 21*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV0, 22*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV1, 23*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV2, 24*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV3, 25*f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV9, 26*f6b02647STrevor Wu /* mux */ 27*f6b02647STrevor Wu MT8188_CLK_TOP_A1SYS_HP_SEL, 28*f6b02647STrevor Wu MT8188_CLK_TOP_AUD_INTBUS_SEL, 29*f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_H_SEL, 30*f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 31*f6b02647STrevor Wu MT8188_CLK_TOP_DPTX_M_SEL, 32*f6b02647STrevor Wu MT8188_CLK_TOP_I2SO1_M_SEL, 33*f6b02647STrevor Wu MT8188_CLK_TOP_I2SO2_M_SEL, 34*f6b02647STrevor Wu MT8188_CLK_TOP_I2SI1_M_SEL, 35*f6b02647STrevor Wu MT8188_CLK_TOP_I2SI2_M_SEL, 36*f6b02647STrevor Wu /* clock gate */ 37*f6b02647STrevor Wu MT8188_CLK_ADSP_AUDIO_26M, 38*f6b02647STrevor Wu MT8188_CLK_AUD_AFE, 39*f6b02647STrevor Wu MT8188_CLK_AUD_APLL1_TUNER, 40*f6b02647STrevor Wu MT8188_CLK_AUD_APLL2_TUNER, 41*f6b02647STrevor Wu MT8188_CLK_AUD_TOP0_SPDF, 42*f6b02647STrevor Wu MT8188_CLK_AUD_APLL, 43*f6b02647STrevor Wu MT8188_CLK_AUD_APLL2, 44*f6b02647STrevor Wu MT8188_CLK_AUD_DAC, 45*f6b02647STrevor Wu MT8188_CLK_AUD_ADC, 46*f6b02647STrevor Wu MT8188_CLK_AUD_DAC_HIRES, 47*f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS_HP, 48*f6b02647STrevor Wu MT8188_CLK_AUD_ADC_HIRES, 49*f6b02647STrevor Wu MT8188_CLK_AUD_I2SIN, 50*f6b02647STrevor Wu MT8188_CLK_AUD_TDM_IN, 51*f6b02647STrevor Wu MT8188_CLK_AUD_I2S_OUT, 52*f6b02647STrevor Wu MT8188_CLK_AUD_TDM_OUT, 53*f6b02647STrevor Wu MT8188_CLK_AUD_HDMI_OUT, 54*f6b02647STrevor Wu MT8188_CLK_AUD_ASRC11, 55*f6b02647STrevor Wu MT8188_CLK_AUD_ASRC12, 56*f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS, 57*f6b02647STrevor Wu MT8188_CLK_AUD_A2SYS, 58*f6b02647STrevor Wu MT8188_CLK_AUD_PCMIF, 59*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL1, 60*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL2, 61*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL3, 62*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL4, 63*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL5, 64*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL6, 65*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL8, 66*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL9, 67*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL10, 68*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL2, 69*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL3, 70*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL6, 71*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL7, 72*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL8, 73*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL10, 74*f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL11, 75*f6b02647STrevor Wu MT8188_CLK_NUM, 76*f6b02647STrevor Wu }; 77*f6b02647STrevor Wu 78*f6b02647STrevor Wu enum { 79*f6b02647STrevor Wu MT8188_AUD_PLL1, 80*f6b02647STrevor Wu MT8188_AUD_PLL2, 81*f6b02647STrevor Wu MT8188_AUD_PLL3, 82*f6b02647STrevor Wu MT8188_AUD_PLL4, 83*f6b02647STrevor Wu MT8188_AUD_PLL5, 84*f6b02647STrevor Wu MT8188_AUD_PLL_NUM, 85*f6b02647STrevor Wu }; 86*f6b02647STrevor Wu 87*f6b02647STrevor Wu enum { 88*f6b02647STrevor Wu MT8188_MCK_SEL_26M, 89*f6b02647STrevor Wu MT8188_MCK_SEL_APLL1, 90*f6b02647STrevor Wu MT8188_MCK_SEL_APLL2, 91*f6b02647STrevor Wu MT8188_MCK_SEL_APLL3, 92*f6b02647STrevor Wu MT8188_MCK_SEL_APLL4, 93*f6b02647STrevor Wu MT8188_MCK_SEL_APLL5, 94*f6b02647STrevor Wu MT8188_MCK_SEL_NUM, 95*f6b02647STrevor Wu }; 96*f6b02647STrevor Wu 97*f6b02647STrevor Wu struct mtk_base_afe; 98*f6b02647STrevor Wu 99*f6b02647STrevor Wu int mt8188_afe_get_mclk_source_clk_id(int sel); 100*f6b02647STrevor Wu int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 101*f6b02647STrevor Wu int mt8188_afe_get_default_mclk_source_by_rate(int rate); 102*f6b02647STrevor Wu int mt8188_afe_init_clock(struct mtk_base_afe *afe); 103*f6b02647STrevor Wu void mt8188_afe_deinit_clock(void *priv); 104*f6b02647STrevor Wu int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 105*f6b02647STrevor Wu void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 106*f6b02647STrevor Wu int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 107*f6b02647STrevor Wu unsigned int rate); 108*f6b02647STrevor Wu int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 109*f6b02647STrevor Wu struct clk *parent); 110*f6b02647STrevor Wu int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 111*f6b02647STrevor Wu int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 112*f6b02647STrevor Wu int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 113*f6b02647STrevor Wu int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 114*f6b02647STrevor Wu 115*f6b02647STrevor Wu #endif 116