1f6b02647STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 2f6b02647STrevor Wu /* 3f6b02647STrevor Wu * mt8188-afe-clk.h -- MediaTek 8188 afe clock ctrl definition 4f6b02647STrevor Wu * 5f6b02647STrevor Wu * Copyright (c) 2022 MediaTek Inc. 6f6b02647STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7f6b02647STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 8f6b02647STrevor Wu * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9f6b02647STrevor Wu */ 10f6b02647STrevor Wu 11f6b02647STrevor Wu #ifndef _MT8188_AFE_CLK_H_ 12f6b02647STrevor Wu #define _MT8188_AFE_CLK_H_ 13f6b02647STrevor Wu 149be0213aSTrevor Wu /* APLL */ 159be0213aSTrevor Wu #define APLL1_W_NAME "APLL1" 169be0213aSTrevor Wu #define APLL2_W_NAME "APLL2" 179be0213aSTrevor Wu 18f6b02647STrevor Wu enum { 19f6b02647STrevor Wu /* xtal */ 20f6b02647STrevor Wu MT8188_CLK_XTAL_26M, 21f6b02647STrevor Wu /* pll */ 22f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL1, 23f6b02647STrevor Wu MT8188_CLK_APMIXED_APLL2, 24f6b02647STrevor Wu /* divider */ 259be0213aSTrevor Wu MT8188_CLK_TOP_APLL1_D4, 26*2e5c422aSTrevor Wu MT8188_CLK_TOP_APLL2_D4, 27f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV0, 28f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV1, 29f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV2, 30f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV3, 31*2e5c422aSTrevor Wu MT8188_CLK_TOP_APLL12_DIV4, 32f6b02647STrevor Wu MT8188_CLK_TOP_APLL12_DIV9, 33f6b02647STrevor Wu /* mux */ 34f6b02647STrevor Wu MT8188_CLK_TOP_A1SYS_HP_SEL, 35*2e5c422aSTrevor Wu MT8188_CLK_TOP_A2SYS_SEL, 36*2e5c422aSTrevor Wu MT8188_CLK_TOP_AUD_IEC_SEL, 37f6b02647STrevor Wu MT8188_CLK_TOP_AUD_INTBUS_SEL, 38f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_H_SEL, 39f6b02647STrevor Wu MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 40f6b02647STrevor Wu MT8188_CLK_TOP_DPTX_M_SEL, 41f6b02647STrevor Wu MT8188_CLK_TOP_I2SO1_M_SEL, 42f6b02647STrevor Wu MT8188_CLK_TOP_I2SO2_M_SEL, 43f6b02647STrevor Wu MT8188_CLK_TOP_I2SI1_M_SEL, 44f6b02647STrevor Wu MT8188_CLK_TOP_I2SI2_M_SEL, 45f6b02647STrevor Wu /* clock gate */ 46f6b02647STrevor Wu MT8188_CLK_ADSP_AUDIO_26M, 47f6b02647STrevor Wu MT8188_CLK_AUD_AFE, 48f6b02647STrevor Wu MT8188_CLK_AUD_APLL1_TUNER, 49f6b02647STrevor Wu MT8188_CLK_AUD_APLL2_TUNER, 50f6b02647STrevor Wu MT8188_CLK_AUD_TOP0_SPDF, 51f6b02647STrevor Wu MT8188_CLK_AUD_APLL, 52f6b02647STrevor Wu MT8188_CLK_AUD_APLL2, 53f6b02647STrevor Wu MT8188_CLK_AUD_DAC, 54f6b02647STrevor Wu MT8188_CLK_AUD_ADC, 55f6b02647STrevor Wu MT8188_CLK_AUD_DAC_HIRES, 56f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS_HP, 57f6b02647STrevor Wu MT8188_CLK_AUD_ADC_HIRES, 58f6b02647STrevor Wu MT8188_CLK_AUD_I2SIN, 59f6b02647STrevor Wu MT8188_CLK_AUD_TDM_IN, 60f6b02647STrevor Wu MT8188_CLK_AUD_I2S_OUT, 61f6b02647STrevor Wu MT8188_CLK_AUD_TDM_OUT, 62f6b02647STrevor Wu MT8188_CLK_AUD_HDMI_OUT, 63f6b02647STrevor Wu MT8188_CLK_AUD_ASRC11, 64f6b02647STrevor Wu MT8188_CLK_AUD_ASRC12, 65f6b02647STrevor Wu MT8188_CLK_AUD_A1SYS, 66f6b02647STrevor Wu MT8188_CLK_AUD_A2SYS, 67f6b02647STrevor Wu MT8188_CLK_AUD_PCMIF, 68f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL1, 69f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL2, 70f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL3, 71f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL4, 72f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL5, 73f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL6, 74f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL8, 75f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL9, 76f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_UL10, 77f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL2, 78f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL3, 79f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL6, 80f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL7, 81f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL8, 82f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL10, 83f6b02647STrevor Wu MT8188_CLK_AUD_MEMIF_DL11, 84f6b02647STrevor Wu MT8188_CLK_NUM, 85f6b02647STrevor Wu }; 86f6b02647STrevor Wu 87f6b02647STrevor Wu enum { 88f6b02647STrevor Wu MT8188_AUD_PLL1, 89f6b02647STrevor Wu MT8188_AUD_PLL2, 90f6b02647STrevor Wu MT8188_AUD_PLL3, 91f6b02647STrevor Wu MT8188_AUD_PLL4, 92f6b02647STrevor Wu MT8188_AUD_PLL5, 93f6b02647STrevor Wu MT8188_AUD_PLL_NUM, 94f6b02647STrevor Wu }; 95f6b02647STrevor Wu 96f6b02647STrevor Wu enum { 97f6b02647STrevor Wu MT8188_MCK_SEL_26M, 98f6b02647STrevor Wu MT8188_MCK_SEL_APLL1, 99f6b02647STrevor Wu MT8188_MCK_SEL_APLL2, 100f6b02647STrevor Wu MT8188_MCK_SEL_APLL3, 101f6b02647STrevor Wu MT8188_MCK_SEL_APLL4, 102f6b02647STrevor Wu MT8188_MCK_SEL_APLL5, 103f6b02647STrevor Wu MT8188_MCK_SEL_NUM, 104f6b02647STrevor Wu }; 105f6b02647STrevor Wu 106f6b02647STrevor Wu struct mtk_base_afe; 107f6b02647STrevor Wu 108f6b02647STrevor Wu int mt8188_afe_get_mclk_source_clk_id(int sel); 109f6b02647STrevor Wu int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 110f6b02647STrevor Wu int mt8188_afe_get_default_mclk_source_by_rate(int rate); 1119be0213aSTrevor Wu int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate); 1129be0213aSTrevor Wu int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name); 113f6b02647STrevor Wu int mt8188_afe_init_clock(struct mtk_base_afe *afe); 114f6b02647STrevor Wu void mt8188_afe_deinit_clock(void *priv); 115f6b02647STrevor Wu int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 116f6b02647STrevor Wu void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 117f6b02647STrevor Wu int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 118f6b02647STrevor Wu unsigned int rate); 119f6b02647STrevor Wu int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 120f6b02647STrevor Wu struct clk *parent); 1219be0213aSTrevor Wu int mt8188_apll1_enable(struct mtk_base_afe *afe); 1229be0213aSTrevor Wu int mt8188_apll1_disable(struct mtk_base_afe *afe); 1239be0213aSTrevor Wu int mt8188_apll2_enable(struct mtk_base_afe *afe); 1249be0213aSTrevor Wu int mt8188_apll2_disable(struct mtk_base_afe *afe); 125f6b02647STrevor Wu int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe); 126f6b02647STrevor Wu int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe); 127f6b02647STrevor Wu int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 128f6b02647STrevor Wu int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 129f6b02647STrevor Wu 130f6b02647STrevor Wu #endif 131