1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mt8188-afe-clk.c -- MediaTek 8188 afe clock ctrl 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #include <linux/clk.h> 12 13 #include "mt8188-afe-common.h" 14 #include "mt8188-afe-clk.h" 15 #include "mt8188-audsys-clk.h" 16 #include "mt8188-reg.h" 17 18 static const char *aud_clks[MT8188_CLK_NUM] = { 19 /* xtal */ 20 [MT8188_CLK_XTAL_26M] = "clk26m", 21 22 /* pll */ 23 [MT8188_CLK_APMIXED_APLL1] = "apll1", 24 [MT8188_CLK_APMIXED_APLL2] = "apll2", 25 26 /* divider */ 27 [MT8188_CLK_TOP_APLL1_D4] = "apll1_d4", 28 [MT8188_CLK_TOP_APLL12_DIV0] = "apll12_div0", 29 [MT8188_CLK_TOP_APLL12_DIV1] = "apll12_div1", 30 [MT8188_CLK_TOP_APLL12_DIV2] = "apll12_div2", 31 [MT8188_CLK_TOP_APLL12_DIV3] = "apll12_div3", 32 [MT8188_CLK_TOP_APLL12_DIV9] = "apll12_div9", 33 34 /* mux */ 35 [MT8188_CLK_TOP_A1SYS_HP_SEL] = "top_a1sys_hp", 36 [MT8188_CLK_TOP_AUD_INTBUS_SEL] = "top_aud_intbus", 37 [MT8188_CLK_TOP_AUDIO_H_SEL] = "top_audio_h", 38 [MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL] = "top_audio_local_bus", 39 [MT8188_CLK_TOP_DPTX_M_SEL] = "top_dptx", 40 [MT8188_CLK_TOP_I2SO1_M_SEL] = "top_i2so1", 41 [MT8188_CLK_TOP_I2SO2_M_SEL] = "top_i2so2", 42 [MT8188_CLK_TOP_I2SI1_M_SEL] = "top_i2si1", 43 [MT8188_CLK_TOP_I2SI2_M_SEL] = "top_i2si2", 44 45 /* clock gate */ 46 [MT8188_CLK_ADSP_AUDIO_26M] = "adsp_audio_26m", 47 /* afe clock gate */ 48 [MT8188_CLK_AUD_AFE] = "aud_afe", 49 [MT8188_CLK_AUD_APLL1_TUNER] = "aud_apll1_tuner", 50 [MT8188_CLK_AUD_APLL2_TUNER] = "aud_apll2_tuner", 51 [MT8188_CLK_AUD_APLL] = "aud_apll", 52 [MT8188_CLK_AUD_APLL2] = "aud_apll2", 53 [MT8188_CLK_AUD_DAC] = "aud_dac", 54 [MT8188_CLK_AUD_ADC] = "aud_adc", 55 [MT8188_CLK_AUD_DAC_HIRES] = "aud_dac_hires", 56 [MT8188_CLK_AUD_A1SYS_HP] = "aud_a1sys_hp", 57 [MT8188_CLK_AUD_ADC_HIRES] = "aud_adc_hires", 58 [MT8188_CLK_AUD_I2SIN] = "aud_i2sin", 59 [MT8188_CLK_AUD_TDM_IN] = "aud_tdm_in", 60 [MT8188_CLK_AUD_I2S_OUT] = "aud_i2s_out", 61 [MT8188_CLK_AUD_TDM_OUT] = "aud_tdm_out", 62 [MT8188_CLK_AUD_HDMI_OUT] = "aud_hdmi_out", 63 [MT8188_CLK_AUD_ASRC11] = "aud_asrc11", 64 [MT8188_CLK_AUD_ASRC12] = "aud_asrc12", 65 [MT8188_CLK_AUD_A1SYS] = "aud_a1sys", 66 [MT8188_CLK_AUD_A2SYS] = "aud_a2sys", 67 [MT8188_CLK_AUD_PCMIF] = "aud_pcmif", 68 [MT8188_CLK_AUD_MEMIF_UL1] = "aud_memif_ul1", 69 [MT8188_CLK_AUD_MEMIF_UL2] = "aud_memif_ul2", 70 [MT8188_CLK_AUD_MEMIF_UL3] = "aud_memif_ul3", 71 [MT8188_CLK_AUD_MEMIF_UL4] = "aud_memif_ul4", 72 [MT8188_CLK_AUD_MEMIF_UL5] = "aud_memif_ul5", 73 [MT8188_CLK_AUD_MEMIF_UL6] = "aud_memif_ul6", 74 [MT8188_CLK_AUD_MEMIF_UL8] = "aud_memif_ul8", 75 [MT8188_CLK_AUD_MEMIF_UL9] = "aud_memif_ul9", 76 [MT8188_CLK_AUD_MEMIF_UL10] = "aud_memif_ul10", 77 [MT8188_CLK_AUD_MEMIF_DL2] = "aud_memif_dl2", 78 [MT8188_CLK_AUD_MEMIF_DL3] = "aud_memif_dl3", 79 [MT8188_CLK_AUD_MEMIF_DL6] = "aud_memif_dl6", 80 [MT8188_CLK_AUD_MEMIF_DL7] = "aud_memif_dl7", 81 [MT8188_CLK_AUD_MEMIF_DL8] = "aud_memif_dl8", 82 [MT8188_CLK_AUD_MEMIF_DL10] = "aud_memif_dl10", 83 [MT8188_CLK_AUD_MEMIF_DL11] = "aud_memif_dl11", 84 }; 85 86 struct mt8188_afe_tuner_cfg { 87 unsigned int id; 88 int apll_div_reg; 89 unsigned int apll_div_shift; 90 unsigned int apll_div_maskbit; 91 unsigned int apll_div_default; 92 int ref_ck_sel_reg; 93 unsigned int ref_ck_sel_shift; 94 unsigned int ref_ck_sel_maskbit; 95 unsigned int ref_ck_sel_default; 96 int tuner_en_reg; 97 unsigned int tuner_en_shift; 98 unsigned int tuner_en_maskbit; 99 int upper_bound_reg; 100 unsigned int upper_bound_shift; 101 unsigned int upper_bound_maskbit; 102 unsigned int upper_bound_default; 103 spinlock_t ctrl_lock; /* lock for apll tuner ctrl*/ 104 int ref_cnt; 105 }; 106 107 static struct mt8188_afe_tuner_cfg 108 mt8188_afe_tuner_cfgs[MT8188_AUD_PLL_NUM] = { 109 [MT8188_AUD_PLL1] = { 110 .id = MT8188_AUD_PLL1, 111 .apll_div_reg = AFE_APLL_TUNER_CFG, 112 .apll_div_shift = 4, 113 .apll_div_maskbit = 0xf, 114 .apll_div_default = 0x7, 115 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG, 116 .ref_ck_sel_shift = 1, 117 .ref_ck_sel_maskbit = 0x3, 118 .ref_ck_sel_default = 0x2, 119 .tuner_en_reg = AFE_APLL_TUNER_CFG, 120 .tuner_en_shift = 0, 121 .tuner_en_maskbit = 0x1, 122 .upper_bound_reg = AFE_APLL_TUNER_CFG, 123 .upper_bound_shift = 8, 124 .upper_bound_maskbit = 0xff, 125 .upper_bound_default = 0x3, 126 }, 127 [MT8188_AUD_PLL2] = { 128 .id = MT8188_AUD_PLL2, 129 .apll_div_reg = AFE_APLL_TUNER_CFG1, 130 .apll_div_shift = 4, 131 .apll_div_maskbit = 0xf, 132 .apll_div_default = 0x7, 133 .ref_ck_sel_reg = AFE_APLL_TUNER_CFG1, 134 .ref_ck_sel_shift = 1, 135 .ref_ck_sel_maskbit = 0x3, 136 .ref_ck_sel_default = 0x1, 137 .tuner_en_reg = AFE_APLL_TUNER_CFG1, 138 .tuner_en_shift = 0, 139 .tuner_en_maskbit = 0x1, 140 .upper_bound_reg = AFE_APLL_TUNER_CFG1, 141 .upper_bound_shift = 8, 142 .upper_bound_maskbit = 0xff, 143 .upper_bound_default = 0x3, 144 }, 145 [MT8188_AUD_PLL3] = { 146 .id = MT8188_AUD_PLL3, 147 .apll_div_reg = AFE_EARC_APLL_TUNER_CFG, 148 .apll_div_shift = 4, 149 .apll_div_maskbit = 0x3f, 150 .apll_div_default = 0x3, 151 .ref_ck_sel_reg = AFE_EARC_APLL_TUNER_CFG, 152 .ref_ck_sel_shift = 24, 153 .ref_ck_sel_maskbit = 0x3, 154 .ref_ck_sel_default = 0x0, 155 .tuner_en_reg = AFE_EARC_APLL_TUNER_CFG, 156 .tuner_en_shift = 0, 157 .tuner_en_maskbit = 0x1, 158 .upper_bound_reg = AFE_EARC_APLL_TUNER_CFG, 159 .upper_bound_shift = 12, 160 .upper_bound_maskbit = 0xff, 161 .upper_bound_default = 0x4, 162 }, 163 [MT8188_AUD_PLL4] = { 164 .id = MT8188_AUD_PLL4, 165 .apll_div_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 166 .apll_div_shift = 4, 167 .apll_div_maskbit = 0x3f, 168 .apll_div_default = 0x7, 169 .ref_ck_sel_reg = AFE_SPDIFIN_APLL_TUNER_CFG1, 170 .ref_ck_sel_shift = 8, 171 .ref_ck_sel_maskbit = 0x1, 172 .ref_ck_sel_default = 0, 173 .tuner_en_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 174 .tuner_en_shift = 0, 175 .tuner_en_maskbit = 0x1, 176 .upper_bound_reg = AFE_SPDIFIN_APLL_TUNER_CFG, 177 .upper_bound_shift = 12, 178 .upper_bound_maskbit = 0xff, 179 .upper_bound_default = 0x4, 180 }, 181 [MT8188_AUD_PLL5] = { 182 .id = MT8188_AUD_PLL5, 183 .apll_div_reg = AFE_LINEIN_APLL_TUNER_CFG, 184 .apll_div_shift = 4, 185 .apll_div_maskbit = 0x3f, 186 .apll_div_default = 0x3, 187 .ref_ck_sel_reg = AFE_LINEIN_APLL_TUNER_CFG, 188 .ref_ck_sel_shift = 24, 189 .ref_ck_sel_maskbit = 0x1, 190 .ref_ck_sel_default = 0, 191 .tuner_en_reg = AFE_LINEIN_APLL_TUNER_CFG, 192 .tuner_en_shift = 0, 193 .tuner_en_maskbit = 0x1, 194 .upper_bound_reg = AFE_LINEIN_APLL_TUNER_CFG, 195 .upper_bound_shift = 12, 196 .upper_bound_maskbit = 0xff, 197 .upper_bound_default = 0x4, 198 }, 199 }; 200 201 static struct mt8188_afe_tuner_cfg *mt8188_afe_found_apll_tuner(unsigned int id) 202 { 203 if (id >= MT8188_AUD_PLL_NUM) 204 return NULL; 205 206 return &mt8188_afe_tuner_cfgs[id]; 207 } 208 209 static int mt8188_afe_init_apll_tuner(unsigned int id) 210 { 211 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 212 213 if (!cfg) 214 return -EINVAL; 215 216 cfg->ref_cnt = 0; 217 spin_lock_init(&cfg->ctrl_lock); 218 219 return 0; 220 } 221 222 static int mt8188_afe_setup_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 223 { 224 const struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 225 226 if (!cfg) 227 return -EINVAL; 228 229 regmap_update_bits(afe->regmap, 230 cfg->apll_div_reg, 231 cfg->apll_div_maskbit << cfg->apll_div_shift, 232 cfg->apll_div_default << cfg->apll_div_shift); 233 234 regmap_update_bits(afe->regmap, 235 cfg->ref_ck_sel_reg, 236 cfg->ref_ck_sel_maskbit << cfg->ref_ck_sel_shift, 237 cfg->ref_ck_sel_default << cfg->ref_ck_sel_shift); 238 239 regmap_update_bits(afe->regmap, 240 cfg->upper_bound_reg, 241 cfg->upper_bound_maskbit << cfg->upper_bound_shift, 242 cfg->upper_bound_default << cfg->upper_bound_shift); 243 244 return 0; 245 } 246 247 static int mt8188_afe_enable_tuner_clk(struct mtk_base_afe *afe, 248 unsigned int id) 249 { 250 struct mt8188_afe_private *afe_priv = afe->platform_priv; 251 252 switch (id) { 253 case MT8188_AUD_PLL1: 254 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]); 255 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]); 256 break; 257 case MT8188_AUD_PLL2: 258 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]); 259 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]); 260 break; 261 default: 262 return -EINVAL; 263 } 264 265 return 0; 266 } 267 268 static int mt8188_afe_disable_tuner_clk(struct mtk_base_afe *afe, 269 unsigned int id) 270 { 271 struct mt8188_afe_private *afe_priv = afe->platform_priv; 272 273 switch (id) { 274 case MT8188_AUD_PLL1: 275 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL1_TUNER]); 276 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL]); 277 break; 278 case MT8188_AUD_PLL2: 279 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2_TUNER]); 280 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_APLL2]); 281 break; 282 default: 283 return -EINVAL; 284 } 285 286 return 0; 287 } 288 289 static int mt8188_afe_enable_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 290 { 291 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 292 unsigned long flags; 293 int ret; 294 295 if (!cfg) 296 return -EINVAL; 297 298 ret = mt8188_afe_setup_apll_tuner(afe, id); 299 if (ret) 300 return ret; 301 302 ret = mt8188_afe_enable_tuner_clk(afe, id); 303 if (ret) 304 return ret; 305 306 spin_lock_irqsave(&cfg->ctrl_lock, flags); 307 308 cfg->ref_cnt++; 309 if (cfg->ref_cnt == 1) 310 regmap_update_bits(afe->regmap, 311 cfg->tuner_en_reg, 312 cfg->tuner_en_maskbit << cfg->tuner_en_shift, 313 BIT(cfg->tuner_en_shift)); 314 315 spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 316 317 return 0; 318 } 319 320 static int mt8188_afe_disable_apll_tuner(struct mtk_base_afe *afe, unsigned int id) 321 { 322 struct mt8188_afe_tuner_cfg *cfg = mt8188_afe_found_apll_tuner(id); 323 unsigned long flags; 324 int ret; 325 326 if (!cfg) 327 return -EINVAL; 328 329 spin_lock_irqsave(&cfg->ctrl_lock, flags); 330 331 cfg->ref_cnt--; 332 if (cfg->ref_cnt == 0) 333 regmap_update_bits(afe->regmap, 334 cfg->tuner_en_reg, 335 cfg->tuner_en_maskbit << cfg->tuner_en_shift, 336 0 << cfg->tuner_en_shift); 337 else if (cfg->ref_cnt < 0) 338 cfg->ref_cnt = 0; 339 340 spin_unlock_irqrestore(&cfg->ctrl_lock, flags); 341 342 ret = mt8188_afe_disable_tuner_clk(afe, id); 343 if (ret) 344 return ret; 345 346 return 0; 347 } 348 349 int mt8188_afe_get_mclk_source_clk_id(int sel) 350 { 351 switch (sel) { 352 case MT8188_MCK_SEL_26M: 353 return MT8188_CLK_XTAL_26M; 354 case MT8188_MCK_SEL_APLL1: 355 return MT8188_CLK_APMIXED_APLL1; 356 case MT8188_MCK_SEL_APLL2: 357 return MT8188_CLK_APMIXED_APLL2; 358 default: 359 return -EINVAL; 360 } 361 } 362 363 int mt8188_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll) 364 { 365 struct mt8188_afe_private *afe_priv = afe->platform_priv; 366 int clk_id = mt8188_afe_get_mclk_source_clk_id(apll); 367 368 if (clk_id < 0) { 369 dev_dbg(afe->dev, "invalid clk id\n"); 370 return 0; 371 } 372 373 return clk_get_rate(afe_priv->clk[clk_id]); 374 } 375 376 int mt8188_afe_get_default_mclk_source_by_rate(int rate) 377 { 378 return ((rate % 8000) == 0) ? 379 MT8188_MCK_SEL_APLL1 : MT8188_MCK_SEL_APLL2; 380 } 381 382 int mt8188_get_apll_by_rate(struct mtk_base_afe *afe, int rate) 383 { 384 return ((rate % 8000) == 0) ? MT8188_AUD_PLL1 : MT8188_AUD_PLL2; 385 } 386 387 int mt8188_get_apll_by_name(struct mtk_base_afe *afe, const char *name) 388 { 389 if (strcmp(name, APLL1_W_NAME) == 0) 390 return MT8188_AUD_PLL1; 391 392 return MT8188_AUD_PLL2; 393 } 394 395 int mt8188_afe_init_clock(struct mtk_base_afe *afe) 396 { 397 struct mt8188_afe_private *afe_priv = afe->platform_priv; 398 int i, ret; 399 400 ret = mt8188_audsys_clk_register(afe); 401 if (ret) { 402 dev_err(afe->dev, "register audsys clk fail %d\n", ret); 403 return ret; 404 } 405 406 afe_priv->clk = 407 devm_kcalloc(afe->dev, MT8188_CLK_NUM, sizeof(*afe_priv->clk), 408 GFP_KERNEL); 409 if (!afe_priv->clk) 410 return -ENOMEM; 411 412 for (i = 0; i < MT8188_CLK_NUM; i++) { 413 afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]); 414 if (IS_ERR(afe_priv->clk[i])) { 415 dev_err(afe->dev, "%s(), devm_clk_get %s fail, ret %ld\n", 416 __func__, aud_clks[i], 417 PTR_ERR(afe_priv->clk[i])); 418 return PTR_ERR(afe_priv->clk[i]); 419 } 420 } 421 422 /* initial tuner */ 423 for (i = 0; i < MT8188_AUD_PLL_NUM; i++) { 424 ret = mt8188_afe_init_apll_tuner(i); 425 if (ret) { 426 dev_info(afe->dev, "%s(), init apll_tuner%d failed", 427 __func__, (i + 1)); 428 return -EINVAL; 429 } 430 } 431 432 return 0; 433 } 434 435 void mt8188_afe_deinit_clock(void *priv) 436 { 437 struct mtk_base_afe *afe = priv; 438 439 mt8188_audsys_clk_unregister(afe); 440 } 441 442 int mt8188_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk) 443 { 444 int ret; 445 446 if (clk) { 447 ret = clk_prepare_enable(clk); 448 if (ret) { 449 dev_dbg(afe->dev, "%s(), failed to enable clk\n", 450 __func__); 451 return ret; 452 } 453 } else { 454 dev_dbg(afe->dev, "NULL clk\n"); 455 } 456 return 0; 457 } 458 EXPORT_SYMBOL_GPL(mt8188_afe_enable_clk); 459 460 void mt8188_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk) 461 { 462 if (clk) 463 clk_disable_unprepare(clk); 464 else 465 dev_dbg(afe->dev, "NULL clk\n"); 466 } 467 EXPORT_SYMBOL_GPL(mt8188_afe_disable_clk); 468 469 int mt8188_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 470 unsigned int rate) 471 { 472 int ret; 473 474 if (clk) { 475 ret = clk_set_rate(clk, rate); 476 if (ret) { 477 dev_dbg(afe->dev, "%s(), failed to set clk rate\n", 478 __func__); 479 return ret; 480 } 481 } 482 483 return 0; 484 } 485 486 int mt8188_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 487 struct clk *parent) 488 { 489 int ret; 490 491 if (clk && parent) { 492 ret = clk_set_parent(clk, parent); 493 if (ret) { 494 dev_dbg(afe->dev, "%s(), failed to set clk parent %d\n", 495 __func__, ret); 496 return ret; 497 } 498 } 499 500 return 0; 501 } 502 503 static unsigned int get_top_cg_reg(unsigned int cg_type) 504 { 505 switch (cg_type) { 506 case MT8188_TOP_CG_A1SYS_TIMING: 507 case MT8188_TOP_CG_A2SYS_TIMING: 508 case MT8188_TOP_CG_26M_TIMING: 509 return ASYS_TOP_CON; 510 default: 511 return 0; 512 } 513 } 514 515 static unsigned int get_top_cg_mask(unsigned int cg_type) 516 { 517 switch (cg_type) { 518 case MT8188_TOP_CG_A1SYS_TIMING: 519 return ASYS_TOP_CON_A1SYS_TIMING_ON; 520 case MT8188_TOP_CG_A2SYS_TIMING: 521 return ASYS_TOP_CON_A2SYS_TIMING_ON; 522 case MT8188_TOP_CG_26M_TIMING: 523 return ASYS_TOP_CON_26M_TIMING_ON; 524 default: 525 return 0; 526 } 527 } 528 529 static unsigned int get_top_cg_on_val(unsigned int cg_type) 530 { 531 switch (cg_type) { 532 case MT8188_TOP_CG_A1SYS_TIMING: 533 case MT8188_TOP_CG_A2SYS_TIMING: 534 case MT8188_TOP_CG_26M_TIMING: 535 return get_top_cg_mask(cg_type); 536 default: 537 return 0; 538 } 539 } 540 541 static unsigned int get_top_cg_off_val(unsigned int cg_type) 542 { 543 switch (cg_type) { 544 case MT8188_TOP_CG_A1SYS_TIMING: 545 case MT8188_TOP_CG_A2SYS_TIMING: 546 case MT8188_TOP_CG_26M_TIMING: 547 return 0; 548 default: 549 return get_top_cg_mask(cg_type); 550 } 551 } 552 553 static int mt8188_afe_enable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 554 { 555 unsigned int reg = get_top_cg_reg(cg_type); 556 unsigned int mask = get_top_cg_mask(cg_type); 557 unsigned int val = get_top_cg_on_val(cg_type); 558 559 regmap_update_bits(afe->regmap, reg, mask, val); 560 561 return 0; 562 } 563 564 static int mt8188_afe_disable_top_cg(struct mtk_base_afe *afe, unsigned int cg_type) 565 { 566 unsigned int reg = get_top_cg_reg(cg_type); 567 unsigned int mask = get_top_cg_mask(cg_type); 568 unsigned int val = get_top_cg_off_val(cg_type); 569 570 regmap_update_bits(afe->regmap, reg, mask, val); 571 572 return 0; 573 } 574 575 int mt8188_afe_enable_reg_rw_clk(struct mtk_base_afe *afe) 576 { 577 struct mt8188_afe_private *afe_priv = afe->platform_priv; 578 579 /* bus clock for AFE external access, like DRAM */ 580 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]); 581 582 /* bus clock for AFE internal access, like AFE SRAM */ 583 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]); 584 585 /* audio 26m clock source */ 586 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]); 587 588 /* AFE hw clock */ 589 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]); 590 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); 591 mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 592 593 return 0; 594 } 595 596 int mt8188_afe_disable_reg_rw_clk(struct mtk_base_afe *afe) 597 { 598 struct mt8188_afe_private *afe_priv = afe->platform_priv; 599 600 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 601 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS_HP]); 602 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_AFE]); 603 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_ADSP_AUDIO_26M]); 604 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUD_INTBUS_SEL]); 605 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_AUDIO_LOCAL_BUS_SEL]); 606 607 return 0; 608 } 609 610 static int mt8188_afe_enable_afe_on(struct mtk_base_afe *afe) 611 { 612 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 613 return 0; 614 } 615 616 static int mt8188_afe_disable_afe_on(struct mtk_base_afe *afe) 617 { 618 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 619 return 0; 620 } 621 622 static int mt8188_afe_enable_a1sys(struct mtk_base_afe *afe) 623 { 624 struct mt8188_afe_private *afe_priv = afe->platform_priv; 625 int ret; 626 627 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 628 if (ret) 629 return ret; 630 631 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 632 } 633 634 static int mt8188_afe_disable_a1sys(struct mtk_base_afe *afe) 635 { 636 struct mt8188_afe_private *afe_priv = afe->platform_priv; 637 638 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A1SYS_TIMING); 639 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A1SYS]); 640 return 0; 641 } 642 643 static int mt8188_afe_enable_a2sys(struct mtk_base_afe *afe) 644 { 645 struct mt8188_afe_private *afe_priv = afe->platform_priv; 646 int ret; 647 648 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 649 if (ret) 650 return ret; 651 652 return mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 653 } 654 655 static int mt8188_afe_disable_a2sys(struct mtk_base_afe *afe) 656 { 657 struct mt8188_afe_private *afe_priv = afe->platform_priv; 658 659 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_A2SYS_TIMING); 660 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_AUD_A2SYS]); 661 return 0; 662 } 663 664 int mt8188_apll1_enable(struct mtk_base_afe *afe) 665 { 666 struct mt8188_afe_private *afe_priv = afe->platform_priv; 667 int ret; 668 669 ret = mt8188_afe_enable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 670 if (ret) 671 return ret; 672 673 ret = mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 674 afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 675 if (ret) 676 goto err_clk_parent; 677 678 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL1); 679 if (ret) 680 goto err_apll_tuner; 681 682 ret = mt8188_afe_enable_a1sys(afe); 683 if (ret) 684 goto err_a1sys; 685 686 return 0; 687 688 err_a1sys: 689 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 690 err_apll_tuner: 691 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 692 afe_priv->clk[MT8188_CLK_XTAL_26M]); 693 err_clk_parent: 694 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 695 696 return ret; 697 } 698 699 int mt8188_apll1_disable(struct mtk_base_afe *afe) 700 { 701 struct mt8188_afe_private *afe_priv = afe->platform_priv; 702 703 mt8188_afe_disable_a1sys(afe); 704 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL1); 705 mt8188_afe_set_clk_parent(afe, afe_priv->clk[MT8188_CLK_TOP_A1SYS_HP_SEL], 706 afe_priv->clk[MT8188_CLK_XTAL_26M]); 707 mt8188_afe_disable_clk(afe, afe_priv->clk[MT8188_CLK_TOP_APLL1_D4]); 708 709 return 0; 710 } 711 712 int mt8188_apll2_enable(struct mtk_base_afe *afe) 713 { 714 int ret; 715 716 ret = mt8188_afe_enable_apll_tuner(afe, MT8188_AUD_PLL2); 717 if (ret) 718 return ret; 719 720 ret = mt8188_afe_enable_a2sys(afe); 721 if (ret) 722 goto err_a2sys; 723 724 return 0; 725 err_a2sys: 726 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 727 728 return ret; 729 } 730 731 int mt8188_apll2_disable(struct mtk_base_afe *afe) 732 { 733 mt8188_afe_disable_a2sys(afe); 734 mt8188_afe_disable_apll_tuner(afe, MT8188_AUD_PLL2); 735 return 0; 736 } 737 738 int mt8188_afe_enable_main_clock(struct mtk_base_afe *afe) 739 { 740 mt8188_afe_enable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 741 mt8188_afe_enable_afe_on(afe); 742 return 0; 743 } 744 745 int mt8188_afe_disable_main_clock(struct mtk_base_afe *afe) 746 { 747 mt8188_afe_disable_afe_on(afe); 748 mt8188_afe_disable_top_cg(afe, MT8188_TOP_CG_26M_TIMING); 749 return 0; 750 } 751