xref: /linux/sound/soc/mediatek/mt8186/mt8186-interconnection.h (revision 80d8cad2e9ce21517d50c7084c12a59d38a778f7)
1*80d8cad2SJiaxin Yu /* SPDX-License-Identifier: GPL-2.0
2*80d8cad2SJiaxin Yu  *
3*80d8cad2SJiaxin Yu  * Mediatek MT8186 audio driver interconnection definition
4*80d8cad2SJiaxin Yu  *
5*80d8cad2SJiaxin Yu  * Copyright (c) 2022 MediaTek Inc.
6*80d8cad2SJiaxin Yu  * Author: Jiaxin Yu <jiaxin.yu@mediatek.com>
7*80d8cad2SJiaxin Yu  */
8*80d8cad2SJiaxin Yu 
9*80d8cad2SJiaxin Yu #ifndef _MT8186_INTERCONNECTION_H_
10*80d8cad2SJiaxin Yu #define _MT8186_INTERCONNECTION_H_
11*80d8cad2SJiaxin Yu 
12*80d8cad2SJiaxin Yu /* in port define */
13*80d8cad2SJiaxin Yu #define I_I2S0_CH1 0
14*80d8cad2SJiaxin Yu #define I_I2S0_CH2 1
15*80d8cad2SJiaxin Yu #define I_ADDA_UL_CH1 3
16*80d8cad2SJiaxin Yu #define I_ADDA_UL_CH2 4
17*80d8cad2SJiaxin Yu #define I_DL1_CH1 5
18*80d8cad2SJiaxin Yu #define I_DL1_CH2 6
19*80d8cad2SJiaxin Yu #define I_DL2_CH1 7
20*80d8cad2SJiaxin Yu #define I_DL2_CH2 8
21*80d8cad2SJiaxin Yu #define I_PCM_1_CAP_CH1 9
22*80d8cad2SJiaxin Yu #define I_GAIN1_OUT_CH1 10
23*80d8cad2SJiaxin Yu #define I_GAIN1_OUT_CH2 11
24*80d8cad2SJiaxin Yu #define I_GAIN2_OUT_CH1 12
25*80d8cad2SJiaxin Yu #define I_GAIN2_OUT_CH2 13
26*80d8cad2SJiaxin Yu #define I_PCM_2_CAP_CH1 14
27*80d8cad2SJiaxin Yu #define I_ADDA_UL_CH3 17
28*80d8cad2SJiaxin Yu #define I_ADDA_UL_CH4 18
29*80d8cad2SJiaxin Yu #define I_DL12_CH1 19
30*80d8cad2SJiaxin Yu #define I_DL12_CH2 20
31*80d8cad2SJiaxin Yu #define I_DL12_CH3 5
32*80d8cad2SJiaxin Yu #define I_DL12_CH4 6
33*80d8cad2SJiaxin Yu #define I_PCM_2_CAP_CH2 21
34*80d8cad2SJiaxin Yu #define I_PCM_1_CAP_CH2 22
35*80d8cad2SJiaxin Yu #define I_DL3_CH1 23
36*80d8cad2SJiaxin Yu #define I_DL3_CH2 24
37*80d8cad2SJiaxin Yu #define I_I2S2_CH1 25
38*80d8cad2SJiaxin Yu #define I_I2S2_CH2 26
39*80d8cad2SJiaxin Yu #define I_I2S2_CH3 27
40*80d8cad2SJiaxin Yu #define I_I2S2_CH4 28
41*80d8cad2SJiaxin Yu 
42*80d8cad2SJiaxin Yu /* in port define >= 32 */
43*80d8cad2SJiaxin Yu #define I_32_OFFSET 32
44*80d8cad2SJiaxin Yu #define I_CONNSYS_I2S_CH1 (34 - I_32_OFFSET)
45*80d8cad2SJiaxin Yu #define I_CONNSYS_I2S_CH2 (35 - I_32_OFFSET)
46*80d8cad2SJiaxin Yu #define I_SRC_1_OUT_CH1 (36 - I_32_OFFSET)
47*80d8cad2SJiaxin Yu #define I_SRC_1_OUT_CH2 (37 - I_32_OFFSET)
48*80d8cad2SJiaxin Yu #define I_SRC_2_OUT_CH1 (38 - I_32_OFFSET)
49*80d8cad2SJiaxin Yu #define I_SRC_2_OUT_CH2 (39 - I_32_OFFSET)
50*80d8cad2SJiaxin Yu #define I_DL4_CH1 (40 - I_32_OFFSET)
51*80d8cad2SJiaxin Yu #define I_DL4_CH2 (41 - I_32_OFFSET)
52*80d8cad2SJiaxin Yu #define I_DL5_CH1 (42 - I_32_OFFSET)
53*80d8cad2SJiaxin Yu #define I_DL5_CH2 (43 - I_32_OFFSET)
54*80d8cad2SJiaxin Yu #define I_DL6_CH1 (44 - I_32_OFFSET)
55*80d8cad2SJiaxin Yu #define I_DL6_CH2 (45 - I_32_OFFSET)
56*80d8cad2SJiaxin Yu #define I_DL7_CH1 (46 - I_32_OFFSET)
57*80d8cad2SJiaxin Yu #define I_DL7_CH2 (47 - I_32_OFFSET)
58*80d8cad2SJiaxin Yu #define I_DL8_CH1 (48 - I_32_OFFSET)
59*80d8cad2SJiaxin Yu #define I_DL8_CH2 (49 - I_32_OFFSET)
60*80d8cad2SJiaxin Yu #define I_TDM_IN_CH1 (56 - I_32_OFFSET)
61*80d8cad2SJiaxin Yu #define I_TDM_IN_CH2 (57 - I_32_OFFSET)
62*80d8cad2SJiaxin Yu #define I_TDM_IN_CH3 (58 - I_32_OFFSET)
63*80d8cad2SJiaxin Yu #define I_TDM_IN_CH4 (59 - I_32_OFFSET)
64*80d8cad2SJiaxin Yu #define I_TDM_IN_CH5 (60 - I_32_OFFSET)
65*80d8cad2SJiaxin Yu #define I_TDM_IN_CH6 (61 - I_32_OFFSET)
66*80d8cad2SJiaxin Yu #define I_TDM_IN_CH7 (62 - I_32_OFFSET)
67*80d8cad2SJiaxin Yu #define I_TDM_IN_CH8 (63 - I_32_OFFSET)
68*80d8cad2SJiaxin Yu 
69*80d8cad2SJiaxin Yu #endif
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