1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // MediaTek ALSA SoC Audio DAI ADDA Control 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/regmap.h> 9 #include <linux/delay.h> 10 #include "mt8186-afe-clk.h" 11 #include "mt8186-afe-common.h" 12 #include "mt8186-afe-gpio.h" 13 #include "mt8186-interconnection.h" 14 15 enum { 16 UL_IIR_SW = 0, 17 UL_IIR_5HZ, 18 UL_IIR_10HZ, 19 UL_IIR_25HZ, 20 UL_IIR_50HZ, 21 UL_IIR_75HZ, 22 }; 23 24 enum { 25 AUDIO_SDM_LEVEL_MUTE = 0, 26 AUDIO_SDM_LEVEL_NORMAL = 0x1d, 27 /* if you change level normal */ 28 /* you need to change formula of hp impedance and dc trim too */ 29 }; 30 31 enum { 32 AUDIO_SDM_2ND = 0, 33 AUDIO_SDM_3RD, 34 }; 35 36 enum { 37 DELAY_DATA_MISO1 = 0, 38 DELAY_DATA_MISO2, 39 }; 40 41 enum { 42 MTK_AFE_ADDA_DL_RATE_8K = 0, 43 MTK_AFE_ADDA_DL_RATE_11K = 1, 44 MTK_AFE_ADDA_DL_RATE_12K = 2, 45 MTK_AFE_ADDA_DL_RATE_16K = 3, 46 MTK_AFE_ADDA_DL_RATE_22K = 4, 47 MTK_AFE_ADDA_DL_RATE_24K = 5, 48 MTK_AFE_ADDA_DL_RATE_32K = 6, 49 MTK_AFE_ADDA_DL_RATE_44K = 7, 50 MTK_AFE_ADDA_DL_RATE_48K = 8, 51 MTK_AFE_ADDA_DL_RATE_96K = 9, 52 MTK_AFE_ADDA_DL_RATE_192K = 10, 53 }; 54 55 enum { 56 MTK_AFE_ADDA_UL_RATE_8K = 0, 57 MTK_AFE_ADDA_UL_RATE_16K = 1, 58 MTK_AFE_ADDA_UL_RATE_32K = 2, 59 MTK_AFE_ADDA_UL_RATE_48K = 3, 60 MTK_AFE_ADDA_UL_RATE_96K = 4, 61 MTK_AFE_ADDA_UL_RATE_192K = 5, 62 MTK_AFE_ADDA_UL_RATE_48K_HD = 6, 63 }; 64 65 #define SDM_AUTO_RESET_THRESHOLD 0x190000 66 67 struct mtk_afe_adda_priv { 68 int dl_rate; 69 int ul_rate; 70 }; 71 72 static struct mtk_afe_adda_priv *get_adda_priv_by_name(struct mtk_base_afe *afe, 73 const char *name) 74 { 75 struct mt8186_afe_private *afe_priv = afe->platform_priv; 76 int dai_id; 77 78 if (strncmp(name, "aud_dac", 7) == 0 || strncmp(name, "aud_adc", 7) == 0) 79 dai_id = MT8186_DAI_ADDA; 80 else 81 return NULL; 82 83 return afe_priv->dai_priv[dai_id]; 84 } 85 86 static unsigned int adda_dl_rate_transform(struct mtk_base_afe *afe, 87 unsigned int rate) 88 { 89 switch (rate) { 90 case 8000: 91 return MTK_AFE_ADDA_DL_RATE_8K; 92 case 11025: 93 return MTK_AFE_ADDA_DL_RATE_11K; 94 case 12000: 95 return MTK_AFE_ADDA_DL_RATE_12K; 96 case 16000: 97 return MTK_AFE_ADDA_DL_RATE_16K; 98 case 22050: 99 return MTK_AFE_ADDA_DL_RATE_22K; 100 case 24000: 101 return MTK_AFE_ADDA_DL_RATE_24K; 102 case 32000: 103 return MTK_AFE_ADDA_DL_RATE_32K; 104 case 44100: 105 return MTK_AFE_ADDA_DL_RATE_44K; 106 case 48000: 107 return MTK_AFE_ADDA_DL_RATE_48K; 108 case 96000: 109 return MTK_AFE_ADDA_DL_RATE_96K; 110 case 192000: 111 return MTK_AFE_ADDA_DL_RATE_192K; 112 default: 113 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 114 __func__, rate); 115 } 116 117 return MTK_AFE_ADDA_DL_RATE_48K; 118 } 119 120 static unsigned int adda_ul_rate_transform(struct mtk_base_afe *afe, 121 unsigned int rate) 122 { 123 switch (rate) { 124 case 8000: 125 return MTK_AFE_ADDA_UL_RATE_8K; 126 case 16000: 127 return MTK_AFE_ADDA_UL_RATE_16K; 128 case 32000: 129 return MTK_AFE_ADDA_UL_RATE_32K; 130 case 48000: 131 return MTK_AFE_ADDA_UL_RATE_48K; 132 case 96000: 133 return MTK_AFE_ADDA_UL_RATE_96K; 134 case 192000: 135 return MTK_AFE_ADDA_UL_RATE_192K; 136 default: 137 dev_info(afe->dev, "%s(), rate %d invalid, use 48kHz!!!\n", 138 __func__, rate); 139 } 140 141 return MTK_AFE_ADDA_UL_RATE_48K; 142 } 143 144 /* dai component */ 145 static const struct snd_kcontrol_new mtk_adda_dl_ch1_mix[] = { 146 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN3, I_DL1_CH1, 1, 0), 147 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN3, I_DL12_CH1, 1, 0), 148 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN3, I_DL2_CH1, 1, 0), 149 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN3, I_DL3_CH1, 1, 0), 150 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN3_1, I_DL4_CH1, 1, 0), 151 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN3_1, I_DL5_CH1, 1, 0), 152 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN3_1, I_DL6_CH1, 1, 0), 153 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH1 Switch", AFE_CONN3_1, I_DL8_CH1, 1, 0), 154 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN3, 155 I_ADDA_UL_CH2, 1, 0), 156 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN3, 157 I_ADDA_UL_CH1, 1, 0), 158 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN3, 159 I_GAIN1_OUT_CH1, 1, 0), 160 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN3, 161 I_PCM_1_CAP_CH1, 1, 0), 162 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH1 Switch", AFE_CONN3, 163 I_PCM_2_CAP_CH1, 1, 0), 164 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN3_1, 165 I_SRC_1_OUT_CH1, 1, 0), 166 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH1 Switch", AFE_CONN3_1, 167 I_SRC_2_OUT_CH1, 1, 0), 168 }; 169 170 static const struct snd_kcontrol_new mtk_adda_dl_ch2_mix[] = { 171 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN4, I_DL1_CH1, 1, 0), 172 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN4, I_DL1_CH2, 1, 0), 173 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN4, I_DL12_CH2, 1, 0), 174 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN4, I_DL2_CH1, 1, 0), 175 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN4, I_DL2_CH2, 1, 0), 176 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN4, I_DL3_CH1, 1, 0), 177 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN4, I_DL3_CH2, 1, 0), 178 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN4_1, I_DL4_CH2, 1, 0), 179 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN4_1, I_DL5_CH2, 1, 0), 180 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN4_1, I_DL6_CH2, 1, 0), 181 SOC_DAPM_SINGLE_AUTODISABLE("DL8_CH2 Switch", AFE_CONN4_1, I_DL8_CH2, 1, 0), 182 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN4, 183 I_ADDA_UL_CH2, 1, 0), 184 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN4, 185 I_ADDA_UL_CH1, 1, 0), 186 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN4, 187 I_GAIN1_OUT_CH2, 1, 0), 188 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN4, 189 I_PCM_1_CAP_CH2, 1, 0), 190 SOC_DAPM_SINGLE_AUTODISABLE("PCM_2_CAP_CH2 Switch", AFE_CONN4, 191 I_PCM_2_CAP_CH2, 1, 0), 192 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN4_1, 193 I_SRC_1_OUT_CH2, 1, 0), 194 SOC_DAPM_SINGLE_AUTODISABLE("SRC_2_OUT_CH2 Switch", AFE_CONN4_1, 195 I_SRC_2_OUT_CH2, 1, 0), 196 }; 197 198 enum { 199 SUPPLY_SEQ_ADDA_AFE_ON, 200 SUPPLY_SEQ_ADDA_DL_ON, 201 SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 202 SUPPLY_SEQ_ADDA_MTKAIF_CFG, 203 SUPPLY_SEQ_ADDA_FIFO, 204 SUPPLY_SEQ_ADDA_AP_DMIC, 205 SUPPLY_SEQ_ADDA_UL_ON, 206 }; 207 208 static int mtk_adda_ul_src_dmic(struct mtk_base_afe *afe, int id) 209 { 210 unsigned int reg; 211 212 switch (id) { 213 case MT8186_DAI_ADDA: 214 case MT8186_DAI_AP_DMIC: 215 reg = AFE_ADDA_UL_SRC_CON0; 216 break; 217 default: 218 return -EINVAL; 219 } 220 221 /* dmic mode, 3.25M*/ 222 regmap_update_bits(afe->regmap, reg, 223 DIGMIC_3P25M_1P625M_SEL_MASK_SFT, 0); 224 regmap_update_bits(afe->regmap, reg, 225 DMIC_LOW_POWER_CTL_MASK_SFT, 0); 226 227 /* turn on dmic, ch1, ch2 */ 228 regmap_update_bits(afe->regmap, reg, 229 UL_SDM_3_LEVEL_MASK_SFT, 230 BIT(UL_SDM_3_LEVEL_SFT)); 231 regmap_update_bits(afe->regmap, reg, 232 UL_MODE_3P25M_CH1_CTL_MASK_SFT, 233 BIT(UL_MODE_3P25M_CH1_CTL_SFT)); 234 regmap_update_bits(afe->regmap, reg, 235 UL_MODE_3P25M_CH2_CTL_MASK_SFT, 236 BIT(UL_MODE_3P25M_CH2_CTL_SFT)); 237 238 return 0; 239 } 240 241 static int mtk_adda_ul_event(struct snd_soc_dapm_widget *w, 242 struct snd_kcontrol *kcontrol, 243 int event) 244 { 245 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 246 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 247 struct mt8186_afe_private *afe_priv = afe->platform_priv; 248 int mtkaif_dmic = afe_priv->mtkaif_dmic; 249 250 dev_dbg(afe->dev, "%s(), name %s, event 0x%x, mtkaif_dmic %d\n", 251 __func__, w->name, event, mtkaif_dmic); 252 253 switch (event) { 254 case SND_SOC_DAPM_PRE_PMU: 255 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 1); 256 257 /* update setting to dmic */ 258 if (mtkaif_dmic) { 259 /* mtkaif_rxif_data_mode = 1, dmic */ 260 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 261 0x1, 0x1); 262 263 /* dmic mode, 3.25M*/ 264 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, 265 MTKAIF_RXIF_VOICE_MODE_MASK_SFT, 266 0x0); 267 mtk_adda_ul_src_dmic(afe, MT8186_DAI_ADDA); 268 } 269 break; 270 case SND_SOC_DAPM_POST_PMD: 271 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 272 usleep_range(125, 135); 273 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 1); 274 break; 275 default: 276 break; 277 } 278 279 return 0; 280 } 281 282 static int mtk_adda_pad_top_event(struct snd_soc_dapm_widget *w, 283 struct snd_kcontrol *kcontrol, 284 int event) 285 { 286 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 287 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 288 struct mt8186_afe_private *afe_priv = afe->platform_priv; 289 290 switch (event) { 291 case SND_SOC_DAPM_PRE_PMU: 292 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) 293 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x39); 294 else 295 regmap_write(afe->regmap, AFE_AUD_PAD_TOP, 0x31); 296 break; 297 default: 298 break; 299 } 300 301 return 0; 302 } 303 304 static int mtk_adda_mtkaif_cfg_event(struct snd_soc_dapm_widget *w, 305 struct snd_kcontrol *kcontrol, 306 int event) 307 { 308 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 309 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 310 struct mt8186_afe_private *afe_priv = afe->platform_priv; 311 int delay_data; 312 int delay_cycle; 313 314 switch (event) { 315 case SND_SOC_DAPM_PRE_PMU: 316 if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2_CLK_P2) { 317 /* set protocol 2 */ 318 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 319 /* mtkaif_rxif_clkinv_adc inverse */ 320 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 321 MTKAIF_RXIF_CLKINV_ADC_MASK_SFT, 322 BIT(MTKAIF_RXIF_CLKINV_ADC_SFT)); 323 324 if (strcmp(w->name, "ADDA_MTKAIF_CFG") == 0) { 325 if (afe_priv->mtkaif_chosen_phase[0] < 0 && 326 afe_priv->mtkaif_chosen_phase[1] < 0) { 327 dev_err(afe->dev, 328 "%s(), calib fail mtkaif_chosen_phase[0/1]:%d/%d\n", 329 __func__, 330 afe_priv->mtkaif_chosen_phase[0], 331 afe_priv->mtkaif_chosen_phase[1]); 332 break; 333 } 334 335 if (afe_priv->mtkaif_chosen_phase[0] < 0 || 336 afe_priv->mtkaif_chosen_phase[1] < 0) { 337 dev_err(afe->dev, 338 "%s(), skip delay setting mtkaif_chosen_phase[0/1]:%d/%d\n", 339 __func__, 340 afe_priv->mtkaif_chosen_phase[0], 341 afe_priv->mtkaif_chosen_phase[1]); 342 break; 343 } 344 } 345 346 /* set delay for ch12 */ 347 if (afe_priv->mtkaif_phase_cycle[0] >= 348 afe_priv->mtkaif_phase_cycle[1]) { 349 delay_data = DELAY_DATA_MISO1; 350 delay_cycle = afe_priv->mtkaif_phase_cycle[0] - 351 afe_priv->mtkaif_phase_cycle[1]; 352 } else { 353 delay_data = DELAY_DATA_MISO2; 354 delay_cycle = afe_priv->mtkaif_phase_cycle[1] - 355 afe_priv->mtkaif_phase_cycle[0]; 356 } 357 358 regmap_update_bits(afe->regmap, 359 AFE_ADDA_MTKAIF_RX_CFG2, 360 MTKAIF_RXIF_DELAY_DATA_MASK_SFT, 361 delay_data << 362 MTKAIF_RXIF_DELAY_DATA_SFT); 363 364 regmap_update_bits(afe->regmap, 365 AFE_ADDA_MTKAIF_RX_CFG2, 366 MTKAIF_RXIF_DELAY_CYCLE_MASK_SFT, 367 delay_cycle << 368 MTKAIF_RXIF_DELAY_CYCLE_SFT); 369 370 } else if (afe_priv->mtkaif_protocol == MTKAIF_PROTOCOL_2) { 371 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0x10000); 372 } else { 373 regmap_write(afe->regmap, AFE_ADDA_MTKAIF_CFG0, 0); 374 } 375 376 break; 377 default: 378 break; 379 } 380 381 return 0; 382 } 383 384 static int mtk_adda_dl_event(struct snd_soc_dapm_widget *w, 385 struct snd_kcontrol *kcontrol, 386 int event) 387 { 388 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 389 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 390 391 dev_dbg(afe->dev, "%s(), name %s, event 0x%x\n", 392 __func__, w->name, event); 393 394 switch (event) { 395 case SND_SOC_DAPM_PRE_PMU: 396 mt8186_afe_gpio_request(afe->dev, true, MT8186_DAI_ADDA, 0); 397 break; 398 case SND_SOC_DAPM_POST_PMD: 399 /* should delayed 1/fs(smallest is 8k) = 125us before afe off */ 400 usleep_range(125, 135); 401 mt8186_afe_gpio_request(afe->dev, false, MT8186_DAI_ADDA, 0); 402 break; 403 default: 404 break; 405 } 406 407 return 0; 408 } 409 410 static int mt8186_adda_dmic_get(struct snd_kcontrol *kcontrol, 411 struct snd_ctl_elem_value *ucontrol) 412 { 413 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 414 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 415 struct mt8186_afe_private *afe_priv = afe->platform_priv; 416 417 ucontrol->value.integer.value[0] = afe_priv->mtkaif_dmic; 418 419 return 0; 420 } 421 422 static int mt8186_adda_dmic_set(struct snd_kcontrol *kcontrol, 423 struct snd_ctl_elem_value *ucontrol) 424 { 425 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 426 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 427 struct mt8186_afe_private *afe_priv = afe->platform_priv; 428 int dmic_on; 429 430 dmic_on = ucontrol->value.integer.value[0]; 431 432 dev_dbg(afe->dev, "%s(), kcontrol name %s, dmic_on %d\n", 433 __func__, kcontrol->id.name, dmic_on); 434 435 if (afe_priv->mtkaif_dmic == dmic_on) 436 return 0; 437 438 afe_priv->mtkaif_dmic = dmic_on; 439 440 return 1; 441 } 442 443 static const struct snd_kcontrol_new mtk_adda_controls[] = { 444 SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, 445 DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), 446 SOC_SINGLE_BOOL_EXT("MTKAIF_DMIC Switch", 0, 447 mt8186_adda_dmic_get, mt8186_adda_dmic_set), 448 }; 449 450 /* ADDA UL MUX */ 451 enum { 452 ADDA_UL_MUX_MTKAIF = 0, 453 ADDA_UL_MUX_AP_DMIC, 454 ADDA_UL_MUX_MASK = 0x1, 455 }; 456 457 static const char * const adda_ul_mux_map[] = { 458 "MTKAIF", "AP_DMIC" 459 }; 460 461 static int adda_ul_map_value[] = { 462 ADDA_UL_MUX_MTKAIF, 463 ADDA_UL_MUX_AP_DMIC, 464 }; 465 466 static SOC_VALUE_ENUM_SINGLE_DECL(adda_ul_mux_map_enum, 467 SND_SOC_NOPM, 468 0, 469 ADDA_UL_MUX_MASK, 470 adda_ul_mux_map, 471 adda_ul_map_value); 472 473 static const struct snd_kcontrol_new adda_ul_mux_control = 474 SOC_DAPM_ENUM("ADDA_UL_MUX Select", adda_ul_mux_map_enum); 475 476 static const struct snd_soc_dapm_widget mtk_dai_adda_widgets[] = { 477 /* inter-connections */ 478 SND_SOC_DAPM_MIXER("ADDA_DL_CH1", SND_SOC_NOPM, 0, 0, 479 mtk_adda_dl_ch1_mix, 480 ARRAY_SIZE(mtk_adda_dl_ch1_mix)), 481 SND_SOC_DAPM_MIXER("ADDA_DL_CH2", SND_SOC_NOPM, 0, 0, 482 mtk_adda_dl_ch2_mix, 483 ARRAY_SIZE(mtk_adda_dl_ch2_mix)), 484 485 SND_SOC_DAPM_SUPPLY_S("ADDA Enable", SUPPLY_SEQ_ADDA_AFE_ON, 486 AFE_ADDA_UL_DL_CON0, ADDA_AFE_ON_SFT, 0, 487 NULL, 0), 488 489 SND_SOC_DAPM_SUPPLY_S("ADDA Playback Enable", SUPPLY_SEQ_ADDA_DL_ON, 490 AFE_ADDA_DL_SRC2_CON0, 491 DL_2_SRC_ON_CTL_PRE_SFT, 0, 492 mtk_adda_dl_event, 493 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 494 495 SND_SOC_DAPM_SUPPLY_S("ADDA Capture Enable", SUPPLY_SEQ_ADDA_UL_ON, 496 AFE_ADDA_UL_SRC_CON0, 497 UL_SRC_ON_CTL_SFT, 0, 498 mtk_adda_ul_event, 499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 500 501 SND_SOC_DAPM_SUPPLY_S("AUD_PAD_TOP", SUPPLY_SEQ_ADDA_AUD_PAD_TOP, 502 0, 0, 0, 503 mtk_adda_pad_top_event, 504 SND_SOC_DAPM_PRE_PMU), 505 SND_SOC_DAPM_SUPPLY_S("ADDA_MTKAIF_CFG", SUPPLY_SEQ_ADDA_MTKAIF_CFG, 506 SND_SOC_NOPM, 0, 0, 507 mtk_adda_mtkaif_cfg_event, 508 SND_SOC_DAPM_PRE_PMU), 509 510 SND_SOC_DAPM_SUPPLY_S("AP_DMIC_EN", SUPPLY_SEQ_ADDA_AP_DMIC, 511 AFE_ADDA_UL_SRC_CON0, 512 UL_AP_DMIC_ON_SFT, 0, 513 NULL, 0), 514 515 SND_SOC_DAPM_SUPPLY_S("ADDA_FIFO", SUPPLY_SEQ_ADDA_FIFO, 516 AFE_ADDA_UL_DL_CON0, 517 AFE_ADDA_FIFO_AUTO_RST_SFT, 1, 518 NULL, 0), 519 520 SND_SOC_DAPM_MUX("ADDA_UL_Mux", SND_SOC_NOPM, 0, 0, 521 &adda_ul_mux_control), 522 523 SND_SOC_DAPM_INPUT("AP_DMIC_INPUT"), 524 525 /* clock */ 526 SND_SOC_DAPM_CLOCK_SUPPLY("top_mux_audio_h"), 527 528 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_clk"), 529 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_hires_clk"), 530 SND_SOC_DAPM_CLOCK_SUPPLY("aud_dac_predis_clk"), 531 532 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_clk"), 533 SND_SOC_DAPM_CLOCK_SUPPLY("aud_adc_hires_clk"), 534 }; 535 536 #define HIRES_THRESHOLD 48000 537 static int mtk_afe_dac_hires_connect(struct snd_soc_dapm_widget *source, 538 struct snd_soc_dapm_widget *sink) 539 { 540 struct snd_soc_dapm_widget *w = source; 541 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 542 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 543 struct mtk_afe_adda_priv *adda_priv; 544 545 adda_priv = get_adda_priv_by_name(afe, w->name); 546 547 if (!adda_priv) { 548 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 549 return 0; 550 } 551 552 return (adda_priv->dl_rate > HIRES_THRESHOLD) ? 1 : 0; 553 } 554 555 static int mtk_afe_adc_hires_connect(struct snd_soc_dapm_widget *source, 556 struct snd_soc_dapm_widget *sink) 557 { 558 struct snd_soc_dapm_widget *w = source; 559 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm); 560 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 561 struct mtk_afe_adda_priv *adda_priv; 562 563 adda_priv = get_adda_priv_by_name(afe, w->name); 564 565 if (!adda_priv) { 566 dev_err(afe->dev, "%s(), adda_priv == NULL", __func__); 567 return 0; 568 } 569 570 return (adda_priv->ul_rate > HIRES_THRESHOLD) ? 1 : 0; 571 } 572 573 static const struct snd_soc_dapm_route mtk_dai_adda_routes[] = { 574 /* playback */ 575 {"ADDA_DL_CH1", "DL1_CH1 Switch", "DL1"}, 576 {"ADDA_DL_CH2", "DL1_CH1 Switch", "DL1"}, 577 {"ADDA_DL_CH2", "DL1_CH2 Switch", "DL1"}, 578 579 {"ADDA_DL_CH1", "DL12_CH1 Switch", "DL12"}, 580 {"ADDA_DL_CH2", "DL12_CH2 Switch", "DL12"}, 581 582 {"ADDA_DL_CH1", "DL6_CH1 Switch", "DL6"}, 583 {"ADDA_DL_CH2", "DL6_CH2 Switch", "DL6"}, 584 585 {"ADDA_DL_CH1", "DL8_CH1 Switch", "DL8"}, 586 {"ADDA_DL_CH2", "DL8_CH2 Switch", "DL8"}, 587 588 {"ADDA_DL_CH1", "DL2_CH1 Switch", "DL2"}, 589 {"ADDA_DL_CH2", "DL2_CH1 Switch", "DL2"}, 590 {"ADDA_DL_CH2", "DL2_CH2 Switch", "DL2"}, 591 592 {"ADDA_DL_CH1", "DL3_CH1 Switch", "DL3"}, 593 {"ADDA_DL_CH2", "DL3_CH1 Switch", "DL3"}, 594 {"ADDA_DL_CH2", "DL3_CH2 Switch", "DL3"}, 595 596 {"ADDA_DL_CH1", "DL4_CH1 Switch", "DL4"}, 597 {"ADDA_DL_CH2", "DL4_CH2 Switch", "DL4"}, 598 599 {"ADDA_DL_CH1", "DL5_CH1 Switch", "DL5"}, 600 {"ADDA_DL_CH2", "DL5_CH2 Switch", "DL5"}, 601 602 {"ADDA Playback", NULL, "ADDA_DL_CH1"}, 603 {"ADDA Playback", NULL, "ADDA_DL_CH2"}, 604 605 {"ADDA Playback", NULL, "ADDA Enable"}, 606 {"ADDA Playback", NULL, "ADDA Playback Enable"}, 607 608 /* capture */ 609 {"ADDA_UL_Mux", "MTKAIF", "ADDA Capture"}, 610 {"ADDA_UL_Mux", "AP_DMIC", "AP DMIC Capture"}, 611 612 {"ADDA Capture", NULL, "ADDA Enable"}, 613 {"ADDA Capture", NULL, "ADDA Capture Enable"}, 614 {"ADDA Capture", NULL, "AUD_PAD_TOP"}, 615 {"ADDA Capture", NULL, "ADDA_MTKAIF_CFG"}, 616 617 {"AP DMIC Capture", NULL, "ADDA Enable"}, 618 {"AP DMIC Capture", NULL, "ADDA Capture Enable"}, 619 {"AP DMIC Capture", NULL, "ADDA_FIFO"}, 620 {"AP DMIC Capture", NULL, "AP_DMIC_EN"}, 621 622 {"AP DMIC Capture", NULL, "AP_DMIC_INPUT"}, 623 624 /* clk */ 625 {"ADDA Playback", NULL, "aud_dac_clk"}, 626 {"ADDA Playback", NULL, "aud_dac_predis_clk"}, 627 {"ADDA Playback", NULL, "aud_dac_hires_clk", mtk_afe_dac_hires_connect}, 628 629 {"ADDA Capture Enable", NULL, "aud_adc_clk"}, 630 {"ADDA Capture Enable", NULL, "aud_adc_hires_clk", 631 mtk_afe_adc_hires_connect}, 632 633 /* hires source from apll1 */ 634 {"top_mux_audio_h", NULL, APLL2_W_NAME}, 635 636 {"aud_dac_hires_clk", NULL, "top_mux_audio_h"}, 637 {"aud_adc_hires_clk", NULL, "top_mux_audio_h"}, 638 }; 639 640 /* dai ops */ 641 static int mtk_dai_adda_hw_params(struct snd_pcm_substream *substream, 642 struct snd_pcm_hw_params *params, 643 struct snd_soc_dai *dai) 644 { 645 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 646 struct mt8186_afe_private *afe_priv = afe->platform_priv; 647 unsigned int rate = params_rate(params); 648 int id = dai->id; 649 struct mtk_afe_adda_priv *adda_priv = afe_priv->dai_priv[id]; 650 651 dev_dbg(afe->dev, "%s(), id %d, stream %d, rate %d\n", 652 __func__, id, substream->stream, rate); 653 654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 655 unsigned int dl_src2_con0; 656 unsigned int dl_src2_con1; 657 658 adda_priv->dl_rate = rate; 659 660 /* set sampling rate */ 661 dl_src2_con0 = adda_dl_rate_transform(afe, rate) << 662 DL_2_INPUT_MODE_CTL_SFT; 663 664 /* set output mode, UP_SAMPLING_RATE_X8 */ 665 dl_src2_con0 |= (0x3 << DL_2_OUTPUT_SEL_CTL_SFT); 666 667 /* turn off mute function */ 668 dl_src2_con0 |= BIT(DL_2_MUTE_CH2_OFF_CTL_PRE_SFT); 669 dl_src2_con0 |= BIT(DL_2_MUTE_CH1_OFF_CTL_PRE_SFT); 670 671 /* set voice input data if input sample rate is 8k or 16k */ 672 if (rate == 8000 || rate == 16000) 673 dl_src2_con0 |= BIT(DL_2_VOICE_MODE_CTL_PRE_SFT); 674 675 /* SA suggest apply -0.3db to audio/speech path */ 676 dl_src2_con1 = MTK_AFE_ADDA_DL_GAIN_NORMAL << 677 DL_2_GAIN_CTL_PRE_SFT; 678 679 /* turn on down-link gain */ 680 dl_src2_con0 |= BIT(DL_2_GAIN_ON_CTL_PRE_SFT); 681 682 if (id == MT8186_DAI_ADDA) { 683 /* clean predistortion */ 684 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON0, 0); 685 regmap_write(afe->regmap, AFE_ADDA_PREDIS_CON1, 0); 686 687 regmap_write(afe->regmap, 688 AFE_ADDA_DL_SRC2_CON0, dl_src2_con0); 689 regmap_write(afe->regmap, 690 AFE_ADDA_DL_SRC2_CON1, dl_src2_con1); 691 692 /* set sdm gain */ 693 regmap_update_bits(afe->regmap, 694 AFE_ADDA_DL_SDM_DCCOMP_CON, 695 ATTGAIN_CTL_MASK_SFT, 696 AUDIO_SDM_LEVEL_NORMAL << 697 ATTGAIN_CTL_SFT); 698 699 /* Use new 2nd sdm */ 700 regmap_update_bits(afe->regmap, 701 AFE_ADDA_DL_SDM_DITHER_CON, 702 AFE_DL_SDM_DITHER_64TAP_EN_MASK_SFT, 703 BIT(AFE_DL_SDM_DITHER_64TAP_EN_SFT)); 704 regmap_update_bits(afe->regmap, 705 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 706 AFE_DL_USE_NEW_2ND_SDM_MASK_SFT, 707 BIT(AFE_DL_USE_NEW_2ND_SDM_SFT)); 708 regmap_update_bits(afe->regmap, 709 AFE_ADDA_DL_SDM_DCCOMP_CON, 710 USE_3RD_SDM_MASK_SFT, 711 AUDIO_SDM_2ND << USE_3RD_SDM_SFT); 712 713 /* sdm auto reset */ 714 regmap_write(afe->regmap, 715 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 716 SDM_AUTO_RESET_THRESHOLD); 717 regmap_update_bits(afe->regmap, 718 AFE_ADDA_DL_SDM_AUTO_RESET_CON, 719 SDM_AUTO_RESET_TEST_ON_MASK_SFT, 720 BIT(SDM_AUTO_RESET_TEST_ON_SFT)); 721 } 722 } else { 723 unsigned int ul_src_con0 = 0; 724 unsigned int voice_mode = adda_ul_rate_transform(afe, rate); 725 726 adda_priv->ul_rate = rate; 727 ul_src_con0 |= (voice_mode << 17) & (0x7 << 17); 728 729 /* enable iir */ 730 ul_src_con0 |= (1 << UL_IIR_ON_TMP_CTL_SFT) & 731 UL_IIR_ON_TMP_CTL_MASK_SFT; 732 ul_src_con0 |= (UL_IIR_SW << UL_IIRMODE_CTL_SFT) & 733 UL_IIRMODE_CTL_MASK_SFT; 734 switch (id) { 735 case MT8186_DAI_ADDA: 736 case MT8186_DAI_AP_DMIC: 737 /* 35Hz @ 48k */ 738 regmap_write(afe->regmap, 739 AFE_ADDA_IIR_COEF_02_01, 0); 740 regmap_write(afe->regmap, 741 AFE_ADDA_IIR_COEF_04_03, 0x3fb8); 742 regmap_write(afe->regmap, 743 AFE_ADDA_IIR_COEF_06_05, 0x3fb80000); 744 regmap_write(afe->regmap, 745 AFE_ADDA_IIR_COEF_08_07, 0x3fb80000); 746 regmap_write(afe->regmap, 747 AFE_ADDA_IIR_COEF_10_09, 0xc048); 748 749 regmap_write(afe->regmap, 750 AFE_ADDA_UL_SRC_CON0, ul_src_con0); 751 752 /* Using Internal ADC */ 753 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, BIT(0), 0); 754 755 /* mtkaif_rxif_data_mode = 0, amic */ 756 regmap_update_bits(afe->regmap, AFE_ADDA_MTKAIF_RX_CFG0, BIT(0), 0); 757 break; 758 default: 759 break; 760 } 761 762 /* ap dmic */ 763 switch (id) { 764 case MT8186_DAI_AP_DMIC: 765 mtk_adda_ul_src_dmic(afe, id); 766 break; 767 default: 768 break; 769 } 770 } 771 772 return 0; 773 } 774 775 static const struct snd_soc_dai_ops mtk_dai_adda_ops = { 776 .hw_params = mtk_dai_adda_hw_params, 777 }; 778 779 /* dai driver */ 780 #define MTK_ADDA_PLAYBACK_RATES (SNDRV_PCM_RATE_8000_48000 |\ 781 SNDRV_PCM_RATE_96000 |\ 782 SNDRV_PCM_RATE_192000) 783 784 #define MTK_ADDA_CAPTURE_RATES (SNDRV_PCM_RATE_8000 |\ 785 SNDRV_PCM_RATE_16000 |\ 786 SNDRV_PCM_RATE_32000 |\ 787 SNDRV_PCM_RATE_48000 |\ 788 SNDRV_PCM_RATE_96000 |\ 789 SNDRV_PCM_RATE_192000) 790 791 #define MTK_ADDA_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 792 SNDRV_PCM_FMTBIT_S24_LE |\ 793 SNDRV_PCM_FMTBIT_S32_LE) 794 795 static struct snd_soc_dai_driver mtk_dai_adda_driver[] = { 796 { 797 .name = "ADDA", 798 .id = MT8186_DAI_ADDA, 799 .playback = { 800 .stream_name = "ADDA Playback", 801 .channels_min = 1, 802 .channels_max = 2, 803 .rates = MTK_ADDA_PLAYBACK_RATES, 804 .formats = MTK_ADDA_FORMATS, 805 }, 806 .capture = { 807 .stream_name = "ADDA Capture", 808 .channels_min = 1, 809 .channels_max = 2, 810 .rates = MTK_ADDA_CAPTURE_RATES, 811 .formats = MTK_ADDA_FORMATS, 812 }, 813 .ops = &mtk_dai_adda_ops, 814 }, 815 { 816 .name = "AP_DMIC", 817 .id = MT8186_DAI_AP_DMIC, 818 .capture = { 819 .stream_name = "AP DMIC Capture", 820 .channels_min = 1, 821 .channels_max = 2, 822 .rates = MTK_ADDA_CAPTURE_RATES, 823 .formats = MTK_ADDA_FORMATS, 824 }, 825 .ops = &mtk_dai_adda_ops, 826 }, 827 }; 828 829 int mt8186_dai_adda_register(struct mtk_base_afe *afe) 830 { 831 struct mtk_base_afe_dai *dai; 832 struct mt8186_afe_private *afe_priv = afe->platform_priv; 833 int ret; 834 835 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 836 if (!dai) 837 return -ENOMEM; 838 839 list_add(&dai->list, &afe->sub_dais); 840 841 dai->dai_drivers = mtk_dai_adda_driver; 842 dai->num_dai_drivers = ARRAY_SIZE(mtk_dai_adda_driver); 843 844 dai->controls = mtk_adda_controls; 845 dai->num_controls = ARRAY_SIZE(mtk_adda_controls); 846 dai->dapm_widgets = mtk_dai_adda_widgets; 847 dai->num_dapm_widgets = ARRAY_SIZE(mtk_dai_adda_widgets); 848 dai->dapm_routes = mtk_dai_adda_routes; 849 dai->num_dapm_routes = ARRAY_SIZE(mtk_dai_adda_routes); 850 851 /* set dai priv */ 852 ret = mt8186_dai_set_priv(afe, MT8186_DAI_ADDA, 853 sizeof(struct mtk_afe_adda_priv), NULL); 854 if (ret) 855 return ret; 856 857 /* ap dmic priv share with adda */ 858 afe_priv->dai_priv[MT8186_DAI_AP_DMIC] = 859 afe_priv->dai_priv[MT8186_DAI_ADDA]; 860 861 return 0; 862 } 863