1*58949aa3SJiaxin Yu // SPDX-License-Identifier: GPL-2.0 2*58949aa3SJiaxin Yu // 3*58949aa3SJiaxin Yu // mt8186-audsys-clk.h -- Mediatek 8186 audsys clock control 4*58949aa3SJiaxin Yu // 5*58949aa3SJiaxin Yu // Copyright (c) 2022 MediaTek Inc. 6*58949aa3SJiaxin Yu // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7*58949aa3SJiaxin Yu 8*58949aa3SJiaxin Yu #include <linux/clk.h> 9*58949aa3SJiaxin Yu #include <linux/clk-provider.h> 10*58949aa3SJiaxin Yu #include <linux/clkdev.h> 11*58949aa3SJiaxin Yu #include "mt8186-afe-common.h" 12*58949aa3SJiaxin Yu #include "mt8186-audsys-clk.h" 13*58949aa3SJiaxin Yu #include "mt8186-audsys-clkid.h" 14*58949aa3SJiaxin Yu #include "mt8186-reg.h" 15*58949aa3SJiaxin Yu 16*58949aa3SJiaxin Yu struct afe_gate { 17*58949aa3SJiaxin Yu int id; 18*58949aa3SJiaxin Yu const char *name; 19*58949aa3SJiaxin Yu const char *parent_name; 20*58949aa3SJiaxin Yu int reg; 21*58949aa3SJiaxin Yu u8 bit; 22*58949aa3SJiaxin Yu const struct clk_ops *ops; 23*58949aa3SJiaxin Yu unsigned long flags; 24*58949aa3SJiaxin Yu u8 cg_flags; 25*58949aa3SJiaxin Yu }; 26*58949aa3SJiaxin Yu 27*58949aa3SJiaxin Yu #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ 28*58949aa3SJiaxin Yu .id = _id, \ 29*58949aa3SJiaxin Yu .name = _name, \ 30*58949aa3SJiaxin Yu .parent_name = _parent, \ 31*58949aa3SJiaxin Yu .reg = _reg, \ 32*58949aa3SJiaxin Yu .bit = _bit, \ 33*58949aa3SJiaxin Yu .flags = _flags, \ 34*58949aa3SJiaxin Yu .cg_flags = _cgflags, \ 35*58949aa3SJiaxin Yu } 36*58949aa3SJiaxin Yu 37*58949aa3SJiaxin Yu #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ 38*58949aa3SJiaxin Yu GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \ 39*58949aa3SJiaxin Yu CLK_SET_RATE_PARENT, CLK_GATE_SET_TO_DISABLE) 40*58949aa3SJiaxin Yu 41*58949aa3SJiaxin Yu #define GATE_AUD0(_id, _name, _parent, _bit) \ 42*58949aa3SJiaxin Yu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit) 43*58949aa3SJiaxin Yu 44*58949aa3SJiaxin Yu #define GATE_AUD1(_id, _name, _parent, _bit) \ 45*58949aa3SJiaxin Yu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit) 46*58949aa3SJiaxin Yu 47*58949aa3SJiaxin Yu #define GATE_AUD2(_id, _name, _parent, _bit) \ 48*58949aa3SJiaxin Yu GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit) 49*58949aa3SJiaxin Yu 50*58949aa3SJiaxin Yu static const struct afe_gate aud_clks[CLK_AUD_NR_CLK] = { 51*58949aa3SJiaxin Yu /* AUD0 */ 52*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_AFE, "aud_afe_clk", "top_audio", 2), 53*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_22M, "aud_apll22m_clk", "top_aud_engen1", 8), 54*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_24M, "aud_apll24m_clk", "top_aud_engen2", 9), 55*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_APLL2_TUNER, "aud_apll2_tuner_clk", "top_aud_engen2", 18), 56*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_APLL_TUNER, "aud_apll_tuner_clk", "top_aud_engen1", 19), 57*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_TDM, "aud_tdm_clk", "top_aud_1", 20), 58*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_ADC, "aud_adc_clk", "top_audio", 24), 59*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_DAC, "aud_dac_clk", "top_audio", 25), 60*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_DAC_PREDIS, "aud_dac_predis_clk", "top_audio", 26), 61*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_TML, "aud_tml_clk", "top_audio", 27), 62*58949aa3SJiaxin Yu GATE_AUD0(CLK_AUD_NLE, "aud_nle_clk", "top_audio", 28), 63*58949aa3SJiaxin Yu 64*58949aa3SJiaxin Yu /* AUD1 */ 65*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_I2S1_BCLK, "aud_i2s1_bclk", "top_audio", 4), 66*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_I2S2_BCLK, "aud_i2s2_bclk", "top_audio", 5), 67*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_I2S3_BCLK, "aud_i2s3_bclk", "top_audio", 6), 68*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_I2S4_BCLK, "aud_i2s4_bclk", "top_audio", 7), 69*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_CONNSYS_I2S_ASRC, "aud_connsys_i2s_asrc", "top_audio", 12), 70*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_GENERAL1_ASRC, "aud_general1_asrc", "top_audio", 13), 71*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_GENERAL2_ASRC, "aud_general2_asrc", "top_audio", 14), 72*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_DAC_HIRES, "aud_dac_hires_clk", "top_audio_h", 15), 73*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_ADC_HIRES, "aud_adc_hires_clk", "top_audio_h", 16), 74*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_ADC_HIRES_TML, "aud_adc_hires_tml", "top_audio_h", 17), 75*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_ADDA6_ADC, "aud_adda6_adc", "top_audio", 20), 76*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_ADDA6_ADC_HIRES, "aud_adda6_adc_hires", "top_audio_h", 21), 77*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_3RD_DAC, "aud_3rd_dac", "top_audio", 28), 78*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_3RD_DAC_PREDIS, "aud_3rd_dac_predis", "top_audio", 29), 79*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_3RD_DAC_TML, "aud_3rd_dac_tml", "top_audio", 30), 80*58949aa3SJiaxin Yu GATE_AUD1(CLK_AUD_3RD_DAC_HIRES, "aud_3rd_dac_hires", "top_audio_h", 31), 81*58949aa3SJiaxin Yu 82*58949aa3SJiaxin Yu /* AUD2 */ 83*58949aa3SJiaxin Yu GATE_AUD2(CLK_AUD_ETDM_IN1_BCLK, "aud_etdm_in1_bclk", "top_audio", 23), 84*58949aa3SJiaxin Yu GATE_AUD2(CLK_AUD_ETDM_OUT1_BCLK, "aud_etdm_out1_bclk", "top_audio", 24), 85*58949aa3SJiaxin Yu }; 86*58949aa3SJiaxin Yu 87*58949aa3SJiaxin Yu int mt8186_audsys_clk_register(struct mtk_base_afe *afe) 88*58949aa3SJiaxin Yu { 89*58949aa3SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 90*58949aa3SJiaxin Yu struct clk *clk; 91*58949aa3SJiaxin Yu struct clk_lookup *cl; 92*58949aa3SJiaxin Yu int i; 93*58949aa3SJiaxin Yu 94*58949aa3SJiaxin Yu afe_priv->lookup = devm_kcalloc(afe->dev, CLK_AUD_NR_CLK, 95*58949aa3SJiaxin Yu sizeof(*afe_priv->lookup), 96*58949aa3SJiaxin Yu GFP_KERNEL); 97*58949aa3SJiaxin Yu 98*58949aa3SJiaxin Yu if (!afe_priv->lookup) 99*58949aa3SJiaxin Yu return -ENOMEM; 100*58949aa3SJiaxin Yu 101*58949aa3SJiaxin Yu for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 102*58949aa3SJiaxin Yu const struct afe_gate *gate = &aud_clks[i]; 103*58949aa3SJiaxin Yu 104*58949aa3SJiaxin Yu clk = clk_register_gate(afe->dev, gate->name, gate->parent_name, 105*58949aa3SJiaxin Yu gate->flags, afe->base_addr + gate->reg, 106*58949aa3SJiaxin Yu gate->bit, gate->cg_flags, NULL); 107*58949aa3SJiaxin Yu 108*58949aa3SJiaxin Yu if (IS_ERR(clk)) { 109*58949aa3SJiaxin Yu dev_err(afe->dev, "Failed to register clk %s: %ld\n", 110*58949aa3SJiaxin Yu gate->name, PTR_ERR(clk)); 111*58949aa3SJiaxin Yu continue; 112*58949aa3SJiaxin Yu } 113*58949aa3SJiaxin Yu 114*58949aa3SJiaxin Yu /* add clk_lookup for devm_clk_get(SND_SOC_DAPM_CLOCK_SUPPLY) */ 115*58949aa3SJiaxin Yu cl = kzalloc(sizeof(*cl), GFP_KERNEL); 116*58949aa3SJiaxin Yu if (!cl) 117*58949aa3SJiaxin Yu return -ENOMEM; 118*58949aa3SJiaxin Yu 119*58949aa3SJiaxin Yu cl->clk = clk; 120*58949aa3SJiaxin Yu cl->con_id = gate->name; 121*58949aa3SJiaxin Yu cl->dev_id = dev_name(afe->dev); 122*58949aa3SJiaxin Yu clkdev_add(cl); 123*58949aa3SJiaxin Yu 124*58949aa3SJiaxin Yu afe_priv->lookup[i] = cl; 125*58949aa3SJiaxin Yu } 126*58949aa3SJiaxin Yu 127*58949aa3SJiaxin Yu return 0; 128*58949aa3SJiaxin Yu } 129*58949aa3SJiaxin Yu 130*58949aa3SJiaxin Yu void mt8186_audsys_clk_unregister(struct mtk_base_afe *afe) 131*58949aa3SJiaxin Yu { 132*58949aa3SJiaxin Yu struct mt8186_afe_private *afe_priv = afe->platform_priv; 133*58949aa3SJiaxin Yu struct clk *clk; 134*58949aa3SJiaxin Yu struct clk_lookup *cl; 135*58949aa3SJiaxin Yu int i; 136*58949aa3SJiaxin Yu 137*58949aa3SJiaxin Yu if (!afe_priv) 138*58949aa3SJiaxin Yu return; 139*58949aa3SJiaxin Yu 140*58949aa3SJiaxin Yu for (i = 0; i < CLK_AUD_NR_CLK; i++) { 141*58949aa3SJiaxin Yu cl = afe_priv->lookup[i]; 142*58949aa3SJiaxin Yu if (!cl) 143*58949aa3SJiaxin Yu continue; 144*58949aa3SJiaxin Yu 145*58949aa3SJiaxin Yu clk = cl->clk; 146*58949aa3SJiaxin Yu clk_unregister_gate(clk); 147*58949aa3SJiaxin Yu 148*58949aa3SJiaxin Yu clkdev_drop(cl); 149*58949aa3SJiaxin Yu } 150*58949aa3SJiaxin Yu } 151