1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Mediatek ALSA SoC AFE platform driver for 8186 4 // 5 // Copyright (c) 2022 MediaTek Inc. 6 // Author: Jiaxin Yu <jiaxin.yu@mediatek.com> 7 8 #include <linux/delay.h> 9 #include <linux/dma-mapping.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_address.h> 13 #include <linux/of_reserved_mem.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 #include <sound/soc.h> 17 18 #include "../common/mtk-afe-platform-driver.h" 19 #include "../common/mtk-afe-fe-dai.h" 20 21 #include "mt8186-afe-common.h" 22 #include "mt8186-afe-clk.h" 23 #include "mt8186-afe-gpio.h" 24 #include "mt8186-interconnection.h" 25 26 static const struct snd_pcm_hardware mt8186_afe_hardware = { 27 .info = (SNDRV_PCM_INFO_MMAP | 28 SNDRV_PCM_INFO_INTERLEAVED | 29 SNDRV_PCM_INFO_MMAP_VALID), 30 .formats = (SNDRV_PCM_FMTBIT_S16_LE | 31 SNDRV_PCM_FMTBIT_S24_LE | 32 SNDRV_PCM_FMTBIT_S32_LE), 33 .period_bytes_min = 96, 34 .period_bytes_max = 4 * 48 * 1024, 35 .periods_min = 2, 36 .periods_max = 256, 37 .buffer_bytes_max = 4 * 48 * 1024, 38 .fifo_size = 0, 39 }; 40 41 static int mt8186_fe_startup(struct snd_pcm_substream *substream, 42 struct snd_soc_dai *dai) 43 { 44 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 45 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 46 struct snd_pcm_runtime *runtime = substream->runtime; 47 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 48 struct mtk_base_afe_memif *memif = &afe->memif[id]; 49 const struct snd_pcm_hardware *mtk_afe_hardware = afe->mtk_afe_hardware; 50 int ret; 51 52 memif->substream = substream; 53 54 snd_pcm_hw_constraint_step(substream->runtime, 0, 55 SNDRV_PCM_HW_PARAM_BUFFER_BYTES, 16); 56 57 snd_soc_set_runtime_hwparams(substream, mtk_afe_hardware); 58 59 ret = snd_pcm_hw_constraint_integer(runtime, 60 SNDRV_PCM_HW_PARAM_PERIODS); 61 if (ret < 0) { 62 dev_err(afe->dev, "snd_pcm_hw_constraint_integer failed\n"); 63 return ret; 64 } 65 66 /* dynamic allocate irq to memif */ 67 if (memif->irq_usage < 0) { 68 int irq_id = mtk_dynamic_irq_acquire(afe); 69 70 if (irq_id != afe->irqs_size) { 71 /* link */ 72 memif->irq_usage = irq_id; 73 } else { 74 dev_err(afe->dev, "%s() error: no more asys irq\n", 75 __func__); 76 return -EBUSY; 77 } 78 } 79 80 return 0; 81 } 82 83 static void mt8186_fe_shutdown(struct snd_pcm_substream *substream, 84 struct snd_soc_dai *dai) 85 { 86 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 87 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 88 struct mt8186_afe_private *afe_priv = afe->platform_priv; 89 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 90 struct mtk_base_afe_memif *memif = &afe->memif[id]; 91 int irq_id = memif->irq_usage; 92 93 memif->substream = NULL; 94 afe_priv->irq_cnt[id] = 0; 95 afe_priv->xrun_assert[id] = 0; 96 97 if (!memif->const_irq) { 98 mtk_dynamic_irq_release(afe, irq_id); 99 memif->irq_usage = -1; 100 memif->substream = NULL; 101 } 102 } 103 104 static int mt8186_fe_hw_params(struct snd_pcm_substream *substream, 105 struct snd_pcm_hw_params *params, 106 struct snd_soc_dai *dai) 107 { 108 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 109 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 110 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 111 unsigned int channels = params_channels(params); 112 unsigned int rate = params_rate(params); 113 int ret; 114 115 ret = mtk_afe_fe_hw_params(substream, params, dai); 116 if (ret) 117 return ret; 118 119 /* channel merge configuration, enable control is in UL5_IN_MUX */ 120 if (id == MT8186_MEMIF_VUL3) { 121 int update_cnt = 8; 122 unsigned int val = 0; 123 unsigned int mask = 0; 124 int fs_mode = mt8186_rate_transform(afe->dev, rate, id); 125 126 /* set rate, channel, update cnt, disable sgen */ 127 val = fs_mode << CM1_FS_SELECT_SFT | 128 (channels - 1) << CHANNEL_MERGE0_CHNUM_SFT | 129 update_cnt << CHANNEL_MERGE0_UPDATE_CNT_SFT; 130 mask = CM1_FS_SELECT_MASK_SFT | 131 CHANNEL_MERGE0_CHNUM_MASK_SFT | 132 CHANNEL_MERGE0_UPDATE_CNT_MASK_SFT; 133 regmap_update_bits(afe->regmap, AFE_CM1_CON, mask, val); 134 } 135 136 return 0; 137 } 138 139 static int mt8186_fe_hw_free(struct snd_pcm_substream *substream, 140 struct snd_soc_dai *dai) 141 { 142 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 143 int ret; 144 145 ret = mtk_afe_fe_hw_free(substream, dai); 146 if (ret) { 147 dev_err(afe->dev, "%s failed\n", __func__); 148 return ret; 149 } 150 151 return 0; 152 } 153 154 static int mt8186_fe_trigger(struct snd_pcm_substream *substream, int cmd, 155 struct snd_soc_dai *dai) 156 { 157 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 158 struct snd_pcm_runtime * const runtime = substream->runtime; 159 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 160 struct mt8186_afe_private *afe_priv = afe->platform_priv; 161 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 162 struct mtk_base_afe_memif *memif = &afe->memif[id]; 163 int irq_id = memif->irq_usage; 164 struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; 165 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 166 unsigned int rate = runtime->rate; 167 unsigned int counter; 168 int fs; 169 int ret; 170 171 dev_dbg(afe->dev, "%s(), %s cmd %d, irq_id %d\n", 172 __func__, memif->data->name, cmd, irq_id); 173 174 switch (cmd) { 175 case SNDRV_PCM_TRIGGER_START: 176 case SNDRV_PCM_TRIGGER_RESUME: 177 ret = mtk_memif_set_enable(afe, id); 178 if (ret) { 179 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 180 __func__, id, ret); 181 return ret; 182 } 183 184 /* 185 * for small latency record 186 * ul memif need read some data before irq enable 187 */ 188 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 189 ((runtime->period_size * 1000) / rate <= 10)) 190 udelay(300); 191 192 /* set irq counter */ 193 if (afe_priv->irq_cnt[id] > 0) 194 counter = afe_priv->irq_cnt[id]; 195 else 196 counter = runtime->period_size; 197 198 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 199 irq_data->irq_cnt_maskbit 200 << irq_data->irq_cnt_shift, 201 counter << irq_data->irq_cnt_shift); 202 203 /* set irq fs */ 204 fs = afe->irq_fs(substream, runtime->rate); 205 if (fs < 0) 206 return -EINVAL; 207 208 regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 209 irq_data->irq_fs_maskbit 210 << irq_data->irq_fs_shift, 211 fs << irq_data->irq_fs_shift); 212 213 /* enable interrupt */ 214 if (runtime->stop_threshold != ~(0U)) 215 regmap_update_bits(afe->regmap, 216 irq_data->irq_en_reg, 217 1 << irq_data->irq_en_shift, 218 1 << irq_data->irq_en_shift); 219 return 0; 220 case SNDRV_PCM_TRIGGER_STOP: 221 case SNDRV_PCM_TRIGGER_SUSPEND: 222 if (afe_priv->xrun_assert[id] > 0) { 223 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 224 int avail = snd_pcm_capture_avail(runtime); 225 /* alsa can trigger stop/start when occur xrun */ 226 if (avail >= runtime->buffer_size) 227 dev_dbg(afe->dev, "%s(), id %d, xrun assert\n", 228 __func__, id); 229 } 230 } 231 232 ret = mtk_memif_set_disable(afe, id); 233 if (ret) 234 dev_err(afe->dev, "%s(), error, id %d, memif enable, ret %d\n", 235 __func__, id, ret); 236 237 /* disable interrupt */ 238 if (runtime->stop_threshold != ~(0U)) 239 regmap_update_bits(afe->regmap, 240 irq_data->irq_en_reg, 241 1 << irq_data->irq_en_shift, 242 0 << irq_data->irq_en_shift); 243 244 /* clear pending IRQ */ 245 regmap_write(afe->regmap, irq_data->irq_clr_reg, 246 1 << irq_data->irq_clr_shift); 247 return ret; 248 default: 249 return -EINVAL; 250 } 251 } 252 253 static int mt8186_memif_fs(struct snd_pcm_substream *substream, 254 unsigned int rate) 255 { 256 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 257 struct snd_soc_component *component = 258 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 259 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 260 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 261 262 return mt8186_rate_transform(afe->dev, rate, id); 263 } 264 265 static int mt8186_get_dai_fs(struct mtk_base_afe *afe, 266 int dai_id, unsigned int rate) 267 { 268 return mt8186_rate_transform(afe->dev, rate, dai_id); 269 } 270 271 static int mt8186_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 272 { 273 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 274 struct snd_soc_component *component = 275 snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 276 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 277 278 return mt8186_general_rate_transform(afe->dev, rate); 279 } 280 281 static int mt8186_get_memif_pbuf_size(struct snd_pcm_substream *substream) 282 { 283 struct snd_pcm_runtime *runtime = substream->runtime; 284 285 if ((runtime->period_size * 1000) / runtime->rate > 10) 286 return MT8186_MEMIF_PBUF_SIZE_256_BYTES; 287 288 return MT8186_MEMIF_PBUF_SIZE_32_BYTES; 289 } 290 291 static int mt8186_fe_prepare(struct snd_pcm_substream *substream, 292 struct snd_soc_dai *dai) 293 { 294 struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); 295 struct snd_pcm_runtime * const runtime = substream->runtime; 296 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 297 int id = snd_soc_rtd_to_cpu(rtd, 0)->id; 298 struct mtk_base_afe_memif *memif = &afe->memif[id]; 299 int irq_id = memif->irq_usage; 300 struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; 301 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 302 unsigned int counter = runtime->period_size; 303 int fs; 304 int ret; 305 306 ret = mtk_afe_fe_prepare(substream, dai); 307 if (ret) 308 return ret; 309 310 /* set irq counter */ 311 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 312 irq_data->irq_cnt_maskbit 313 << irq_data->irq_cnt_shift, 314 counter << irq_data->irq_cnt_shift); 315 316 /* set irq fs */ 317 fs = afe->irq_fs(substream, runtime->rate); 318 319 if (fs < 0) 320 return -EINVAL; 321 322 regmap_update_bits(afe->regmap, irq_data->irq_fs_reg, 323 irq_data->irq_fs_maskbit 324 << irq_data->irq_fs_shift, 325 fs << irq_data->irq_fs_shift); 326 327 return 0; 328 } 329 330 /* FE DAIs */ 331 static const struct snd_soc_dai_ops mt8186_memif_dai_ops = { 332 .startup = mt8186_fe_startup, 333 .shutdown = mt8186_fe_shutdown, 334 .hw_params = mt8186_fe_hw_params, 335 .hw_free = mt8186_fe_hw_free, 336 .prepare = mt8186_fe_prepare, 337 .trigger = mt8186_fe_trigger, 338 }; 339 340 #define MTK_PCM_RATES (SNDRV_PCM_RATE_8000_48000 |\ 341 SNDRV_PCM_RATE_88200 |\ 342 SNDRV_PCM_RATE_96000 |\ 343 SNDRV_PCM_RATE_176400 |\ 344 SNDRV_PCM_RATE_192000) 345 346 #define MTK_PCM_DAI_RATES (SNDRV_PCM_RATE_8000 |\ 347 SNDRV_PCM_RATE_16000 |\ 348 SNDRV_PCM_RATE_32000 |\ 349 SNDRV_PCM_RATE_48000) 350 351 #define MTK_PCM_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ 352 SNDRV_PCM_FMTBIT_S24_LE |\ 353 SNDRV_PCM_FMTBIT_S32_LE) 354 355 static struct snd_soc_dai_driver mt8186_memif_dai_driver[] = { 356 /* FE DAIs: memory intefaces to CPU */ 357 { 358 .name = "DL1", 359 .id = MT8186_MEMIF_DL1, 360 .playback = { 361 .stream_name = "DL1", 362 .channels_min = 1, 363 .channels_max = 2, 364 .rates = MTK_PCM_RATES, 365 .formats = MTK_PCM_FORMATS, 366 }, 367 .ops = &mt8186_memif_dai_ops, 368 }, 369 { 370 .name = "DL12", 371 .id = MT8186_MEMIF_DL12, 372 .playback = { 373 .stream_name = "DL12", 374 .channels_min = 1, 375 .channels_max = 4, 376 .rates = MTK_PCM_RATES, 377 .formats = MTK_PCM_FORMATS, 378 }, 379 .ops = &mt8186_memif_dai_ops, 380 }, 381 { 382 .name = "DL2", 383 .id = MT8186_MEMIF_DL2, 384 .playback = { 385 .stream_name = "DL2", 386 .channels_min = 1, 387 .channels_max = 2, 388 .rates = MTK_PCM_RATES, 389 .formats = MTK_PCM_FORMATS, 390 }, 391 .ops = &mt8186_memif_dai_ops, 392 }, 393 { 394 .name = "DL3", 395 .id = MT8186_MEMIF_DL3, 396 .playback = { 397 .stream_name = "DL3", 398 .channels_min = 1, 399 .channels_max = 2, 400 .rates = MTK_PCM_RATES, 401 .formats = MTK_PCM_FORMATS, 402 }, 403 .ops = &mt8186_memif_dai_ops, 404 }, 405 { 406 .name = "DL4", 407 .id = MT8186_MEMIF_DL4, 408 .playback = { 409 .stream_name = "DL4", 410 .channels_min = 1, 411 .channels_max = 2, 412 .rates = MTK_PCM_RATES, 413 .formats = MTK_PCM_FORMATS, 414 }, 415 .ops = &mt8186_memif_dai_ops, 416 }, 417 { 418 .name = "DL5", 419 .id = MT8186_MEMIF_DL5, 420 .playback = { 421 .stream_name = "DL5", 422 .channels_min = 1, 423 .channels_max = 2, 424 .rates = MTK_PCM_RATES, 425 .formats = MTK_PCM_FORMATS, 426 }, 427 .ops = &mt8186_memif_dai_ops, 428 }, 429 { 430 .name = "DL6", 431 .id = MT8186_MEMIF_DL6, 432 .playback = { 433 .stream_name = "DL6", 434 .channels_min = 1, 435 .channels_max = 2, 436 .rates = MTK_PCM_RATES, 437 .formats = MTK_PCM_FORMATS, 438 }, 439 .ops = &mt8186_memif_dai_ops, 440 }, 441 { 442 .name = "DL7", 443 .id = MT8186_MEMIF_DL7, 444 .playback = { 445 .stream_name = "DL7", 446 .channels_min = 1, 447 .channels_max = 2, 448 .rates = MTK_PCM_RATES, 449 .formats = MTK_PCM_FORMATS, 450 }, 451 .ops = &mt8186_memif_dai_ops, 452 }, 453 { 454 .name = "DL8", 455 .id = MT8186_MEMIF_DL8, 456 .playback = { 457 .stream_name = "DL8", 458 .channels_min = 1, 459 .channels_max = 2, 460 .rates = MTK_PCM_RATES, 461 .formats = MTK_PCM_FORMATS, 462 }, 463 .ops = &mt8186_memif_dai_ops, 464 }, 465 { 466 .name = "UL1", 467 .id = MT8186_MEMIF_VUL12, 468 .capture = { 469 .stream_name = "UL1", 470 .channels_min = 1, 471 .channels_max = 4, 472 .rates = MTK_PCM_RATES, 473 .formats = MTK_PCM_FORMATS, 474 }, 475 .ops = &mt8186_memif_dai_ops, 476 }, 477 { 478 .name = "UL2", 479 .id = MT8186_MEMIF_AWB, 480 .capture = { 481 .stream_name = "UL2", 482 .channels_min = 1, 483 .channels_max = 2, 484 .rates = MTK_PCM_RATES, 485 .formats = MTK_PCM_FORMATS, 486 }, 487 .ops = &mt8186_memif_dai_ops, 488 }, 489 { 490 .name = "UL3", 491 .id = MT8186_MEMIF_VUL2, 492 .capture = { 493 .stream_name = "UL3", 494 .channels_min = 1, 495 .channels_max = 2, 496 .rates = MTK_PCM_RATES, 497 .formats = MTK_PCM_FORMATS, 498 }, 499 .ops = &mt8186_memif_dai_ops, 500 }, 501 { 502 .name = "UL4", 503 .id = MT8186_MEMIF_AWB2, 504 .capture = { 505 .stream_name = "UL4", 506 .channels_min = 1, 507 .channels_max = 2, 508 .rates = MTK_PCM_RATES, 509 .formats = MTK_PCM_FORMATS, 510 }, 511 .ops = &mt8186_memif_dai_ops, 512 }, 513 { 514 .name = "UL5", 515 .id = MT8186_MEMIF_VUL3, 516 .capture = { 517 .stream_name = "UL5", 518 .channels_min = 1, 519 .channels_max = 12, 520 .rates = MTK_PCM_RATES, 521 .formats = MTK_PCM_FORMATS, 522 }, 523 .ops = &mt8186_memif_dai_ops, 524 }, 525 { 526 .name = "UL6", 527 .id = MT8186_MEMIF_VUL4, 528 .capture = { 529 .stream_name = "UL6", 530 .channels_min = 1, 531 .channels_max = 2, 532 .rates = MTK_PCM_RATES, 533 .formats = MTK_PCM_FORMATS, 534 }, 535 .ops = &mt8186_memif_dai_ops, 536 }, 537 { 538 .name = "UL7", 539 .id = MT8186_MEMIF_VUL5, 540 .capture = { 541 .stream_name = "UL7", 542 .channels_min = 1, 543 .channels_max = 2, 544 .rates = MTK_PCM_RATES, 545 .formats = MTK_PCM_FORMATS, 546 }, 547 .ops = &mt8186_memif_dai_ops, 548 }, 549 { 550 .name = "UL8", 551 .id = MT8186_MEMIF_VUL6, 552 .capture = { 553 .stream_name = "UL8", 554 .channels_min = 1, 555 .channels_max = 2, 556 .rates = MTK_PCM_RATES, 557 .formats = MTK_PCM_FORMATS, 558 }, 559 .ops = &mt8186_memif_dai_ops, 560 } 561 }; 562 563 /* kcontrol */ 564 static int mt8186_irq_cnt1_get(struct snd_kcontrol *kcontrol, 565 struct snd_ctl_elem_value *ucontrol) 566 { 567 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 568 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 569 struct mt8186_afe_private *afe_priv = afe->platform_priv; 570 571 ucontrol->value.integer.value[0] = 572 afe_priv->irq_cnt[MT8186_PRIMARY_MEMIF]; 573 574 return 0; 575 } 576 577 static int mt8186_irq_cnt1_set(struct snd_kcontrol *kcontrol, 578 struct snd_ctl_elem_value *ucontrol) 579 { 580 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 581 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 582 struct mt8186_afe_private *afe_priv = afe->platform_priv; 583 int memif_num = MT8186_PRIMARY_MEMIF; 584 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 585 int irq_id = memif->irq_usage; 586 int irq_cnt = afe_priv->irq_cnt[memif_num]; 587 588 dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n", 589 __func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]); 590 591 if (irq_cnt == ucontrol->value.integer.value[0]) 592 return 0; 593 594 irq_cnt = ucontrol->value.integer.value[0]; 595 afe_priv->irq_cnt[memif_num] = irq_cnt; 596 597 if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) { 598 struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; 599 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 600 601 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 602 irq_data->irq_cnt_maskbit 603 << irq_data->irq_cnt_shift, 604 irq_cnt << irq_data->irq_cnt_shift); 605 } else { 606 dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n", 607 __func__, irq_id); 608 } 609 610 return 1; 611 } 612 613 static int mt8186_irq_cnt2_get(struct snd_kcontrol *kcontrol, 614 struct snd_ctl_elem_value *ucontrol) 615 { 616 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 617 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 618 struct mt8186_afe_private *afe_priv = afe->platform_priv; 619 620 ucontrol->value.integer.value[0] = 621 afe_priv->irq_cnt[MT8186_RECORD_MEMIF]; 622 623 return 0; 624 } 625 626 static int mt8186_irq_cnt2_set(struct snd_kcontrol *kcontrol, 627 struct snd_ctl_elem_value *ucontrol) 628 { 629 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 630 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 631 struct mt8186_afe_private *afe_priv = afe->platform_priv; 632 int memif_num = MT8186_RECORD_MEMIF; 633 struct mtk_base_afe_memif *memif = &afe->memif[memif_num]; 634 int irq_id = memif->irq_usage; 635 int irq_cnt = afe_priv->irq_cnt[memif_num]; 636 637 dev_dbg(afe->dev, "%s(), irq_id %d, irq_cnt = %d, value = %ld\n", 638 __func__, irq_id, irq_cnt, ucontrol->value.integer.value[0]); 639 640 if (irq_cnt == ucontrol->value.integer.value[0]) 641 return 0; 642 643 irq_cnt = ucontrol->value.integer.value[0]; 644 afe_priv->irq_cnt[memif_num] = irq_cnt; 645 646 if (!pm_runtime_status_suspended(afe->dev) && irq_id >= 0) { 647 struct mtk_base_afe_irq *irqs = &afe->irqs[irq_id]; 648 const struct mtk_base_irq_data *irq_data = irqs->irq_data; 649 650 regmap_update_bits(afe->regmap, irq_data->irq_cnt_reg, 651 irq_data->irq_cnt_maskbit 652 << irq_data->irq_cnt_shift, 653 irq_cnt << irq_data->irq_cnt_shift); 654 } else { 655 dev_dbg(afe->dev, "%s(), suspended || irq_id %d, not set\n", 656 __func__, irq_id); 657 } 658 659 return 1; 660 } 661 662 static int mt8186_record_xrun_assert_get(struct snd_kcontrol *kcontrol, 663 struct snd_ctl_elem_value *ucontrol) 664 { 665 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 666 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 667 struct mt8186_afe_private *afe_priv = afe->platform_priv; 668 int xrun_assert = afe_priv->xrun_assert[MT8186_RECORD_MEMIF]; 669 670 ucontrol->value.integer.value[0] = xrun_assert; 671 672 return 0; 673 } 674 675 static int mt8186_record_xrun_assert_set(struct snd_kcontrol *kcontrol, 676 struct snd_ctl_elem_value *ucontrol) 677 { 678 struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol); 679 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(cmpnt); 680 struct mt8186_afe_private *afe_priv = afe->platform_priv; 681 int xrun_assert = ucontrol->value.integer.value[0]; 682 683 dev_dbg(afe->dev, "%s(), xrun_assert %d\n", __func__, xrun_assert); 684 685 if (xrun_assert == afe_priv->xrun_assert[MT8186_RECORD_MEMIF]) 686 return 0; 687 688 afe_priv->xrun_assert[MT8186_RECORD_MEMIF] = xrun_assert; 689 690 return 1; 691 } 692 693 static const struct snd_kcontrol_new mt8186_pcm_kcontrols[] = { 694 SOC_SINGLE_EXT("Audio IRQ1 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0, 695 mt8186_irq_cnt1_get, mt8186_irq_cnt1_set), 696 SOC_SINGLE_EXT("Audio IRQ2 CNT", SND_SOC_NOPM, 0, 0x3ffff, 0, 697 mt8186_irq_cnt2_get, mt8186_irq_cnt2_set), 698 SOC_SINGLE_EXT("record_xrun_assert", SND_SOC_NOPM, 0, 0x1, 0, 699 mt8186_record_xrun_assert_get, 700 mt8186_record_xrun_assert_set), 701 }; 702 703 /* dma widget & routes*/ 704 static const struct snd_kcontrol_new memif_ul1_ch1_mix[] = { 705 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN21, 706 I_ADDA_UL_CH1, 1, 0), 707 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN21, 708 I_ADDA_UL_CH2, 1, 0), 709 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN21, 710 I_ADDA_UL_CH3, 1, 0), 711 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN21_1, 712 I_TDM_IN_CH1, 1, 0), 713 }; 714 715 static const struct snd_kcontrol_new memif_ul1_ch2_mix[] = { 716 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN22, 717 I_ADDA_UL_CH1, 1, 0), 718 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN22, 719 I_ADDA_UL_CH2, 1, 0), 720 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN22, 721 I_ADDA_UL_CH3, 1, 0), 722 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN22, 723 I_ADDA_UL_CH4, 1, 0), 724 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN22_1, 725 I_TDM_IN_CH2, 1, 0), 726 }; 727 728 static const struct snd_kcontrol_new memif_ul1_ch3_mix[] = { 729 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN9, 730 I_ADDA_UL_CH1, 1, 0), 731 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN9, 732 I_ADDA_UL_CH2, 1, 0), 733 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN9, 734 I_ADDA_UL_CH3, 1, 0), 735 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN9_1, 736 I_TDM_IN_CH3, 1, 0), 737 }; 738 739 static const struct snd_kcontrol_new memif_ul1_ch4_mix[] = { 740 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN10, 741 I_ADDA_UL_CH1, 1, 0), 742 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN10, 743 I_ADDA_UL_CH2, 1, 0), 744 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH3 Switch", AFE_CONN10, 745 I_ADDA_UL_CH3, 1, 0), 746 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH4 Switch", AFE_CONN10, 747 I_ADDA_UL_CH4, 1, 0), 748 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN10_1, 749 I_TDM_IN_CH4, 1, 0), 750 }; 751 752 static const struct snd_kcontrol_new memif_ul2_ch1_mix[] = { 753 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN5, 754 I_I2S0_CH1, 1, 0), 755 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN5, 756 I_DL1_CH1, 1, 0), 757 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN5, 758 I_DL12_CH1, 1, 0), 759 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN5, 760 I_DL2_CH1, 1, 0), 761 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN5, 762 I_DL3_CH1, 1, 0), 763 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN5_1, 764 I_DL4_CH1, 1, 0), 765 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN5_1, 766 I_DL5_CH1, 1, 0), 767 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN5_1, 768 I_DL6_CH1, 1, 0), 769 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN5, 770 I_PCM_1_CAP_CH1, 1, 0), 771 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN5, 772 I_I2S2_CH1, 1, 0), 773 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN5_1, 774 I_CONNSYS_I2S_CH1, 1, 0), 775 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH1 Switch", AFE_CONN5_1, 776 I_SRC_1_OUT_CH1, 1, 0), 777 }; 778 779 static const struct snd_kcontrol_new memif_ul2_ch2_mix[] = { 780 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN6, 781 I_I2S0_CH2, 1, 0), 782 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN6, 783 I_DL1_CH2, 1, 0), 784 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN6, 785 I_DL12_CH2, 1, 0), 786 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN6, 787 I_DL2_CH2, 1, 0), 788 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN6, 789 I_DL3_CH2, 1, 0), 790 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN6_1, 791 I_DL4_CH2, 1, 0), 792 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN6_1, 793 I_DL5_CH2, 1, 0), 794 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN6_1, 795 I_DL6_CH2, 1, 0), 796 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN6, 797 I_PCM_1_CAP_CH2, 1, 0), 798 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN6, 799 I_I2S2_CH2, 1, 0), 800 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN6_1, 801 I_CONNSYS_I2S_CH2, 1, 0), 802 SOC_DAPM_SINGLE_AUTODISABLE("SRC_1_OUT_CH2 Switch", AFE_CONN6_1, 803 I_SRC_1_OUT_CH2, 1, 0), 804 }; 805 806 static const struct snd_kcontrol_new memif_ul3_ch1_mix[] = { 807 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH1 Switch", AFE_CONN32_1, 808 I_CONNSYS_I2S_CH1, 1, 0), 809 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN32, 810 I_DL1_CH1, 1, 0), 811 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN32, 812 I_DL2_CH1, 1, 0), 813 }; 814 815 static const struct snd_kcontrol_new memif_ul3_ch2_mix[] = { 816 SOC_DAPM_SINGLE_AUTODISABLE("CONNSYS_I2S_CH2 Switch", AFE_CONN33_1, 817 I_CONNSYS_I2S_CH2, 1, 0), 818 }; 819 820 static const struct snd_kcontrol_new memif_ul4_ch1_mix[] = { 821 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN38, 822 I_ADDA_UL_CH1, 1, 0), 823 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN38, 824 I_I2S0_CH1, 1, 0), 825 }; 826 827 static const struct snd_kcontrol_new memif_ul4_ch2_mix[] = { 828 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN39, 829 I_ADDA_UL_CH2, 1, 0), 830 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN39, 831 I_I2S0_CH2, 1, 0), 832 }; 833 834 static const struct snd_kcontrol_new memif_ul5_ch1_mix[] = { 835 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN44, 836 I_ADDA_UL_CH1, 1, 0), 837 }; 838 839 static const struct snd_kcontrol_new memif_ul5_ch2_mix[] = { 840 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN45, 841 I_ADDA_UL_CH2, 1, 0), 842 }; 843 844 static const struct snd_kcontrol_new memif_ul6_ch1_mix[] = { 845 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN46, 846 I_ADDA_UL_CH1, 1, 0), 847 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN46, 848 I_DL1_CH1, 1, 0), 849 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN46, 850 I_DL12_CH1, 1, 0), 851 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH1 Switch", AFE_CONN46_1, 852 I_DL6_CH1, 1, 0), 853 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN46, 854 I_DL2_CH1, 1, 0), 855 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN46, 856 I_DL3_CH1, 1, 0), 857 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN46_1, 858 I_DL4_CH1, 1, 0), 859 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH1 Switch", AFE_CONN46, 860 I_PCM_1_CAP_CH1, 1, 0), 861 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH1 Switch", AFE_CONN46, 862 I_GAIN1_OUT_CH1, 1, 0), 863 }; 864 865 static const struct snd_kcontrol_new memif_ul6_ch2_mix[] = { 866 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN47, 867 I_ADDA_UL_CH2, 1, 0), 868 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN47, 869 I_DL1_CH2, 1, 0), 870 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN47, 871 I_DL12_CH2, 1, 0), 872 SOC_DAPM_SINGLE_AUTODISABLE("DL6_CH2 Switch", AFE_CONN47_1, 873 I_DL6_CH2, 1, 0), 874 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN47, 875 I_DL2_CH2, 1, 0), 876 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN47, 877 I_DL3_CH2, 1, 0), 878 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN47_1, 879 I_DL4_CH2, 1, 0), 880 SOC_DAPM_SINGLE_AUTODISABLE("PCM_1_CAP_CH2 Switch", AFE_CONN47, 881 I_PCM_1_CAP_CH2, 1, 0), 882 SOC_DAPM_SINGLE_AUTODISABLE("GAIN1_OUT_CH2 Switch", AFE_CONN47, 883 I_GAIN1_OUT_CH2, 1, 0), 884 }; 885 886 static const struct snd_kcontrol_new memif_ul7_ch1_mix[] = { 887 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN48, 888 I_ADDA_UL_CH1, 1, 0), 889 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH1 Switch", AFE_CONN48, 890 I_GAIN2_OUT_CH1, 1, 0), 891 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH1 Switch", AFE_CONN48_1, 892 I_SRC_2_OUT_CH1, 1, 0), 893 }; 894 895 static const struct snd_kcontrol_new memif_ul7_ch2_mix[] = { 896 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN49, 897 I_ADDA_UL_CH2, 1, 0), 898 SOC_DAPM_SINGLE_AUTODISABLE("HW_GAIN2_OUT_CH2 Switch", AFE_CONN49, 899 I_GAIN2_OUT_CH2, 1, 0), 900 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC_2_OUT_CH2 Switch", AFE_CONN49_1, 901 I_SRC_2_OUT_CH2, 1, 0), 902 }; 903 904 static const struct snd_kcontrol_new memif_ul8_ch1_mix[] = { 905 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN50, 906 I_ADDA_UL_CH1, 1, 0), 907 }; 908 909 static const struct snd_kcontrol_new memif_ul8_ch2_mix[] = { 910 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN51, 911 I_ADDA_UL_CH2, 1, 0), 912 }; 913 914 static const struct snd_kcontrol_new hw_cm1_ch1_mix[] = { 915 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH1 Switch", AFE_CONN58_1, 916 I_TDM_IN_CH1, 1, 0), 917 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN58, 918 I_I2S0_CH1, 1, 0), 919 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN58, 920 I_I2S2_CH1, 1, 0), 921 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN58, 922 I_ADDA_UL_CH1, 1, 0), 923 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN58, 924 I_DL1_CH1, 1, 0), 925 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN58, 926 I_DL12_CH1, 1, 0), 927 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN58, 928 I_DL12_CH3, 1, 0), 929 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN58, 930 I_DL2_CH1, 1, 0), 931 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN58, 932 I_DL3_CH1, 1, 0), 933 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN58_1, 934 I_DL4_CH1, 1, 0), 935 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN58_1, 936 I_DL5_CH1, 1, 0), 937 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN58_1, 938 I_SRC_1_OUT_CH1, 1, 0), 939 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN58_1, 940 I_SRC_2_OUT_CH1, 1, 0), 941 }; 942 943 static const struct snd_kcontrol_new hw_cm1_ch2_mix[] = { 944 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH2 Switch", AFE_CONN59_1, 945 I_TDM_IN_CH2, 1, 0), 946 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN59, 947 I_I2S0_CH2, 1, 0), 948 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN59, 949 I_I2S2_CH2, 1, 0), 950 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN59, 951 I_ADDA_UL_CH2, 1, 0), 952 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN59, 953 I_DL1_CH2, 1, 0), 954 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN59, 955 I_DL12_CH2, 1, 0), 956 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN59, 957 I_DL12_CH4, 1, 0), 958 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN59, 959 I_DL2_CH2, 1, 0), 960 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN59, 961 I_DL3_CH2, 1, 0), 962 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN59_1, 963 I_DL4_CH2, 1, 0), 964 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN59_1, 965 I_DL5_CH2, 1, 0), 966 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN59_1, 967 I_SRC_1_OUT_CH2, 1, 0), 968 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN59_1, 969 I_SRC_2_OUT_CH2, 1, 0), 970 }; 971 972 static const struct snd_kcontrol_new hw_cm1_ch3_mix[] = { 973 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH3 Switch", AFE_CONN60_1, 974 I_TDM_IN_CH3, 1, 0), 975 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN60, 976 I_I2S0_CH1, 1, 0), 977 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN60, 978 I_I2S2_CH1, 1, 0), 979 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN60, 980 I_ADDA_UL_CH1, 1, 0), 981 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN60, 982 I_DL1_CH1, 1, 0), 983 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN60, 984 I_DL12_CH1, 1, 0), 985 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN60, 986 I_DL12_CH3, 1, 0), 987 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN60, 988 I_DL2_CH1, 1, 0), 989 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN60, 990 I_DL3_CH1, 1, 0), 991 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN60_1, 992 I_DL4_CH1, 1, 0), 993 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN60_1, 994 I_DL5_CH1, 1, 0), 995 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN60_1, 996 I_SRC_1_OUT_CH1, 1, 0), 997 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN60_1, 998 I_SRC_2_OUT_CH1, 1, 0), 999 }; 1000 1001 static const struct snd_kcontrol_new hw_cm1_ch4_mix[] = { 1002 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH4 Switch", AFE_CONN61_1, 1003 I_TDM_IN_CH4, 1, 0), 1004 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN61, 1005 I_I2S0_CH2, 1, 0), 1006 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN61, 1007 I_I2S2_CH2, 1, 0), 1008 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN61, 1009 I_ADDA_UL_CH2, 1, 0), 1010 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN61, 1011 I_DL1_CH2, 1, 0), 1012 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN61, 1013 I_DL12_CH2, 1, 0), 1014 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN61, 1015 I_DL12_CH4, 1, 0), 1016 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN61, 1017 I_DL2_CH2, 1, 0), 1018 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN61, 1019 I_DL3_CH2, 1, 0), 1020 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN61_1, 1021 I_DL4_CH2, 1, 0), 1022 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN61_1, 1023 I_DL5_CH2, 1, 0), 1024 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN61_1, 1025 I_SRC_1_OUT_CH2, 1, 0), 1026 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN61_1, 1027 I_SRC_2_OUT_CH2, 1, 0), 1028 }; 1029 1030 static const struct snd_kcontrol_new hw_cm1_ch5_mix[] = { 1031 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH5 Switch", AFE_CONN62_1, 1032 I_TDM_IN_CH5, 1, 0), 1033 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN62, 1034 I_I2S0_CH1, 1, 0), 1035 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN62, 1036 I_I2S2_CH1, 1, 0), 1037 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN62, 1038 I_ADDA_UL_CH1, 1, 0), 1039 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN62, 1040 I_DL1_CH1, 1, 0), 1041 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN62, 1042 I_DL12_CH1, 1, 0), 1043 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN62, 1044 I_DL12_CH3, 1, 0), 1045 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN62, 1046 I_DL2_CH1, 1, 0), 1047 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN62, 1048 I_DL3_CH1, 1, 0), 1049 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN62_1, 1050 I_DL4_CH1, 1, 0), 1051 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN62_1, 1052 I_DL5_CH1, 1, 0), 1053 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN62_1, 1054 I_SRC_1_OUT_CH1, 1, 0), 1055 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN62_1, 1056 I_SRC_2_OUT_CH1, 1, 0), 1057 }; 1058 1059 static const struct snd_kcontrol_new hw_cm1_ch6_mix[] = { 1060 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH6 Switch", AFE_CONN63_1, 1061 I_TDM_IN_CH6, 1, 0), 1062 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN63, 1063 I_I2S0_CH2, 1, 0), 1064 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN63, 1065 I_I2S2_CH2, 1, 0), 1066 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN63, 1067 I_ADDA_UL_CH2, 1, 0), 1068 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN63, 1069 I_DL1_CH2, 1, 0), 1070 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN63, 1071 I_DL12_CH2, 1, 0), 1072 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN63, 1073 I_DL12_CH4, 1, 0), 1074 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN63, 1075 I_DL2_CH2, 1, 0), 1076 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN63, 1077 I_DL3_CH2, 1, 0), 1078 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN63_1, 1079 I_DL4_CH2, 1, 0), 1080 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN63_1, 1081 I_DL5_CH2, 1, 0), 1082 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN63_1, 1083 I_SRC_1_OUT_CH2, 1, 0), 1084 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN63_1, 1085 I_SRC_2_OUT_CH2, 1, 0), 1086 }; 1087 1088 static const struct snd_kcontrol_new hw_cm1_ch7_mix[] = { 1089 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH7 Switch", AFE_CONN64_1, 1090 I_TDM_IN_CH7, 1, 0), 1091 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN64, 1092 I_I2S0_CH1, 1, 0), 1093 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN64, 1094 I_I2S2_CH1, 1, 0), 1095 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN64, 1096 I_ADDA_UL_CH1, 1, 0), 1097 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN64, 1098 I_DL1_CH1, 1, 0), 1099 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1v", AFE_CONN64, 1100 I_DL12_CH1, 1, 0), 1101 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN64, 1102 I_DL12_CH3, 1, 0), 1103 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN64, 1104 I_DL2_CH1, 1, 0), 1105 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN64, 1106 I_DL3_CH1, 1, 0), 1107 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN64_1, 1108 I_DL4_CH1, 1, 0), 1109 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN64_1, 1110 I_DL5_CH1, 1, 0), 1111 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN64_1, 1112 I_SRC_1_OUT_CH1, 1, 0), 1113 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN64_1, 1114 I_SRC_2_OUT_CH1, 1, 0), 1115 }; 1116 1117 static const struct snd_kcontrol_new hw_cm1_ch8_mix[] = { 1118 SOC_DAPM_SINGLE_AUTODISABLE("TDM_IN_CH8 Switch", AFE_CONN65_1, 1119 I_TDM_IN_CH8, 1, 0), 1120 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN65, 1121 I_I2S0_CH2, 1, 0), 1122 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN65, 1123 I_I2S2_CH2, 1, 0), 1124 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN65, 1125 I_ADDA_UL_CH2, 1, 0), 1126 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN65, 1127 I_DL1_CH2, 1, 0), 1128 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN65, 1129 I_DL12_CH2, 1, 0), 1130 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN65, 1131 I_DL12_CH4, 1, 0), 1132 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN65, 1133 I_DL2_CH2, 1, 0), 1134 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN65, 1135 I_DL3_CH2, 1, 0), 1136 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN65_1, 1137 I_DL4_CH2, 1, 0), 1138 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN65_1, 1139 I_DL5_CH2, 1, 0), 1140 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN65_1, 1141 I_SRC_1_OUT_CH2, 1, 0), 1142 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN65_1, 1143 I_SRC_2_OUT_CH2, 1, 0), 1144 }; 1145 1146 static const struct snd_kcontrol_new hw_cm1_ch9_mix[] = { 1147 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN66, 1148 I_I2S0_CH1, 1, 0), 1149 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN66, 1150 I_I2S2_CH1, 1, 0), 1151 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN66, 1152 I_ADDA_UL_CH1, 1, 0), 1153 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN66, 1154 I_DL1_CH1, 1, 0), 1155 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN66, 1156 I_DL12_CH1, 1, 0), 1157 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN66, 1158 I_DL12_CH3, 1, 0), 1159 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN66, 1160 I_DL2_CH1, 1, 0), 1161 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN66, 1162 I_DL3_CH1, 1, 0), 1163 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN66_1, 1164 I_DL4_CH1, 1, 0), 1165 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN66_1, 1166 I_DL5_CH1, 1, 0), 1167 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN66_1, 1168 I_SRC_1_OUT_CH1, 1, 0), 1169 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN66_1, 1170 I_SRC_2_OUT_CH1, 1, 0), 1171 }; 1172 1173 static const struct snd_kcontrol_new hw_cm1_ch10_mix[] = { 1174 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN67, 1175 I_I2S0_CH2, 1, 0), 1176 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN67, 1177 I_I2S2_CH2, 1, 0), 1178 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN67, 1179 I_ADDA_UL_CH2, 1, 0), 1180 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN67, 1181 I_DL1_CH2, 1, 0), 1182 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN67, 1183 I_DL12_CH2, 1, 0), 1184 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN67, 1185 I_DL12_CH4, 1, 0), 1186 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN67, 1187 I_DL2_CH2, 1, 0), 1188 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN67, 1189 I_DL3_CH2, 1, 0), 1190 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN67_1, 1191 I_DL4_CH2, 1, 0), 1192 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN67_1, 1193 I_DL5_CH2, 1, 0), 1194 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN67_1, 1195 I_SRC_1_OUT_CH2, 1, 0), 1196 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN67_1, 1197 I_SRC_2_OUT_CH2, 1, 0), 1198 }; 1199 1200 static const struct snd_kcontrol_new hw_cm1_ch11_mix[] = { 1201 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH1 Switch", AFE_CONN68, 1202 I_I2S0_CH1, 1, 0), 1203 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH1 Switch", AFE_CONN68, 1204 I_I2S2_CH1, 1, 0), 1205 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH1 Switch", AFE_CONN68, 1206 I_ADDA_UL_CH1, 1, 0), 1207 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH1 Switch", AFE_CONN68, 1208 I_DL1_CH1, 1, 0), 1209 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH1 Switch", AFE_CONN68, 1210 I_DL12_CH1, 1, 0), 1211 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH3 Switch", AFE_CONN68, 1212 I_DL12_CH3, 1, 0), 1213 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH1 Switch", AFE_CONN68, 1214 I_DL2_CH1, 1, 0), 1215 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH1 Switch", AFE_CONN68, 1216 I_DL3_CH1, 1, 0), 1217 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH1 Switch", AFE_CONN68_1, 1218 I_DL4_CH1, 1, 0), 1219 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH1 Switch", AFE_CONN68_1, 1220 I_DL5_CH1, 1, 0), 1221 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH1 Switch", AFE_CONN68_1, 1222 I_SRC_1_OUT_CH1, 1, 0), 1223 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH1 Switch", AFE_CONN68_1, 1224 I_SRC_2_OUT_CH1, 1, 0), 1225 }; 1226 1227 static const struct snd_kcontrol_new hw_cm1_ch12_mix[] = { 1228 SOC_DAPM_SINGLE_AUTODISABLE("I2S0_CH2 Switch", AFE_CONN69, 1229 I_I2S0_CH2, 1, 0), 1230 SOC_DAPM_SINGLE_AUTODISABLE("I2S2_CH2 Switch", AFE_CONN69, 1231 I_I2S2_CH2, 1, 0), 1232 SOC_DAPM_SINGLE_AUTODISABLE("ADDA_UL_CH2 Switch", AFE_CONN69, 1233 I_ADDA_UL_CH2, 1, 0), 1234 SOC_DAPM_SINGLE_AUTODISABLE("DL1_CH2 Switch", AFE_CONN69, 1235 I_DL1_CH2, 1, 0), 1236 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH2 Switch", AFE_CONN69, 1237 I_DL12_CH2, 1, 0), 1238 SOC_DAPM_SINGLE_AUTODISABLE("DL12_CH4 Switch", AFE_CONN69, 1239 I_DL12_CH4, 1, 0), 1240 SOC_DAPM_SINGLE_AUTODISABLE("DL2_CH2 Switch", AFE_CONN69, 1241 I_DL2_CH2, 1, 0), 1242 SOC_DAPM_SINGLE_AUTODISABLE("DL3_CH2 Switch", AFE_CONN69, 1243 I_DL3_CH2, 1, 0), 1244 SOC_DAPM_SINGLE_AUTODISABLE("DL4_CH2 Switch", AFE_CONN69_1, 1245 I_DL4_CH2, 1, 0), 1246 SOC_DAPM_SINGLE_AUTODISABLE("DL5_CH2 Switch", AFE_CONN69_1, 1247 I_DL5_CH2, 1, 0), 1248 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC1_OUT_CH2 Switch", AFE_CONN69_1, 1249 I_SRC_1_OUT_CH2, 1, 0), 1250 SOC_DAPM_SINGLE_AUTODISABLE("HW_SRC2_OUT_CH2 Switch", AFE_CONN69_1, 1251 I_SRC_2_OUT_CH2, 1, 0), 1252 }; 1253 1254 /* ADDA UL MUX */ 1255 enum { 1256 UL5_IN_MUX_CM1 = 0, 1257 UL5_IN_MUX_NORMAL, 1258 UL5_IN_MUX_MASK = 0x1, 1259 }; 1260 1261 static const char * const ul5_in_mux_map[] = { 1262 "UL5_IN_FROM_CM1", "UL5_IN_FROM_Normal" 1263 }; 1264 1265 static int ul5_in_map_value[] = { 1266 UL5_IN_MUX_CM1, 1267 UL5_IN_MUX_NORMAL, 1268 }; 1269 1270 static SOC_VALUE_ENUM_SINGLE_DECL(ul5_in_mux_map_enum, 1271 AFE_CM1_CON, 1272 VUL3_BYPASS_CM_SFT, 1273 VUL3_BYPASS_CM_MASK, 1274 ul5_in_mux_map, 1275 ul5_in_map_value); 1276 1277 static const struct snd_kcontrol_new ul5_in_mux_control = 1278 SOC_DAPM_ENUM("UL5_IN_MUX Select", ul5_in_mux_map_enum); 1279 1280 static const struct snd_soc_dapm_widget mt8186_memif_widgets[] = { 1281 /* inter-connections */ 1282 SND_SOC_DAPM_MIXER("UL1_CH1", SND_SOC_NOPM, 0, 0, 1283 memif_ul1_ch1_mix, ARRAY_SIZE(memif_ul1_ch1_mix)), 1284 SND_SOC_DAPM_MIXER("UL1_CH2", SND_SOC_NOPM, 0, 0, 1285 memif_ul1_ch2_mix, ARRAY_SIZE(memif_ul1_ch2_mix)), 1286 SND_SOC_DAPM_MIXER("UL1_CH3", SND_SOC_NOPM, 0, 0, 1287 memif_ul1_ch3_mix, ARRAY_SIZE(memif_ul1_ch3_mix)), 1288 SND_SOC_DAPM_MIXER("UL1_CH4", SND_SOC_NOPM, 0, 0, 1289 memif_ul1_ch4_mix, ARRAY_SIZE(memif_ul1_ch4_mix)), 1290 1291 SND_SOC_DAPM_MIXER("UL2_CH1", SND_SOC_NOPM, 0, 0, 1292 memif_ul2_ch1_mix, ARRAY_SIZE(memif_ul2_ch1_mix)), 1293 SND_SOC_DAPM_MIXER("UL2_CH2", SND_SOC_NOPM, 0, 0, 1294 memif_ul2_ch2_mix, ARRAY_SIZE(memif_ul2_ch2_mix)), 1295 1296 SND_SOC_DAPM_MIXER("UL3_CH1", SND_SOC_NOPM, 0, 0, 1297 memif_ul3_ch1_mix, ARRAY_SIZE(memif_ul3_ch1_mix)), 1298 SND_SOC_DAPM_MIXER("UL3_CH2", SND_SOC_NOPM, 0, 0, 1299 memif_ul3_ch2_mix, ARRAY_SIZE(memif_ul3_ch2_mix)), 1300 1301 SND_SOC_DAPM_MIXER("UL4_CH1", SND_SOC_NOPM, 0, 0, 1302 memif_ul4_ch1_mix, ARRAY_SIZE(memif_ul4_ch1_mix)), 1303 SND_SOC_DAPM_MIXER("UL4_CH2", SND_SOC_NOPM, 0, 0, 1304 memif_ul4_ch2_mix, ARRAY_SIZE(memif_ul4_ch2_mix)), 1305 1306 SND_SOC_DAPM_MIXER("UL5_CH1", SND_SOC_NOPM, 0, 0, 1307 memif_ul5_ch1_mix, ARRAY_SIZE(memif_ul5_ch1_mix)), 1308 SND_SOC_DAPM_MIXER("UL5_CH2", SND_SOC_NOPM, 0, 0, 1309 memif_ul5_ch2_mix, ARRAY_SIZE(memif_ul5_ch2_mix)), 1310 1311 SND_SOC_DAPM_MIXER("UL6_CH1", SND_SOC_NOPM, 0, 0, 1312 memif_ul6_ch1_mix, ARRAY_SIZE(memif_ul6_ch1_mix)), 1313 SND_SOC_DAPM_MIXER("UL6_CH2", SND_SOC_NOPM, 0, 0, 1314 memif_ul6_ch2_mix, ARRAY_SIZE(memif_ul6_ch2_mix)), 1315 1316 SND_SOC_DAPM_MIXER("UL7_CH1", SND_SOC_NOPM, 0, 0, 1317 memif_ul7_ch1_mix, ARRAY_SIZE(memif_ul7_ch1_mix)), 1318 SND_SOC_DAPM_MIXER("UL7_CH2", SND_SOC_NOPM, 0, 0, 1319 memif_ul7_ch2_mix, ARRAY_SIZE(memif_ul7_ch2_mix)), 1320 1321 SND_SOC_DAPM_MIXER("UL8_CH1", SND_SOC_NOPM, 0, 0, 1322 memif_ul8_ch1_mix, ARRAY_SIZE(memif_ul8_ch1_mix)), 1323 SND_SOC_DAPM_MIXER("UL8_CH2", SND_SOC_NOPM, 0, 0, 1324 memif_ul8_ch2_mix, ARRAY_SIZE(memif_ul8_ch2_mix)), 1325 1326 SND_SOC_DAPM_MIXER("UL5_2CH", SND_SOC_NOPM, 0, 0, NULL, 0), 1327 1328 SND_SOC_DAPM_MIXER("HW_CM1", SND_SOC_NOPM, 0, 0, NULL, 0), 1329 1330 /* CM1 en*/ 1331 SND_SOC_DAPM_SUPPLY_S("CM1_EN", 0, AFE_CM1_CON, 1332 CHANNEL_MERGE0_EN_SFT, 0, NULL, 1333 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), 1334 1335 SND_SOC_DAPM_MIXER("HW_CM1_CH1", SND_SOC_NOPM, 0, 0, 1336 hw_cm1_ch1_mix, ARRAY_SIZE(hw_cm1_ch1_mix)), 1337 SND_SOC_DAPM_MIXER("HW_CM1_CH2", SND_SOC_NOPM, 0, 0, 1338 hw_cm1_ch2_mix, ARRAY_SIZE(hw_cm1_ch2_mix)), 1339 SND_SOC_DAPM_MIXER("HW_CM1_CH3", SND_SOC_NOPM, 0, 0, 1340 hw_cm1_ch3_mix, ARRAY_SIZE(hw_cm1_ch3_mix)), 1341 SND_SOC_DAPM_MIXER("HW_CM1_CH4", SND_SOC_NOPM, 0, 0, 1342 hw_cm1_ch4_mix, ARRAY_SIZE(hw_cm1_ch4_mix)), 1343 SND_SOC_DAPM_MIXER("HW_CM1_CH5", SND_SOC_NOPM, 0, 0, 1344 hw_cm1_ch5_mix, ARRAY_SIZE(hw_cm1_ch5_mix)), 1345 SND_SOC_DAPM_MIXER("HW_CM1_CH6", SND_SOC_NOPM, 0, 0, 1346 hw_cm1_ch6_mix, ARRAY_SIZE(hw_cm1_ch6_mix)), 1347 SND_SOC_DAPM_MIXER("HW_CM1_CH7", SND_SOC_NOPM, 0, 0, 1348 hw_cm1_ch7_mix, ARRAY_SIZE(hw_cm1_ch7_mix)), 1349 SND_SOC_DAPM_MIXER("HW_CM1_CH8", SND_SOC_NOPM, 0, 0, 1350 hw_cm1_ch8_mix, ARRAY_SIZE(hw_cm1_ch8_mix)), 1351 SND_SOC_DAPM_MIXER("HW_CM1_CH9", SND_SOC_NOPM, 0, 0, 1352 hw_cm1_ch9_mix, ARRAY_SIZE(hw_cm1_ch9_mix)), 1353 SND_SOC_DAPM_MIXER("HW_CM1_CH10", SND_SOC_NOPM, 0, 0, 1354 hw_cm1_ch10_mix, ARRAY_SIZE(hw_cm1_ch10_mix)), 1355 SND_SOC_DAPM_MIXER("HW_CM1_CH11", SND_SOC_NOPM, 0, 0, 1356 hw_cm1_ch11_mix, ARRAY_SIZE(hw_cm1_ch11_mix)), 1357 SND_SOC_DAPM_MIXER("HW_CM1_CH12", SND_SOC_NOPM, 0, 0, 1358 hw_cm1_ch12_mix, ARRAY_SIZE(hw_cm1_ch12_mix)), 1359 1360 SND_SOC_DAPM_MUX("UL5_IN_MUX", SND_SOC_NOPM, 0, 0, 1361 &ul5_in_mux_control), 1362 1363 SND_SOC_DAPM_MIXER("DSP_DL1_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0), 1364 SND_SOC_DAPM_MIXER("DSP_DL2_VIRT", SND_SOC_NOPM, 0, 0, NULL, 0), 1365 1366 SND_SOC_DAPM_INPUT("UL1_VIRTUAL_INPUT"), 1367 SND_SOC_DAPM_INPUT("UL2_VIRTUAL_INPUT"), 1368 SND_SOC_DAPM_INPUT("UL3_VIRTUAL_INPUT"), 1369 SND_SOC_DAPM_INPUT("UL4_VIRTUAL_INPUT"), 1370 SND_SOC_DAPM_INPUT("UL5_VIRTUAL_INPUT"), 1371 SND_SOC_DAPM_INPUT("UL6_VIRTUAL_INPUT"), 1372 }; 1373 1374 static const struct snd_soc_dapm_route mt8186_memif_routes[] = { 1375 {"UL1", NULL, "UL1_CH1"}, 1376 {"UL1", NULL, "UL1_CH2"}, 1377 {"UL1", NULL, "UL1_CH3"}, 1378 {"UL1", NULL, "UL1_CH4"}, 1379 {"UL1_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1380 {"UL1_CH1", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1381 {"UL1_CH2", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1382 {"UL1_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1383 {"UL1_CH3", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1384 {"UL1_CH3", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1385 {"UL1_CH4", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1386 {"UL1_CH4", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1387 {"UL1_CH1", "TDM_IN_CH1 Switch", "TDM IN"}, 1388 {"UL1_CH2", "TDM_IN_CH2 Switch", "TDM IN"}, 1389 {"UL1_CH3", "TDM_IN_CH3 Switch", "TDM IN"}, 1390 {"UL1_CH4", "TDM_IN_CH4 Switch", "TDM IN"}, 1391 1392 {"UL2", NULL, "UL2_CH1"}, 1393 {"UL2", NULL, "UL2_CH2"}, 1394 1395 /* cannot connect FE to FE directly */ 1396 {"UL2_CH1", "DL1_CH1 Switch", "Hostless_UL2 UL"}, 1397 {"UL2_CH2", "DL1_CH2 Switch", "Hostless_UL2 UL"}, 1398 {"UL2_CH1", "DL12_CH1 Switch", "Hostless_UL2 UL"}, 1399 {"UL2_CH2", "DL12_CH2 Switch", "Hostless_UL2 UL"}, 1400 {"UL2_CH1", "DL6_CH1 Switch", "Hostless_UL2 UL"}, 1401 {"UL2_CH2", "DL6_CH2 Switch", "Hostless_UL2 UL"}, 1402 {"UL2_CH1", "DL2_CH1 Switch", "Hostless_UL2 UL"}, 1403 {"UL2_CH2", "DL2_CH2 Switch", "Hostless_UL2 UL"}, 1404 {"UL2_CH1", "DL3_CH1 Switch", "Hostless_UL2 UL"}, 1405 {"UL2_CH2", "DL3_CH2 Switch", "Hostless_UL2 UL"}, 1406 {"UL2_CH1", "DL4_CH1 Switch", "Hostless_UL2 UL"}, 1407 {"UL2_CH2", "DL4_CH2 Switch", "Hostless_UL2 UL"}, 1408 {"UL2_CH1", "DL5_CH1 Switch", "Hostless_UL2 UL"}, 1409 {"UL2_CH2", "DL5_CH2 Switch", "Hostless_UL2 UL"}, 1410 1411 {"Hostless_UL2 UL", NULL, "UL2_VIRTUAL_INPUT"}, 1412 1413 {"UL2_CH1", "I2S0_CH1 Switch", "I2S0"}, 1414 {"UL2_CH2", "I2S0_CH2 Switch", "I2S0"}, 1415 {"UL2_CH1", "I2S2_CH1 Switch", "I2S2"}, 1416 {"UL2_CH2", "I2S2_CH2 Switch", "I2S2"}, 1417 1418 {"UL2_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"}, 1419 {"UL2_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"}, 1420 1421 {"UL2_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"}, 1422 {"UL2_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"}, 1423 1424 {"UL2_CH1", "SRC_1_OUT_CH1 Switch", "HW_SRC_1_Out"}, 1425 {"UL2_CH2", "SRC_1_OUT_CH2 Switch", "HW_SRC_1_Out"}, 1426 1427 {"UL3", NULL, "UL3_CH1"}, 1428 {"UL3", NULL, "UL3_CH2"}, 1429 {"UL3_CH1", "CONNSYS_I2S_CH1 Switch", "Connsys I2S"}, 1430 {"UL3_CH2", "CONNSYS_I2S_CH2 Switch", "Connsys I2S"}, 1431 1432 {"UL4", NULL, "UL4_CH1"}, 1433 {"UL4", NULL, "UL4_CH2"}, 1434 {"UL4_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1435 {"UL4_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1436 {"UL4_CH1", "I2S0_CH1 Switch", "I2S0"}, 1437 {"UL4_CH2", "I2S0_CH2 Switch", "I2S0"}, 1438 1439 {"UL5", NULL, "UL5_IN_MUX"}, 1440 {"UL5_IN_MUX", "UL5_IN_FROM_Normal", "UL5_2CH"}, 1441 {"UL5_IN_MUX", "UL5_IN_FROM_CM1", "HW_CM1"}, 1442 {"UL5_2CH", NULL, "UL5_CH1"}, 1443 {"UL5_2CH", NULL, "UL5_CH2"}, 1444 {"UL5_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1445 {"UL5_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1446 {"HW_CM1", NULL, "CM1_EN"}, 1447 {"HW_CM1", NULL, "HW_CM1_CH1"}, 1448 {"HW_CM1", NULL, "HW_CM1_CH2"}, 1449 {"HW_CM1", NULL, "HW_CM1_CH3"}, 1450 {"HW_CM1", NULL, "HW_CM1_CH4"}, 1451 {"HW_CM1", NULL, "HW_CM1_CH5"}, 1452 {"HW_CM1", NULL, "HW_CM1_CH6"}, 1453 {"HW_CM1", NULL, "HW_CM1_CH7"}, 1454 {"HW_CM1", NULL, "HW_CM1_CH8"}, 1455 {"HW_CM1", NULL, "HW_CM1_CH9"}, 1456 {"HW_CM1", NULL, "HW_CM1_CH10"}, 1457 {"HW_CM1", NULL, "HW_CM1_CH11"}, 1458 {"HW_CM1", NULL, "HW_CM1_CH12"}, 1459 {"HW_CM1_CH1", "TDM_IN_CH1 Switch", "TDM IN"}, 1460 {"HW_CM1_CH2", "TDM_IN_CH2 Switch", "TDM IN"}, 1461 {"HW_CM1_CH3", "TDM_IN_CH3 Switch", "TDM IN"}, 1462 {"HW_CM1_CH4", "TDM_IN_CH4 Switch", "TDM IN"}, 1463 {"HW_CM1_CH5", "TDM_IN_CH5 Switch", "TDM IN"}, 1464 {"HW_CM1_CH6", "TDM_IN_CH6 Switch", "TDM IN"}, 1465 {"HW_CM1_CH7", "TDM_IN_CH7 Switch", "TDM IN"}, 1466 {"HW_CM1_CH8", "TDM_IN_CH8 Switch", "TDM IN"}, 1467 {"HW_CM1_CH9", "DL1_CH1 Switch", "Hostless_UL5 UL"}, 1468 {"HW_CM1_CH10", "DL1_CH2 Switch", "Hostless_UL5 UL"}, 1469 1470 {"HW_CM1_CH3", "DL1_CH1 Switch", "Hostless_UL5 UL"}, 1471 {"HW_CM1_CH4", "DL1_CH2 Switch", "Hostless_UL5 UL"}, 1472 1473 {"HW_CM1_CH3", "DL3_CH1 Switch", "Hostless_UL5 UL"}, 1474 {"HW_CM1_CH4", "DL3_CH2 Switch", "Hostless_UL5 UL"}, 1475 1476 {"HW_CM1_CH5", "HW_SRC1_OUT_CH1 Switch", "HW_SRC_1_Out"}, 1477 {"HW_CM1_CH6", "HW_SRC1_OUT_CH2 Switch", "HW_SRC_1_Out"}, 1478 1479 {"HW_CM1_CH9", "DL12_CH1 Switch", "Hostless_UL5 UL"}, 1480 {"HW_CM1_CH10", "DL12_CH2 Switch", "Hostless_UL5 UL"}, 1481 {"HW_CM1_CH11", "DL12_CH3 Switch", "Hostless_UL5 UL"}, 1482 {"HW_CM1_CH12", "DL12_CH4 Switch", "Hostless_UL5 UL"}, 1483 1484 {"Hostless_UL5 UL", NULL, "UL5_VIRTUAL_INPUT"}, 1485 1486 {"UL6", NULL, "UL6_CH1"}, 1487 {"UL6", NULL, "UL6_CH2"}, 1488 1489 {"UL6_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1490 {"UL6_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1491 {"UL6_CH1", "DL1_CH1 Switch", "Hostless_UL6 UL"}, 1492 {"UL6_CH2", "DL1_CH2 Switch", "Hostless_UL6 UL"}, 1493 {"UL6_CH1", "DL2_CH1 Switch", "Hostless_UL6 UL"}, 1494 {"UL6_CH2", "DL2_CH2 Switch", "Hostless_UL6 UL"}, 1495 {"UL6_CH1", "DL12_CH1 Switch", "Hostless_UL6 UL"}, 1496 {"UL6_CH2", "DL12_CH2 Switch", "Hostless_UL6 UL"}, 1497 {"UL6_CH1", "DL6_CH1 Switch", "Hostless_UL6 UL"}, 1498 {"UL6_CH2", "DL6_CH2 Switch", "Hostless_UL6 UL"}, 1499 {"UL6_CH1", "DL3_CH1 Switch", "Hostless_UL6 UL"}, 1500 {"UL6_CH2", "DL3_CH2 Switch", "Hostless_UL6 UL"}, 1501 {"UL6_CH1", "DL4_CH1 Switch", "Hostless_UL6 UL"}, 1502 {"UL6_CH2", "DL4_CH2 Switch", "Hostless_UL6 UL"}, 1503 {"Hostless_UL6 UL", NULL, "UL6_VIRTUAL_INPUT"}, 1504 {"UL6_CH1", "PCM_1_CAP_CH1 Switch", "PCM 1 Capture"}, 1505 {"UL6_CH2", "PCM_1_CAP_CH2 Switch", "PCM 1 Capture"}, 1506 {"UL6_CH1", "GAIN1_OUT_CH1 Switch", "HW Gain 1 Out"}, 1507 {"UL6_CH2", "GAIN1_OUT_CH2 Switch", "HW Gain 1 Out"}, 1508 1509 {"UL7", NULL, "UL7_CH1"}, 1510 {"UL7", NULL, "UL7_CH2"}, 1511 {"UL7_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1512 {"UL7_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1513 {"UL7_CH1", "HW_GAIN2_OUT_CH1 Switch", "HW Gain 2 Out"}, 1514 {"UL7_CH2", "HW_GAIN2_OUT_CH2 Switch", "HW Gain 2 Out"}, 1515 {"UL7_CH1", "HW_SRC_2_OUT_CH1 Switch", "HW_SRC_2_Out"}, 1516 {"UL7_CH2", "HW_SRC_2_OUT_CH2 Switch", "HW_SRC_2_Out"}, 1517 1518 {"UL8", NULL, "UL8_CH1"}, 1519 {"UL8", NULL, "UL8_CH2"}, 1520 {"UL8_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1521 {"UL8_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1522 1523 {"HW_GAIN2_IN_CH1", "ADDA_UL_CH1 Switch", "ADDA_UL_Mux"}, 1524 {"HW_GAIN2_IN_CH2", "ADDA_UL_CH2 Switch", "ADDA_UL_Mux"}, 1525 }; 1526 1527 static const struct mtk_base_memif_data memif_data[MT8186_MEMIF_NUM] = { 1528 [MT8186_MEMIF_DL1] = { 1529 .name = "DL1", 1530 .id = MT8186_MEMIF_DL1, 1531 .reg_ofs_base = AFE_DL1_BASE, 1532 .reg_ofs_cur = AFE_DL1_CUR, 1533 .reg_ofs_end = AFE_DL1_END, 1534 .reg_ofs_base_msb = AFE_DL1_BASE_MSB, 1535 .reg_ofs_cur_msb = AFE_DL1_CUR_MSB, 1536 .reg_ofs_end_msb = AFE_DL1_END_MSB, 1537 .fs_reg = AFE_DL1_CON0, 1538 .fs_shift = DL1_MODE_SFT, 1539 .fs_maskbit = DL1_MODE_MASK, 1540 .mono_reg = AFE_DL1_CON0, 1541 .mono_shift = DL1_MONO_SFT, 1542 .enable_reg = AFE_DAC_CON0, 1543 .enable_shift = DL1_ON_SFT, 1544 .hd_reg = AFE_DL1_CON0, 1545 .hd_shift = DL1_HD_MODE_SFT, 1546 .hd_align_reg = AFE_DL1_CON0, 1547 .hd_align_mshift = DL1_HALIGN_SFT, 1548 .agent_disable_reg = -1, 1549 .agent_disable_shift = -1, 1550 .msb_reg = -1, 1551 .msb_shift = -1, 1552 .pbuf_reg = AFE_DL1_CON0, 1553 .pbuf_mask = DL1_PBUF_SIZE_MASK, 1554 .pbuf_shift = DL1_PBUF_SIZE_SFT, 1555 .minlen_reg = AFE_DL1_CON0, 1556 .minlen_mask = DL1_MINLEN_MASK, 1557 .minlen_shift = DL1_MINLEN_SFT, 1558 }, 1559 [MT8186_MEMIF_DL12] = { 1560 .name = "DL12", 1561 .id = MT8186_MEMIF_DL12, 1562 .reg_ofs_base = AFE_DL12_BASE, 1563 .reg_ofs_cur = AFE_DL12_CUR, 1564 .reg_ofs_end = AFE_DL12_END, 1565 .reg_ofs_base_msb = AFE_DL12_BASE_MSB, 1566 .reg_ofs_cur_msb = AFE_DL12_CUR_MSB, 1567 .reg_ofs_end_msb = AFE_DL12_END_MSB, 1568 .fs_reg = AFE_DL12_CON0, 1569 .fs_shift = DL12_MODE_SFT, 1570 .fs_maskbit = DL12_MODE_MASK, 1571 .mono_reg = AFE_DL12_CON0, 1572 .mono_shift = DL12_MONO_SFT, 1573 .quad_ch_reg = AFE_DL12_CON0, 1574 .quad_ch_mask = DL12_4CH_EN_MASK, 1575 .quad_ch_shift = DL12_4CH_EN_SFT, 1576 .enable_reg = AFE_DAC_CON0, 1577 .enable_shift = DL12_ON_SFT, 1578 .hd_reg = AFE_DL12_CON0, 1579 .hd_shift = DL12_HD_MODE_SFT, 1580 .hd_align_reg = AFE_DL12_CON0, 1581 .hd_align_mshift = DL12_HALIGN_SFT, 1582 .agent_disable_reg = -1, 1583 .agent_disable_shift = -1, 1584 .msb_reg = -1, 1585 .msb_shift = -1, 1586 .pbuf_reg = AFE_DL12_CON0, 1587 .pbuf_mask = DL12_PBUF_SIZE_MASK, 1588 .pbuf_shift = DL12_PBUF_SIZE_SFT, 1589 .minlen_reg = AFE_DL12_CON0, 1590 .minlen_mask = DL12_MINLEN_MASK, 1591 .minlen_shift = DL12_MINLEN_SFT, 1592 }, 1593 [MT8186_MEMIF_DL2] = { 1594 .name = "DL2", 1595 .id = MT8186_MEMIF_DL2, 1596 .reg_ofs_base = AFE_DL2_BASE, 1597 .reg_ofs_cur = AFE_DL2_CUR, 1598 .reg_ofs_end = AFE_DL2_END, 1599 .reg_ofs_base_msb = AFE_DL2_BASE_MSB, 1600 .reg_ofs_cur_msb = AFE_DL2_CUR_MSB, 1601 .reg_ofs_end_msb = AFE_DL2_END_MSB, 1602 .fs_reg = AFE_DL2_CON0, 1603 .fs_shift = DL2_MODE_SFT, 1604 .fs_maskbit = DL2_MODE_MASK, 1605 .mono_reg = AFE_DL2_CON0, 1606 .mono_shift = DL2_MONO_SFT, 1607 .enable_reg = AFE_DAC_CON0, 1608 .enable_shift = DL2_ON_SFT, 1609 .hd_reg = AFE_DL2_CON0, 1610 .hd_shift = DL2_HD_MODE_SFT, 1611 .hd_align_reg = AFE_DL2_CON0, 1612 .hd_align_mshift = DL2_HALIGN_SFT, 1613 .agent_disable_reg = -1, 1614 .agent_disable_shift = -1, 1615 .msb_reg = -1, 1616 .msb_shift = -1, 1617 .pbuf_reg = AFE_DL2_CON0, 1618 .pbuf_mask = DL2_PBUF_SIZE_MASK, 1619 .pbuf_shift = DL2_PBUF_SIZE_SFT, 1620 .minlen_reg = AFE_DL2_CON0, 1621 .minlen_mask = DL2_MINLEN_MASK, 1622 .minlen_shift = DL2_MINLEN_SFT, 1623 }, 1624 [MT8186_MEMIF_DL3] = { 1625 .name = "DL3", 1626 .id = MT8186_MEMIF_DL3, 1627 .reg_ofs_base = AFE_DL3_BASE, 1628 .reg_ofs_cur = AFE_DL3_CUR, 1629 .reg_ofs_end = AFE_DL3_END, 1630 .reg_ofs_base_msb = AFE_DL3_BASE_MSB, 1631 .reg_ofs_cur_msb = AFE_DL3_CUR_MSB, 1632 .reg_ofs_end_msb = AFE_DL3_END_MSB, 1633 .fs_reg = AFE_DL3_CON0, 1634 .fs_shift = DL3_MODE_SFT, 1635 .fs_maskbit = DL3_MODE_MASK, 1636 .mono_reg = AFE_DL3_CON0, 1637 .mono_shift = DL3_MONO_SFT, 1638 .enable_reg = AFE_DAC_CON0, 1639 .enable_shift = DL3_ON_SFT, 1640 .hd_reg = AFE_DL3_CON0, 1641 .hd_shift = DL3_HD_MODE_SFT, 1642 .hd_align_reg = AFE_DL3_CON0, 1643 .hd_align_mshift = DL3_HALIGN_SFT, 1644 .agent_disable_reg = -1, 1645 .agent_disable_shift = -1, 1646 .msb_reg = -1, 1647 .msb_shift = -1, 1648 .pbuf_reg = AFE_DL3_CON0, 1649 .pbuf_mask = DL3_PBUF_SIZE_MASK, 1650 .pbuf_shift = DL3_PBUF_SIZE_SFT, 1651 .minlen_reg = AFE_DL3_CON0, 1652 .minlen_mask = DL3_MINLEN_MASK, 1653 .minlen_shift = DL3_MINLEN_SFT, 1654 }, 1655 [MT8186_MEMIF_DL4] = { 1656 .name = "DL4", 1657 .id = MT8186_MEMIF_DL4, 1658 .reg_ofs_base = AFE_DL4_BASE, 1659 .reg_ofs_cur = AFE_DL4_CUR, 1660 .reg_ofs_end = AFE_DL4_END, 1661 .reg_ofs_base_msb = AFE_DL4_BASE_MSB, 1662 .reg_ofs_cur_msb = AFE_DL4_CUR_MSB, 1663 .reg_ofs_end_msb = AFE_DL4_END_MSB, 1664 .fs_reg = AFE_DL4_CON0, 1665 .fs_shift = DL4_MODE_SFT, 1666 .fs_maskbit = DL4_MODE_MASK, 1667 .mono_reg = AFE_DL4_CON0, 1668 .mono_shift = DL4_MONO_SFT, 1669 .enable_reg = AFE_DAC_CON0, 1670 .enable_shift = DL4_ON_SFT, 1671 .hd_reg = AFE_DL4_CON0, 1672 .hd_shift = DL4_HD_MODE_SFT, 1673 .hd_align_reg = AFE_DL4_CON0, 1674 .hd_align_mshift = DL4_HALIGN_SFT, 1675 .agent_disable_reg = -1, 1676 .agent_disable_shift = -1, 1677 .msb_reg = -1, 1678 .msb_shift = -1, 1679 .pbuf_reg = AFE_DL4_CON0, 1680 .pbuf_mask = DL4_PBUF_SIZE_MASK, 1681 .pbuf_shift = DL4_PBUF_SIZE_SFT, 1682 .minlen_reg = AFE_DL4_CON0, 1683 .minlen_mask = DL4_MINLEN_MASK, 1684 .minlen_shift = DL4_MINLEN_SFT, 1685 }, 1686 [MT8186_MEMIF_DL5] = { 1687 .name = "DL5", 1688 .id = MT8186_MEMIF_DL5, 1689 .reg_ofs_base = AFE_DL5_BASE, 1690 .reg_ofs_cur = AFE_DL5_CUR, 1691 .reg_ofs_end = AFE_DL5_END, 1692 .reg_ofs_base_msb = AFE_DL5_BASE_MSB, 1693 .reg_ofs_cur_msb = AFE_DL5_CUR_MSB, 1694 .reg_ofs_end_msb = AFE_DL5_END_MSB, 1695 .fs_reg = AFE_DL5_CON0, 1696 .fs_shift = DL5_MODE_SFT, 1697 .fs_maskbit = DL5_MODE_MASK, 1698 .mono_reg = AFE_DL5_CON0, 1699 .mono_shift = DL5_MONO_SFT, 1700 .enable_reg = AFE_DAC_CON0, 1701 .enable_shift = DL5_ON_SFT, 1702 .hd_reg = AFE_DL5_CON0, 1703 .hd_shift = DL5_HD_MODE_SFT, 1704 .hd_align_reg = AFE_DL5_CON0, 1705 .hd_align_mshift = DL5_HALIGN_SFT, 1706 .agent_disable_reg = -1, 1707 .agent_disable_shift = -1, 1708 .msb_reg = -1, 1709 .msb_shift = -1, 1710 .pbuf_reg = AFE_DL5_CON0, 1711 .pbuf_mask = DL5_PBUF_SIZE_MASK, 1712 .pbuf_shift = DL5_PBUF_SIZE_SFT, 1713 .minlen_reg = AFE_DL5_CON0, 1714 .minlen_mask = DL5_MINLEN_MASK, 1715 .minlen_shift = DL5_MINLEN_SFT, 1716 }, 1717 [MT8186_MEMIF_DL6] = { 1718 .name = "DL6", 1719 .id = MT8186_MEMIF_DL6, 1720 .reg_ofs_base = AFE_DL6_BASE, 1721 .reg_ofs_cur = AFE_DL6_CUR, 1722 .reg_ofs_end = AFE_DL6_END, 1723 .reg_ofs_base_msb = AFE_DL6_BASE_MSB, 1724 .reg_ofs_cur_msb = AFE_DL6_CUR_MSB, 1725 .reg_ofs_end_msb = AFE_DL6_END_MSB, 1726 .fs_reg = AFE_DL6_CON0, 1727 .fs_shift = DL6_MODE_SFT, 1728 .fs_maskbit = DL6_MODE_MASK, 1729 .mono_reg = AFE_DL6_CON0, 1730 .mono_shift = DL6_MONO_SFT, 1731 .enable_reg = AFE_DAC_CON0, 1732 .enable_shift = DL6_ON_SFT, 1733 .hd_reg = AFE_DL6_CON0, 1734 .hd_shift = DL6_HD_MODE_SFT, 1735 .hd_align_reg = AFE_DL6_CON0, 1736 .hd_align_mshift = DL6_HALIGN_SFT, 1737 .agent_disable_reg = -1, 1738 .agent_disable_shift = -1, 1739 .msb_reg = -1, 1740 .msb_shift = -1, 1741 .pbuf_reg = AFE_DL6_CON0, 1742 .pbuf_mask = DL6_PBUF_SIZE_MASK, 1743 .pbuf_shift = DL6_PBUF_SIZE_SFT, 1744 .minlen_reg = AFE_DL6_CON0, 1745 .minlen_mask = DL6_MINLEN_MASK, 1746 .minlen_shift = DL6_MINLEN_SFT, 1747 }, 1748 [MT8186_MEMIF_DL7] = { 1749 .name = "DL7", 1750 .id = MT8186_MEMIF_DL7, 1751 .reg_ofs_base = AFE_DL7_BASE, 1752 .reg_ofs_cur = AFE_DL7_CUR, 1753 .reg_ofs_end = AFE_DL7_END, 1754 .reg_ofs_base_msb = AFE_DL7_BASE_MSB, 1755 .reg_ofs_cur_msb = AFE_DL7_CUR_MSB, 1756 .reg_ofs_end_msb = AFE_DL7_END_MSB, 1757 .fs_reg = AFE_DL7_CON0, 1758 .fs_shift = DL7_MODE_SFT, 1759 .fs_maskbit = DL7_MODE_MASK, 1760 .mono_reg = AFE_DL7_CON0, 1761 .mono_shift = DL7_MONO_SFT, 1762 .enable_reg = AFE_DAC_CON0, 1763 .enable_shift = DL7_ON_SFT, 1764 .hd_reg = AFE_DL7_CON0, 1765 .hd_shift = DL7_HD_MODE_SFT, 1766 .hd_align_reg = AFE_DL7_CON0, 1767 .hd_align_mshift = DL7_HALIGN_SFT, 1768 .agent_disable_reg = -1, 1769 .agent_disable_shift = -1, 1770 .msb_reg = -1, 1771 .msb_shift = -1, 1772 .pbuf_reg = AFE_DL7_CON0, 1773 .pbuf_mask = DL7_PBUF_SIZE_MASK, 1774 .pbuf_shift = DL7_PBUF_SIZE_SFT, 1775 .minlen_reg = AFE_DL7_CON0, 1776 .minlen_mask = DL7_MINLEN_MASK, 1777 .minlen_shift = DL7_MINLEN_SFT, 1778 }, 1779 [MT8186_MEMIF_DL8] = { 1780 .name = "DL8", 1781 .id = MT8186_MEMIF_DL8, 1782 .reg_ofs_base = AFE_DL8_BASE, 1783 .reg_ofs_cur = AFE_DL8_CUR, 1784 .reg_ofs_end = AFE_DL8_END, 1785 .reg_ofs_base_msb = AFE_DL8_BASE_MSB, 1786 .reg_ofs_cur_msb = AFE_DL8_CUR_MSB, 1787 .reg_ofs_end_msb = AFE_DL8_END_MSB, 1788 .fs_reg = AFE_DL8_CON0, 1789 .fs_shift = DL8_MODE_SFT, 1790 .fs_maskbit = DL8_MODE_MASK, 1791 .mono_reg = AFE_DL8_CON0, 1792 .mono_shift = DL8_MONO_SFT, 1793 .enable_reg = AFE_DAC_CON0, 1794 .enable_shift = DL8_ON_SFT, 1795 .hd_reg = AFE_DL8_CON0, 1796 .hd_shift = DL8_HD_MODE_SFT, 1797 .hd_align_reg = AFE_DL8_CON0, 1798 .hd_align_mshift = DL8_HALIGN_SFT, 1799 .agent_disable_reg = -1, 1800 .agent_disable_shift = -1, 1801 .msb_reg = -1, 1802 .msb_shift = -1, 1803 .pbuf_reg = AFE_DL8_CON0, 1804 .pbuf_mask = DL8_PBUF_SIZE_MASK, 1805 .pbuf_shift = DL8_PBUF_SIZE_SFT, 1806 .minlen_reg = AFE_DL8_CON0, 1807 .minlen_mask = DL8_MINLEN_MASK, 1808 .minlen_shift = DL8_MINLEN_SFT, 1809 }, 1810 [MT8186_MEMIF_VUL12] = { 1811 .name = "VUL12", 1812 .id = MT8186_MEMIF_VUL12, 1813 .reg_ofs_base = AFE_VUL12_BASE, 1814 .reg_ofs_cur = AFE_VUL12_CUR, 1815 .reg_ofs_end = AFE_VUL12_END, 1816 .reg_ofs_base_msb = AFE_VUL12_BASE_MSB, 1817 .reg_ofs_cur_msb = AFE_VUL12_CUR_MSB, 1818 .reg_ofs_end_msb = AFE_VUL12_END_MSB, 1819 .fs_reg = AFE_VUL12_CON0, 1820 .fs_shift = VUL12_MODE_SFT, 1821 .fs_maskbit = VUL12_MODE_MASK, 1822 .mono_reg = AFE_VUL12_CON0, 1823 .mono_shift = VUL12_MONO_SFT, 1824 .quad_ch_reg = AFE_VUL12_CON0, 1825 .quad_ch_mask = VUL12_4CH_EN_MASK, 1826 .quad_ch_shift = VUL12_4CH_EN_SFT, 1827 .enable_reg = AFE_DAC_CON0, 1828 .enable_shift = VUL12_ON_SFT, 1829 .hd_reg = AFE_VUL12_CON0, 1830 .hd_shift = VUL12_HD_MODE_SFT, 1831 .hd_align_reg = AFE_VUL12_CON0, 1832 .hd_align_mshift = VUL12_HALIGN_SFT, 1833 .agent_disable_reg = -1, 1834 .agent_disable_shift = -1, 1835 .msb_reg = -1, 1836 .msb_shift = -1, 1837 }, 1838 [MT8186_MEMIF_VUL2] = { 1839 .name = "VUL2", 1840 .id = MT8186_MEMIF_VUL2, 1841 .reg_ofs_base = AFE_VUL2_BASE, 1842 .reg_ofs_cur = AFE_VUL2_CUR, 1843 .reg_ofs_end = AFE_VUL2_END, 1844 .reg_ofs_base_msb = AFE_VUL2_BASE_MSB, 1845 .reg_ofs_cur_msb = AFE_VUL2_CUR_MSB, 1846 .reg_ofs_end_msb = AFE_VUL2_END_MSB, 1847 .fs_reg = AFE_VUL2_CON0, 1848 .fs_shift = VUL2_MODE_SFT, 1849 .fs_maskbit = VUL2_MODE_MASK, 1850 .mono_reg = AFE_VUL2_CON0, 1851 .mono_shift = VUL2_MONO_SFT, 1852 .enable_reg = AFE_DAC_CON0, 1853 .enable_shift = VUL2_ON_SFT, 1854 .hd_reg = AFE_VUL2_CON0, 1855 .hd_shift = VUL2_HD_MODE_SFT, 1856 .hd_align_reg = AFE_VUL2_CON0, 1857 .hd_align_mshift = VUL2_HALIGN_SFT, 1858 .agent_disable_reg = -1, 1859 .agent_disable_shift = -1, 1860 .msb_reg = -1, 1861 .msb_shift = -1, 1862 }, 1863 [MT8186_MEMIF_AWB] = { 1864 .name = "AWB", 1865 .id = MT8186_MEMIF_AWB, 1866 .reg_ofs_base = AFE_AWB_BASE, 1867 .reg_ofs_cur = AFE_AWB_CUR, 1868 .reg_ofs_end = AFE_AWB_END, 1869 .reg_ofs_base_msb = AFE_AWB_BASE_MSB, 1870 .reg_ofs_cur_msb = AFE_AWB_CUR_MSB, 1871 .reg_ofs_end_msb = AFE_AWB_END_MSB, 1872 .fs_reg = AFE_AWB_CON0, 1873 .fs_shift = AWB_MODE_SFT, 1874 .fs_maskbit = AWB_MODE_MASK, 1875 .mono_reg = AFE_AWB_CON0, 1876 .mono_shift = AWB_MONO_SFT, 1877 .enable_reg = AFE_DAC_CON0, 1878 .enable_shift = AWB_ON_SFT, 1879 .hd_reg = AFE_AWB_CON0, 1880 .hd_shift = AWB_HD_MODE_SFT, 1881 .hd_align_reg = AFE_AWB_CON0, 1882 .hd_align_mshift = AWB_HALIGN_SFT, 1883 .agent_disable_reg = -1, 1884 .agent_disable_shift = -1, 1885 .msb_reg = -1, 1886 .msb_shift = -1, 1887 }, 1888 [MT8186_MEMIF_AWB2] = { 1889 .name = "AWB2", 1890 .id = MT8186_MEMIF_AWB2, 1891 .reg_ofs_base = AFE_AWB2_BASE, 1892 .reg_ofs_cur = AFE_AWB2_CUR, 1893 .reg_ofs_end = AFE_AWB2_END, 1894 .reg_ofs_base_msb = AFE_AWB2_BASE_MSB, 1895 .reg_ofs_cur_msb = AFE_AWB2_CUR_MSB, 1896 .reg_ofs_end_msb = AFE_AWB2_END_MSB, 1897 .fs_reg = AFE_AWB2_CON0, 1898 .fs_shift = AWB2_MODE_SFT, 1899 .fs_maskbit = AWB2_MODE_MASK, 1900 .mono_reg = AFE_AWB2_CON0, 1901 .mono_shift = AWB2_MONO_SFT, 1902 .enable_reg = AFE_DAC_CON0, 1903 .enable_shift = AWB2_ON_SFT, 1904 .hd_reg = AFE_AWB2_CON0, 1905 .hd_shift = AWB2_HD_MODE_SFT, 1906 .hd_align_reg = AFE_AWB2_CON0, 1907 .hd_align_mshift = AWB2_HALIGN_SFT, 1908 .agent_disable_reg = -1, 1909 .agent_disable_shift = -1, 1910 .msb_reg = -1, 1911 .msb_shift = -1, 1912 }, 1913 [MT8186_MEMIF_VUL3] = { 1914 .name = "VUL3", 1915 .id = MT8186_MEMIF_VUL3, 1916 .reg_ofs_base = AFE_VUL3_BASE, 1917 .reg_ofs_cur = AFE_VUL3_CUR, 1918 .reg_ofs_end = AFE_VUL3_END, 1919 .reg_ofs_base_msb = AFE_VUL3_BASE_MSB, 1920 .reg_ofs_cur_msb = AFE_VUL3_CUR_MSB, 1921 .reg_ofs_end_msb = AFE_VUL3_END_MSB, 1922 .fs_reg = AFE_VUL3_CON0, 1923 .fs_shift = VUL3_MODE_SFT, 1924 .fs_maskbit = VUL3_MODE_MASK, 1925 .mono_reg = AFE_VUL3_CON0, 1926 .mono_shift = VUL3_MONO_SFT, 1927 .enable_reg = AFE_DAC_CON0, 1928 .enable_shift = VUL3_ON_SFT, 1929 .hd_reg = AFE_VUL3_CON0, 1930 .hd_shift = VUL3_HD_MODE_SFT, 1931 .hd_align_reg = AFE_VUL3_CON0, 1932 .hd_align_mshift = VUL3_HALIGN_SFT, 1933 .agent_disable_reg = -1, 1934 .agent_disable_shift = -1, 1935 .msb_reg = -1, 1936 .msb_shift = -1, 1937 }, 1938 [MT8186_MEMIF_VUL4] = { 1939 .name = "VUL4", 1940 .id = MT8186_MEMIF_VUL4, 1941 .reg_ofs_base = AFE_VUL4_BASE, 1942 .reg_ofs_cur = AFE_VUL4_CUR, 1943 .reg_ofs_end = AFE_VUL4_END, 1944 .reg_ofs_base_msb = AFE_VUL4_BASE_MSB, 1945 .reg_ofs_cur_msb = AFE_VUL4_CUR_MSB, 1946 .reg_ofs_end_msb = AFE_VUL4_END_MSB, 1947 .fs_reg = AFE_VUL4_CON0, 1948 .fs_shift = VUL4_MODE_SFT, 1949 .fs_maskbit = VUL4_MODE_MASK, 1950 .mono_reg = AFE_VUL4_CON0, 1951 .mono_shift = VUL4_MONO_SFT, 1952 .enable_reg = AFE_DAC_CON0, 1953 .enable_shift = VUL4_ON_SFT, 1954 .hd_reg = AFE_VUL4_CON0, 1955 .hd_shift = VUL4_HD_MODE_SFT, 1956 .hd_align_reg = AFE_VUL4_CON0, 1957 .hd_align_mshift = VUL4_HALIGN_SFT, 1958 .agent_disable_reg = -1, 1959 .agent_disable_shift = -1, 1960 .msb_reg = -1, 1961 .msb_shift = -1, 1962 }, 1963 [MT8186_MEMIF_VUL5] = { 1964 .name = "VUL5", 1965 .id = MT8186_MEMIF_VUL5, 1966 .reg_ofs_base = AFE_VUL5_BASE, 1967 .reg_ofs_cur = AFE_VUL5_CUR, 1968 .reg_ofs_end = AFE_VUL5_END, 1969 .reg_ofs_base_msb = AFE_VUL5_BASE_MSB, 1970 .reg_ofs_cur_msb = AFE_VUL5_CUR_MSB, 1971 .reg_ofs_end_msb = AFE_VUL5_END_MSB, 1972 .fs_reg = AFE_VUL5_CON0, 1973 .fs_shift = VUL5_MODE_SFT, 1974 .fs_maskbit = VUL5_MODE_MASK, 1975 .mono_reg = AFE_VUL5_CON0, 1976 .mono_shift = VUL5_MONO_SFT, 1977 .enable_reg = AFE_DAC_CON0, 1978 .enable_shift = VUL5_ON_SFT, 1979 .hd_reg = AFE_VUL5_CON0, 1980 .hd_shift = VUL5_HD_MODE_SFT, 1981 .hd_align_reg = AFE_VUL5_CON0, 1982 .hd_align_mshift = VUL5_HALIGN_SFT, 1983 .agent_disable_reg = -1, 1984 .agent_disable_shift = -1, 1985 .msb_reg = -1, 1986 .msb_shift = -1, 1987 }, 1988 [MT8186_MEMIF_VUL6] = { 1989 .name = "VUL6", 1990 .id = MT8186_MEMIF_VUL6, 1991 .reg_ofs_base = AFE_VUL6_BASE, 1992 .reg_ofs_cur = AFE_VUL6_CUR, 1993 .reg_ofs_end = AFE_VUL6_END, 1994 .reg_ofs_base_msb = AFE_VUL6_BASE_MSB, 1995 .reg_ofs_cur_msb = AFE_VUL6_CUR_MSB, 1996 .reg_ofs_end_msb = AFE_VUL6_END_MSB, 1997 .fs_reg = AFE_VUL6_CON0, 1998 .fs_shift = VUL6_MODE_SFT, 1999 .fs_maskbit = VUL6_MODE_MASK, 2000 .mono_reg = AFE_VUL6_CON0, 2001 .mono_shift = VUL6_MONO_SFT, 2002 .enable_reg = AFE_DAC_CON0, 2003 .enable_shift = VUL6_ON_SFT, 2004 .hd_reg = AFE_VUL6_CON0, 2005 .hd_shift = VUL6_HD_MODE_SFT, 2006 .hd_align_reg = AFE_VUL6_CON0, 2007 .hd_align_mshift = VUL6_HALIGN_SFT, 2008 .agent_disable_reg = -1, 2009 .agent_disable_shift = -1, 2010 .msb_reg = -1, 2011 .msb_shift = -1, 2012 }, 2013 }; 2014 2015 static const struct mtk_base_irq_data irq_data[MT8186_IRQ_NUM] = { 2016 [MT8186_IRQ_0] = { 2017 .id = MT8186_IRQ_0, 2018 .irq_cnt_reg = AFE_IRQ_MCU_CNT0, 2019 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2020 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2021 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2022 .irq_fs_shift = IRQ0_MCU_MODE_SFT, 2023 .irq_fs_maskbit = IRQ0_MCU_MODE_MASK, 2024 .irq_en_reg = AFE_IRQ_MCU_CON0, 2025 .irq_en_shift = IRQ0_MCU_ON_SFT, 2026 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2027 .irq_clr_shift = IRQ0_MCU_CLR_SFT, 2028 }, 2029 [MT8186_IRQ_1] = { 2030 .id = MT8186_IRQ_1, 2031 .irq_cnt_reg = AFE_IRQ_MCU_CNT1, 2032 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2033 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2034 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2035 .irq_fs_shift = IRQ1_MCU_MODE_SFT, 2036 .irq_fs_maskbit = IRQ1_MCU_MODE_MASK, 2037 .irq_en_reg = AFE_IRQ_MCU_CON0, 2038 .irq_en_shift = IRQ1_MCU_ON_SFT, 2039 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2040 .irq_clr_shift = IRQ1_MCU_CLR_SFT, 2041 }, 2042 [MT8186_IRQ_2] = { 2043 .id = MT8186_IRQ_2, 2044 .irq_cnt_reg = AFE_IRQ_MCU_CNT2, 2045 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2046 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2047 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2048 .irq_fs_shift = IRQ2_MCU_MODE_SFT, 2049 .irq_fs_maskbit = IRQ2_MCU_MODE_MASK, 2050 .irq_en_reg = AFE_IRQ_MCU_CON0, 2051 .irq_en_shift = IRQ2_MCU_ON_SFT, 2052 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2053 .irq_clr_shift = IRQ2_MCU_CLR_SFT, 2054 }, 2055 [MT8186_IRQ_3] = { 2056 .id = MT8186_IRQ_3, 2057 .irq_cnt_reg = AFE_IRQ_MCU_CNT3, 2058 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2059 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2060 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2061 .irq_fs_shift = IRQ3_MCU_MODE_SFT, 2062 .irq_fs_maskbit = IRQ3_MCU_MODE_MASK, 2063 .irq_en_reg = AFE_IRQ_MCU_CON0, 2064 .irq_en_shift = IRQ3_MCU_ON_SFT, 2065 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2066 .irq_clr_shift = IRQ3_MCU_CLR_SFT, 2067 }, 2068 [MT8186_IRQ_4] = { 2069 .id = MT8186_IRQ_4, 2070 .irq_cnt_reg = AFE_IRQ_MCU_CNT4, 2071 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2072 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2073 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2074 .irq_fs_shift = IRQ4_MCU_MODE_SFT, 2075 .irq_fs_maskbit = IRQ4_MCU_MODE_MASK, 2076 .irq_en_reg = AFE_IRQ_MCU_CON0, 2077 .irq_en_shift = IRQ4_MCU_ON_SFT, 2078 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2079 .irq_clr_shift = IRQ4_MCU_CLR_SFT, 2080 }, 2081 [MT8186_IRQ_5] = { 2082 .id = MT8186_IRQ_5, 2083 .irq_cnt_reg = AFE_IRQ_MCU_CNT5, 2084 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2085 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2086 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2087 .irq_fs_shift = IRQ5_MCU_MODE_SFT, 2088 .irq_fs_maskbit = IRQ5_MCU_MODE_MASK, 2089 .irq_en_reg = AFE_IRQ_MCU_CON0, 2090 .irq_en_shift = IRQ5_MCU_ON_SFT, 2091 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2092 .irq_clr_shift = IRQ5_MCU_CLR_SFT, 2093 }, 2094 [MT8186_IRQ_6] = { 2095 .id = MT8186_IRQ_6, 2096 .irq_cnt_reg = AFE_IRQ_MCU_CNT6, 2097 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2098 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2099 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2100 .irq_fs_shift = IRQ6_MCU_MODE_SFT, 2101 .irq_fs_maskbit = IRQ6_MCU_MODE_MASK, 2102 .irq_en_reg = AFE_IRQ_MCU_CON0, 2103 .irq_en_shift = IRQ6_MCU_ON_SFT, 2104 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2105 .irq_clr_shift = IRQ6_MCU_CLR_SFT, 2106 }, 2107 [MT8186_IRQ_7] = { 2108 .id = MT8186_IRQ_7, 2109 .irq_cnt_reg = AFE_IRQ_MCU_CNT7, 2110 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2111 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2112 .irq_fs_reg = AFE_IRQ_MCU_CON1, 2113 .irq_fs_shift = IRQ7_MCU_MODE_SFT, 2114 .irq_fs_maskbit = IRQ7_MCU_MODE_MASK, 2115 .irq_en_reg = AFE_IRQ_MCU_CON0, 2116 .irq_en_shift = IRQ7_MCU_ON_SFT, 2117 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2118 .irq_clr_shift = IRQ7_MCU_CLR_SFT, 2119 }, 2120 [MT8186_IRQ_8] = { 2121 .id = MT8186_IRQ_8, 2122 .irq_cnt_reg = AFE_IRQ_MCU_CNT8, 2123 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2124 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2125 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2126 .irq_fs_shift = IRQ8_MCU_MODE_SFT, 2127 .irq_fs_maskbit = IRQ8_MCU_MODE_MASK, 2128 .irq_en_reg = AFE_IRQ_MCU_CON0, 2129 .irq_en_shift = IRQ8_MCU_ON_SFT, 2130 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2131 .irq_clr_shift = IRQ8_MCU_CLR_SFT, 2132 }, 2133 [MT8186_IRQ_9] = { 2134 .id = MT8186_IRQ_9, 2135 .irq_cnt_reg = AFE_IRQ_MCU_CNT9, 2136 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2137 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2138 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2139 .irq_fs_shift = IRQ9_MCU_MODE_SFT, 2140 .irq_fs_maskbit = IRQ9_MCU_MODE_MASK, 2141 .irq_en_reg = AFE_IRQ_MCU_CON0, 2142 .irq_en_shift = IRQ9_MCU_ON_SFT, 2143 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2144 .irq_clr_shift = IRQ9_MCU_CLR_SFT, 2145 }, 2146 [MT8186_IRQ_10] = { 2147 .id = MT8186_IRQ_10, 2148 .irq_cnt_reg = AFE_IRQ_MCU_CNT10, 2149 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2150 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2151 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2152 .irq_fs_shift = IRQ10_MCU_MODE_SFT, 2153 .irq_fs_maskbit = IRQ10_MCU_MODE_MASK, 2154 .irq_en_reg = AFE_IRQ_MCU_CON0, 2155 .irq_en_shift = IRQ10_MCU_ON_SFT, 2156 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2157 .irq_clr_shift = IRQ10_MCU_CLR_SFT, 2158 }, 2159 [MT8186_IRQ_11] = { 2160 .id = MT8186_IRQ_11, 2161 .irq_cnt_reg = AFE_IRQ_MCU_CNT11, 2162 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2163 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2164 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2165 .irq_fs_shift = IRQ11_MCU_MODE_SFT, 2166 .irq_fs_maskbit = IRQ11_MCU_MODE_MASK, 2167 .irq_en_reg = AFE_IRQ_MCU_CON0, 2168 .irq_en_shift = IRQ11_MCU_ON_SFT, 2169 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2170 .irq_clr_shift = IRQ11_MCU_CLR_SFT, 2171 }, 2172 [MT8186_IRQ_12] = { 2173 .id = MT8186_IRQ_12, 2174 .irq_cnt_reg = AFE_IRQ_MCU_CNT12, 2175 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2176 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2177 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2178 .irq_fs_shift = IRQ12_MCU_MODE_SFT, 2179 .irq_fs_maskbit = IRQ12_MCU_MODE_MASK, 2180 .irq_en_reg = AFE_IRQ_MCU_CON0, 2181 .irq_en_shift = IRQ12_MCU_ON_SFT, 2182 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2183 .irq_clr_shift = IRQ12_MCU_CLR_SFT, 2184 }, 2185 [MT8186_IRQ_13] = { 2186 .id = MT8186_IRQ_13, 2187 .irq_cnt_reg = AFE_IRQ_MCU_CNT13, 2188 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2189 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2190 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2191 .irq_fs_shift = IRQ13_MCU_MODE_SFT, 2192 .irq_fs_maskbit = IRQ13_MCU_MODE_MASK, 2193 .irq_en_reg = AFE_IRQ_MCU_CON0, 2194 .irq_en_shift = IRQ13_MCU_ON_SFT, 2195 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2196 .irq_clr_shift = IRQ13_MCU_CLR_SFT, 2197 }, 2198 [MT8186_IRQ_14] = { 2199 .id = MT8186_IRQ_14, 2200 .irq_cnt_reg = AFE_IRQ_MCU_CNT14, 2201 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2202 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2203 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2204 .irq_fs_shift = IRQ14_MCU_MODE_SFT, 2205 .irq_fs_maskbit = IRQ14_MCU_MODE_MASK, 2206 .irq_en_reg = AFE_IRQ_MCU_CON0, 2207 .irq_en_shift = IRQ14_MCU_ON_SFT, 2208 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2209 .irq_clr_shift = IRQ14_MCU_CLR_SFT, 2210 }, 2211 [MT8186_IRQ_15] = { 2212 .id = MT8186_IRQ_15, 2213 .irq_cnt_reg = AFE_IRQ_MCU_CNT15, 2214 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2215 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2216 .irq_fs_reg = AFE_IRQ_MCU_CON2, 2217 .irq_fs_shift = IRQ15_MCU_MODE_SFT, 2218 .irq_fs_maskbit = IRQ15_MCU_MODE_MASK, 2219 .irq_en_reg = AFE_IRQ_MCU_CON0, 2220 .irq_en_shift = IRQ15_MCU_ON_SFT, 2221 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2222 .irq_clr_shift = IRQ15_MCU_CLR_SFT, 2223 }, 2224 [MT8186_IRQ_16] = { 2225 .id = MT8186_IRQ_16, 2226 .irq_cnt_reg = AFE_IRQ_MCU_CNT16, 2227 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2228 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2229 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2230 .irq_fs_shift = IRQ16_MCU_MODE_SFT, 2231 .irq_fs_maskbit = IRQ16_MCU_MODE_MASK, 2232 .irq_en_reg = AFE_IRQ_MCU_CON0, 2233 .irq_en_shift = IRQ16_MCU_ON_SFT, 2234 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2235 .irq_clr_shift = IRQ16_MCU_CLR_SFT, 2236 }, 2237 [MT8186_IRQ_17] = { 2238 .id = MT8186_IRQ_17, 2239 .irq_cnt_reg = AFE_IRQ_MCU_CNT17, 2240 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2241 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2242 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2243 .irq_fs_shift = IRQ17_MCU_MODE_SFT, 2244 .irq_fs_maskbit = IRQ17_MCU_MODE_MASK, 2245 .irq_en_reg = AFE_IRQ_MCU_CON0, 2246 .irq_en_shift = IRQ17_MCU_ON_SFT, 2247 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2248 .irq_clr_shift = IRQ17_MCU_CLR_SFT, 2249 }, 2250 [MT8186_IRQ_18] = { 2251 .id = MT8186_IRQ_18, 2252 .irq_cnt_reg = AFE_IRQ_MCU_CNT18, 2253 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2254 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2255 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2256 .irq_fs_shift = IRQ18_MCU_MODE_SFT, 2257 .irq_fs_maskbit = IRQ18_MCU_MODE_MASK, 2258 .irq_en_reg = AFE_IRQ_MCU_CON0, 2259 .irq_en_shift = IRQ18_MCU_ON_SFT, 2260 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2261 .irq_clr_shift = IRQ18_MCU_CLR_SFT, 2262 }, 2263 [MT8186_IRQ_19] = { 2264 .id = MT8186_IRQ_19, 2265 .irq_cnt_reg = AFE_IRQ_MCU_CNT19, 2266 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2267 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2268 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2269 .irq_fs_shift = IRQ19_MCU_MODE_SFT, 2270 .irq_fs_maskbit = IRQ19_MCU_MODE_MASK, 2271 .irq_en_reg = AFE_IRQ_MCU_CON0, 2272 .irq_en_shift = IRQ19_MCU_ON_SFT, 2273 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2274 .irq_clr_shift = IRQ19_MCU_CLR_SFT, 2275 }, 2276 [MT8186_IRQ_20] = { 2277 .id = MT8186_IRQ_20, 2278 .irq_cnt_reg = AFE_IRQ_MCU_CNT20, 2279 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2280 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2281 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2282 .irq_fs_shift = IRQ20_MCU_MODE_SFT, 2283 .irq_fs_maskbit = IRQ20_MCU_MODE_MASK, 2284 .irq_en_reg = AFE_IRQ_MCU_CON0, 2285 .irq_en_shift = IRQ20_MCU_ON_SFT, 2286 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2287 .irq_clr_shift = IRQ20_MCU_CLR_SFT, 2288 }, 2289 [MT8186_IRQ_21] = { 2290 .id = MT8186_IRQ_21, 2291 .irq_cnt_reg = AFE_IRQ_MCU_CNT21, 2292 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2293 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2294 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2295 .irq_fs_shift = IRQ21_MCU_MODE_SFT, 2296 .irq_fs_maskbit = IRQ21_MCU_MODE_MASK, 2297 .irq_en_reg = AFE_IRQ_MCU_CON0, 2298 .irq_en_shift = IRQ21_MCU_ON_SFT, 2299 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2300 .irq_clr_shift = IRQ21_MCU_CLR_SFT, 2301 }, 2302 [MT8186_IRQ_22] = { 2303 .id = MT8186_IRQ_22, 2304 .irq_cnt_reg = AFE_IRQ_MCU_CNT22, 2305 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2306 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2307 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2308 .irq_fs_shift = IRQ22_MCU_MODE_SFT, 2309 .irq_fs_maskbit = IRQ22_MCU_MODE_MASK, 2310 .irq_en_reg = AFE_IRQ_MCU_CON0, 2311 .irq_en_shift = IRQ22_MCU_ON_SFT, 2312 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2313 .irq_clr_shift = IRQ22_MCU_CLR_SFT, 2314 }, 2315 [MT8186_IRQ_23] = { 2316 .id = MT8186_IRQ_23, 2317 .irq_cnt_reg = AFE_IRQ_MCU_CNT23, 2318 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2319 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2320 .irq_fs_reg = AFE_IRQ_MCU_CON3, 2321 .irq_fs_shift = IRQ23_MCU_MODE_SFT, 2322 .irq_fs_maskbit = IRQ23_MCU_MODE_MASK, 2323 .irq_en_reg = AFE_IRQ_MCU_CON0, 2324 .irq_en_shift = IRQ23_MCU_ON_SFT, 2325 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2326 .irq_clr_shift = IRQ23_MCU_CLR_SFT, 2327 }, 2328 [MT8186_IRQ_24] = { 2329 .id = MT8186_IRQ_24, 2330 .irq_cnt_reg = AFE_IRQ_MCU_CNT24, 2331 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2332 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2333 .irq_fs_reg = AFE_IRQ_MCU_CON4, 2334 .irq_fs_shift = IRQ24_MCU_MODE_SFT, 2335 .irq_fs_maskbit = IRQ24_MCU_MODE_MASK, 2336 .irq_en_reg = AFE_IRQ_MCU_CON0, 2337 .irq_en_shift = IRQ24_MCU_ON_SFT, 2338 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2339 .irq_clr_shift = IRQ24_MCU_CLR_SFT, 2340 }, 2341 [MT8186_IRQ_25] = { 2342 .id = MT8186_IRQ_25, 2343 .irq_cnt_reg = AFE_IRQ_MCU_CNT25, 2344 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2345 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2346 .irq_fs_reg = AFE_IRQ_MCU_CON4, 2347 .irq_fs_shift = IRQ25_MCU_MODE_SFT, 2348 .irq_fs_maskbit = IRQ25_MCU_MODE_MASK, 2349 .irq_en_reg = AFE_IRQ_MCU_CON0, 2350 .irq_en_shift = IRQ25_MCU_ON_SFT, 2351 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2352 .irq_clr_shift = IRQ25_MCU_CLR_SFT, 2353 }, 2354 [MT8186_IRQ_26] = { 2355 .id = MT8186_IRQ_26, 2356 .irq_cnt_reg = AFE_IRQ_MCU_CNT26, 2357 .irq_cnt_shift = AFE_IRQ_CNT_SHIFT, 2358 .irq_cnt_maskbit = AFE_IRQ_CNT_MASK, 2359 .irq_fs_reg = AFE_IRQ_MCU_CON4, 2360 .irq_fs_shift = IRQ26_MCU_MODE_SFT, 2361 .irq_fs_maskbit = IRQ26_MCU_MODE_MASK, 2362 .irq_en_reg = AFE_IRQ_MCU_CON0, 2363 .irq_en_shift = IRQ26_MCU_ON_SFT, 2364 .irq_clr_reg = AFE_IRQ_MCU_CLR, 2365 .irq_clr_shift = IRQ26_MCU_CLR_SFT, 2366 }, 2367 }; 2368 2369 static const int memif_irq_usage[MT8186_MEMIF_NUM] = { 2370 /* TODO: verify each memif & irq */ 2371 [MT8186_MEMIF_DL1] = MT8186_IRQ_0, 2372 [MT8186_MEMIF_DL2] = MT8186_IRQ_1, 2373 [MT8186_MEMIF_DL3] = MT8186_IRQ_2, 2374 [MT8186_MEMIF_DL4] = MT8186_IRQ_3, 2375 [MT8186_MEMIF_DL5] = MT8186_IRQ_4, 2376 [MT8186_MEMIF_DL6] = MT8186_IRQ_5, 2377 [MT8186_MEMIF_DL7] = MT8186_IRQ_6, 2378 [MT8186_MEMIF_DL8] = MT8186_IRQ_7, 2379 [MT8186_MEMIF_DL12] = MT8186_IRQ_9, 2380 [MT8186_MEMIF_VUL12] = MT8186_IRQ_10, 2381 [MT8186_MEMIF_VUL2] = MT8186_IRQ_11, 2382 [MT8186_MEMIF_AWB] = MT8186_IRQ_12, 2383 [MT8186_MEMIF_AWB2] = MT8186_IRQ_13, 2384 [MT8186_MEMIF_VUL3] = MT8186_IRQ_14, 2385 [MT8186_MEMIF_VUL4] = MT8186_IRQ_15, 2386 [MT8186_MEMIF_VUL5] = MT8186_IRQ_16, 2387 [MT8186_MEMIF_VUL6] = MT8186_IRQ_17, 2388 }; 2389 2390 static bool mt8186_is_volatile_reg(struct device *dev, unsigned int reg) 2391 { 2392 /* these auto-gen reg has read-only bit, so put it as volatile */ 2393 /* volatile reg cannot be cached, so cannot be set when power off */ 2394 switch (reg) { 2395 case AUDIO_TOP_CON0: /* reg bit controlled by CCF */ 2396 case AUDIO_TOP_CON1: /* reg bit controlled by CCF */ 2397 case AUDIO_TOP_CON2: 2398 case AUDIO_TOP_CON3: 2399 case AFE_DAC_CON0: 2400 case AFE_DL1_CUR_MSB: 2401 case AFE_DL1_CUR: 2402 case AFE_DL1_END: 2403 case AFE_DL2_CUR_MSB: 2404 case AFE_DL2_CUR: 2405 case AFE_DL2_END: 2406 case AFE_DL3_CUR_MSB: 2407 case AFE_DL3_CUR: 2408 case AFE_DL3_END: 2409 case AFE_DL4_CUR_MSB: 2410 case AFE_DL4_CUR: 2411 case AFE_DL4_END: 2412 case AFE_DL12_CUR_MSB: 2413 case AFE_DL12_CUR: 2414 case AFE_DL12_END: 2415 case AFE_ADDA_SRC_DEBUG_MON0: 2416 case AFE_ADDA_SRC_DEBUG_MON1: 2417 case AFE_ADDA_UL_SRC_MON0: 2418 case AFE_ADDA_UL_SRC_MON1: 2419 case AFE_SECURE_CON0: 2420 case AFE_SRAM_BOUND: 2421 case AFE_SECURE_CON1: 2422 case AFE_VUL_CUR_MSB: 2423 case AFE_VUL_CUR: 2424 case AFE_VUL_END: 2425 case AFE_SIDETONE_MON: 2426 case AFE_SIDETONE_CON0: 2427 case AFE_SIDETONE_COEFF: 2428 case AFE_VUL2_CUR_MSB: 2429 case AFE_VUL2_CUR: 2430 case AFE_VUL2_END: 2431 case AFE_VUL3_CUR_MSB: 2432 case AFE_VUL3_CUR: 2433 case AFE_VUL3_END: 2434 case AFE_I2S_MON: 2435 case AFE_DAC_MON: 2436 case AFE_IRQ0_MCU_CNT_MON: 2437 case AFE_IRQ6_MCU_CNT_MON: 2438 case AFE_VUL4_CUR_MSB: 2439 case AFE_VUL4_CUR: 2440 case AFE_VUL4_END: 2441 case AFE_VUL12_CUR_MSB: 2442 case AFE_VUL12_CUR: 2443 case AFE_VUL12_END: 2444 case AFE_IRQ3_MCU_CNT_MON: 2445 case AFE_IRQ4_MCU_CNT_MON: 2446 case AFE_IRQ_MCU_STATUS: 2447 case AFE_IRQ_MCU_CLR: 2448 case AFE_IRQ_MCU_MON2: 2449 case AFE_IRQ1_MCU_CNT_MON: 2450 case AFE_IRQ2_MCU_CNT_MON: 2451 case AFE_IRQ5_MCU_CNT_MON: 2452 case AFE_IRQ7_MCU_CNT_MON: 2453 case AFE_IRQ_MCU_MISS_CLR: 2454 case AFE_GAIN1_CUR: 2455 case AFE_GAIN2_CUR: 2456 case AFE_SRAM_DELSEL_CON1: 2457 case PCM_INTF_CON2: 2458 case FPGA_CFG0: 2459 case FPGA_CFG1: 2460 case FPGA_CFG2: 2461 case FPGA_CFG3: 2462 case AUDIO_TOP_DBG_MON0: 2463 case AUDIO_TOP_DBG_MON1: 2464 case AFE_IRQ8_MCU_CNT_MON: 2465 case AFE_IRQ11_MCU_CNT_MON: 2466 case AFE_IRQ12_MCU_CNT_MON: 2467 case AFE_IRQ9_MCU_CNT_MON: 2468 case AFE_IRQ10_MCU_CNT_MON: 2469 case AFE_IRQ13_MCU_CNT_MON: 2470 case AFE_IRQ14_MCU_CNT_MON: 2471 case AFE_IRQ15_MCU_CNT_MON: 2472 case AFE_IRQ16_MCU_CNT_MON: 2473 case AFE_IRQ17_MCU_CNT_MON: 2474 case AFE_IRQ18_MCU_CNT_MON: 2475 case AFE_IRQ19_MCU_CNT_MON: 2476 case AFE_IRQ20_MCU_CNT_MON: 2477 case AFE_IRQ21_MCU_CNT_MON: 2478 case AFE_IRQ22_MCU_CNT_MON: 2479 case AFE_IRQ23_MCU_CNT_MON: 2480 case AFE_IRQ24_MCU_CNT_MON: 2481 case AFE_IRQ25_MCU_CNT_MON: 2482 case AFE_IRQ26_MCU_CNT_MON: 2483 case AFE_IRQ31_MCU_CNT_MON: 2484 case AFE_CBIP_MON0: 2485 case AFE_CBIP_SLV_MUX_MON0: 2486 case AFE_CBIP_SLV_DECODER_MON0: 2487 case AFE_ADDA6_MTKAIF_MON0: 2488 case AFE_ADDA6_MTKAIF_MON1: 2489 case AFE_AWB_CUR_MSB: 2490 case AFE_AWB_CUR: 2491 case AFE_AWB_END: 2492 case AFE_AWB2_CUR_MSB: 2493 case AFE_AWB2_CUR: 2494 case AFE_AWB2_END: 2495 case AFE_DAI_CUR_MSB: 2496 case AFE_DAI_CUR: 2497 case AFE_DAI_END: 2498 case AFE_DAI2_CUR_MSB: 2499 case AFE_DAI2_CUR: 2500 case AFE_DAI2_END: 2501 case AFE_ADDA6_SRC_DEBUG_MON0: 2502 case AFE_ADD6A_UL_SRC_MON0: 2503 case AFE_ADDA6_UL_SRC_MON1: 2504 case AFE_MOD_DAI_CUR_MSB: 2505 case AFE_MOD_DAI_CUR: 2506 case AFE_MOD_DAI_END: 2507 case AFE_AWB_RCH_MON: 2508 case AFE_AWB_LCH_MON: 2509 case AFE_VUL_RCH_MON: 2510 case AFE_VUL_LCH_MON: 2511 case AFE_VUL12_RCH_MON: 2512 case AFE_VUL12_LCH_MON: 2513 case AFE_VUL2_RCH_MON: 2514 case AFE_VUL2_LCH_MON: 2515 case AFE_DAI_DATA_MON: 2516 case AFE_MOD_DAI_DATA_MON: 2517 case AFE_DAI2_DATA_MON: 2518 case AFE_AWB2_RCH_MON: 2519 case AFE_AWB2_LCH_MON: 2520 case AFE_VUL3_RCH_MON: 2521 case AFE_VUL3_LCH_MON: 2522 case AFE_VUL4_RCH_MON: 2523 case AFE_VUL4_LCH_MON: 2524 case AFE_VUL5_RCH_MON: 2525 case AFE_VUL5_LCH_MON: 2526 case AFE_VUL6_RCH_MON: 2527 case AFE_VUL6_LCH_MON: 2528 case AFE_DL1_RCH_MON: 2529 case AFE_DL1_LCH_MON: 2530 case AFE_DL2_RCH_MON: 2531 case AFE_DL2_LCH_MON: 2532 case AFE_DL12_RCH1_MON: 2533 case AFE_DL12_LCH1_MON: 2534 case AFE_DL12_RCH2_MON: 2535 case AFE_DL12_LCH2_MON: 2536 case AFE_DL3_RCH_MON: 2537 case AFE_DL3_LCH_MON: 2538 case AFE_DL4_RCH_MON: 2539 case AFE_DL4_LCH_MON: 2540 case AFE_DL5_RCH_MON: 2541 case AFE_DL5_LCH_MON: 2542 case AFE_DL6_RCH_MON: 2543 case AFE_DL6_LCH_MON: 2544 case AFE_DL7_RCH_MON: 2545 case AFE_DL7_LCH_MON: 2546 case AFE_DL8_RCH_MON: 2547 case AFE_DL8_LCH_MON: 2548 case AFE_VUL5_CUR_MSB: 2549 case AFE_VUL5_CUR: 2550 case AFE_VUL5_END: 2551 case AFE_VUL6_CUR_MSB: 2552 case AFE_VUL6_CUR: 2553 case AFE_VUL6_END: 2554 case AFE_ADDA_DL_SDM_FIFO_MON: 2555 case AFE_ADDA_DL_SRC_LCH_MON: 2556 case AFE_ADDA_DL_SRC_RCH_MON: 2557 case AFE_ADDA_DL_SDM_OUT_MON: 2558 case AFE_CONNSYS_I2S_MON: 2559 case AFE_ASRC_2CH_CON0: 2560 case AFE_ASRC_2CH_CON2: 2561 case AFE_ASRC_2CH_CON3: 2562 case AFE_ASRC_2CH_CON4: 2563 case AFE_ASRC_2CH_CON5: 2564 case AFE_ASRC_2CH_CON7: 2565 case AFE_ASRC_2CH_CON8: 2566 case AFE_ASRC_2CH_CON12: 2567 case AFE_ASRC_2CH_CON13: 2568 case AFE_ADDA_MTKAIF_MON0: 2569 case AFE_ADDA_MTKAIF_MON1: 2570 case AFE_AUD_PAD_TOP: 2571 case AFE_DL_NLE_R_MON0: 2572 case AFE_DL_NLE_R_MON1: 2573 case AFE_DL_NLE_R_MON2: 2574 case AFE_DL_NLE_L_MON0: 2575 case AFE_DL_NLE_L_MON1: 2576 case AFE_DL_NLE_L_MON2: 2577 case AFE_GENERAL1_ASRC_2CH_CON0: 2578 case AFE_GENERAL1_ASRC_2CH_CON2: 2579 case AFE_GENERAL1_ASRC_2CH_CON3: 2580 case AFE_GENERAL1_ASRC_2CH_CON4: 2581 case AFE_GENERAL1_ASRC_2CH_CON5: 2582 case AFE_GENERAL1_ASRC_2CH_CON7: 2583 case AFE_GENERAL1_ASRC_2CH_CON8: 2584 case AFE_GENERAL1_ASRC_2CH_CON12: 2585 case AFE_GENERAL1_ASRC_2CH_CON13: 2586 case AFE_GENERAL2_ASRC_2CH_CON0: 2587 case AFE_GENERAL2_ASRC_2CH_CON2: 2588 case AFE_GENERAL2_ASRC_2CH_CON3: 2589 case AFE_GENERAL2_ASRC_2CH_CON4: 2590 case AFE_GENERAL2_ASRC_2CH_CON5: 2591 case AFE_GENERAL2_ASRC_2CH_CON7: 2592 case AFE_GENERAL2_ASRC_2CH_CON8: 2593 case AFE_GENERAL2_ASRC_2CH_CON12: 2594 case AFE_GENERAL2_ASRC_2CH_CON13: 2595 case AFE_DL5_CUR_MSB: 2596 case AFE_DL5_CUR: 2597 case AFE_DL5_END: 2598 case AFE_DL6_CUR_MSB: 2599 case AFE_DL6_CUR: 2600 case AFE_DL6_END: 2601 case AFE_DL7_CUR_MSB: 2602 case AFE_DL7_CUR: 2603 case AFE_DL7_END: 2604 case AFE_DL8_CUR_MSB: 2605 case AFE_DL8_CUR: 2606 case AFE_DL8_END: 2607 case AFE_PROT_SIDEBAND_MON: 2608 case AFE_DOMAIN_SIDEBAND0_MON: 2609 case AFE_DOMAIN_SIDEBAND1_MON: 2610 case AFE_DOMAIN_SIDEBAND2_MON: 2611 case AFE_DOMAIN_SIDEBAND3_MON: 2612 case AFE_APLL1_TUNER_CFG: /* [20:31] is monitor */ 2613 case AFE_APLL2_TUNER_CFG: /* [20:31] is monitor */ 2614 return true; 2615 default: 2616 return false; 2617 }; 2618 } 2619 2620 static const struct regmap_config mt8186_afe_regmap_config = { 2621 .reg_bits = 32, 2622 .reg_stride = 4, 2623 .val_bits = 32, 2624 2625 .volatile_reg = mt8186_is_volatile_reg, 2626 2627 .max_register = AFE_MAX_REGISTER, 2628 .num_reg_defaults_raw = AFE_MAX_REGISTER, 2629 2630 .cache_type = REGCACHE_FLAT, 2631 }; 2632 2633 static irqreturn_t mt8186_afe_irq_handler(int irq_id, void *dev) 2634 { 2635 struct mtk_base_afe *afe = dev; 2636 struct mtk_base_afe_irq *irq; 2637 unsigned int status; 2638 unsigned int status_mcu; 2639 unsigned int mcu_en; 2640 int ret; 2641 int i; 2642 2643 /* get irq that is sent to MCU */ 2644 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_EN, &mcu_en); 2645 if (ret) { 2646 dev_err(afe->dev, "%s, get irq direction fail, ret %d", __func__, ret); 2647 return ret; 2648 } 2649 2650 ret = regmap_read(afe->regmap, AFE_IRQ_MCU_STATUS, &status); 2651 /* only care IRQ which is sent to MCU */ 2652 status_mcu = status & mcu_en & AFE_IRQ_STATUS_BITS; 2653 2654 if (ret || status_mcu == 0) { 2655 dev_err(afe->dev, "%s(), irq status err, ret %d, status 0x%x, mcu_en 0x%x\n", 2656 __func__, ret, status, mcu_en); 2657 2658 goto err_irq; 2659 } 2660 2661 for (i = 0; i < MT8186_MEMIF_NUM; i++) { 2662 struct mtk_base_afe_memif *memif = &afe->memif[i]; 2663 2664 if (!memif->substream) 2665 continue; 2666 2667 if (memif->irq_usage < 0) 2668 continue; 2669 2670 irq = &afe->irqs[memif->irq_usage]; 2671 2672 if (status_mcu & (1 << irq->irq_data->irq_en_shift)) 2673 snd_pcm_period_elapsed(memif->substream); 2674 } 2675 2676 err_irq: 2677 /* clear irq */ 2678 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, status_mcu); 2679 2680 return IRQ_HANDLED; 2681 } 2682 2683 static int mt8186_afe_runtime_suspend(struct device *dev) 2684 { 2685 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2686 struct mt8186_afe_private *afe_priv = afe->platform_priv; 2687 unsigned int value = 0; 2688 int ret; 2689 2690 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2691 goto skip_regmap; 2692 2693 /* disable AFE */ 2694 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x0); 2695 2696 ret = regmap_read_poll_timeout(afe->regmap, 2697 AFE_DAC_MON, 2698 value, 2699 (value & AFE_ON_RETM_MASK_SFT) == 0, 2700 20, 2701 1 * 1000 * 1000); 2702 if (ret) { 2703 dev_err(afe->dev, "%s(), ret %d\n", __func__, ret); 2704 return ret; 2705 } 2706 2707 /* make sure all irq status are cleared */ 2708 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff); 2709 regmap_write(afe->regmap, AFE_IRQ_MCU_CLR, 0xffffffff); 2710 2711 /* reset sgen */ 2712 regmap_write(afe->regmap, AFE_SINEGEN_CON0, 0x0); 2713 regmap_update_bits(afe->regmap, AFE_SINEGEN_CON2, 2714 INNER_LOOP_BACK_MODE_MASK_SFT, 2715 0x3f << INNER_LOOP_BACK_MODE_SFT); 2716 2717 /* cache only */ 2718 regcache_cache_only(afe->regmap, true); 2719 regcache_mark_dirty(afe->regmap); 2720 2721 skip_regmap: 2722 mt8186_afe_disable_cgs(afe); 2723 mt8186_afe_disable_clock(afe); 2724 2725 return 0; 2726 } 2727 2728 static int mt8186_afe_runtime_resume(struct device *dev) 2729 { 2730 struct mtk_base_afe *afe = dev_get_drvdata(dev); 2731 struct mt8186_afe_private *afe_priv = afe->platform_priv; 2732 int ret; 2733 2734 ret = mt8186_afe_enable_clock(afe); 2735 if (ret) 2736 return ret; 2737 2738 ret = mt8186_afe_enable_cgs(afe); 2739 if (ret) 2740 return ret; 2741 2742 if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) 2743 goto skip_regmap; 2744 2745 regcache_cache_only(afe->regmap, false); 2746 regcache_sync(afe->regmap); 2747 2748 /* enable audio sys DCM for power saving */ 2749 regmap_update_bits(afe_priv->infracfg, PERI_BUS_DCM_CTRL, BIT(29), BIT(29)); 2750 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, BIT(29), BIT(29)); 2751 2752 /* force cpu use 8_24 format when writing 32bit data */ 2753 regmap_update_bits(afe->regmap, AFE_MEMIF_CON0, CPU_HD_ALIGN_MASK_SFT, 0); 2754 2755 /* set all output port to 24bit */ 2756 regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff); 2757 regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff); 2758 2759 /* enable AFE */ 2760 regmap_update_bits(afe->regmap, AFE_DAC_CON0, AUDIO_AFE_ON_MASK_SFT, BIT(0)); 2761 2762 skip_regmap: 2763 return 0; 2764 } 2765 2766 static int mt8186_afe_component_probe(struct snd_soc_component *component) 2767 { 2768 mtk_afe_add_sub_dai_control(component); 2769 mt8186_add_misc_control(component); 2770 2771 return 0; 2772 } 2773 2774 static const struct snd_soc_component_driver mt8186_afe_component = { 2775 .name = AFE_PCM_NAME, 2776 .pcm_construct = mtk_afe_pcm_new, 2777 .pointer = mtk_afe_pcm_pointer, 2778 .probe = mt8186_afe_component_probe, 2779 }; 2780 2781 static int mt8186_dai_memif_register(struct mtk_base_afe *afe) 2782 { 2783 struct mtk_base_afe_dai *dai; 2784 2785 dai = devm_kzalloc(afe->dev, sizeof(*dai), GFP_KERNEL); 2786 if (!dai) 2787 return -ENOMEM; 2788 2789 list_add(&dai->list, &afe->sub_dais); 2790 2791 dai->dai_drivers = mt8186_memif_dai_driver; 2792 dai->num_dai_drivers = ARRAY_SIZE(mt8186_memif_dai_driver); 2793 2794 dai->controls = mt8186_pcm_kcontrols; 2795 dai->num_controls = ARRAY_SIZE(mt8186_pcm_kcontrols); 2796 dai->dapm_widgets = mt8186_memif_widgets; 2797 dai->num_dapm_widgets = ARRAY_SIZE(mt8186_memif_widgets); 2798 dai->dapm_routes = mt8186_memif_routes; 2799 dai->num_dapm_routes = ARRAY_SIZE(mt8186_memif_routes); 2800 return 0; 2801 } 2802 2803 typedef int (*dai_register_cb)(struct mtk_base_afe *); 2804 static const dai_register_cb dai_register_cbs[] = { 2805 mt8186_dai_adda_register, 2806 mt8186_dai_i2s_register, 2807 mt8186_dai_tdm_register, 2808 mt8186_dai_hw_gain_register, 2809 mt8186_dai_src_register, 2810 mt8186_dai_pcm_register, 2811 mt8186_dai_hostless_register, 2812 mt8186_dai_memif_register, 2813 }; 2814 2815 static int mt8186_afe_pcm_dev_probe(struct platform_device *pdev) 2816 { 2817 struct mtk_base_afe *afe; 2818 struct mt8186_afe_private *afe_priv; 2819 struct reset_control *rstc; 2820 struct device *dev = &pdev->dev; 2821 int i, ret, irq_id; 2822 2823 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34)); 2824 if (ret) 2825 return ret; 2826 2827 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 2828 if (!afe) 2829 return -ENOMEM; 2830 platform_set_drvdata(pdev, afe); 2831 2832 afe->platform_priv = devm_kzalloc(dev, sizeof(*afe_priv), GFP_KERNEL); 2833 if (!afe->platform_priv) 2834 return -ENOMEM; 2835 2836 afe_priv = afe->platform_priv; 2837 afe->dev = &pdev->dev; 2838 2839 ret = of_reserved_mem_device_init(dev); 2840 if (ret) { 2841 dev_info(dev, "no reserved memory found, pre-allocating buffers instead\n"); 2842 afe->preallocate_buffers = true; 2843 } 2844 2845 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 2846 if (IS_ERR(afe->base_addr)) 2847 return PTR_ERR(afe->base_addr); 2848 2849 /* init audio related clock */ 2850 ret = mt8186_init_clock(afe); 2851 if (ret) { 2852 dev_err(dev, "init clock error, ret %d\n", ret); 2853 return ret; 2854 } 2855 2856 /* init memif */ 2857 afe->memif_32bit_supported = 0; 2858 afe->memif_size = MT8186_MEMIF_NUM; 2859 afe->memif = devm_kcalloc(dev, afe->memif_size, sizeof(*afe->memif), GFP_KERNEL); 2860 if (!afe->memif) 2861 return -ENOMEM; 2862 2863 for (i = 0; i < afe->memif_size; i++) { 2864 afe->memif[i].data = &memif_data[i]; 2865 afe->memif[i].irq_usage = memif_irq_usage[i]; 2866 afe->memif[i].const_irq = 1; 2867 } 2868 2869 mutex_init(&afe->irq_alloc_lock); /* needed when dynamic irq */ 2870 2871 /* init irq */ 2872 afe->irqs_size = MT8186_IRQ_NUM; 2873 afe->irqs = devm_kcalloc(dev, afe->irqs_size, sizeof(*afe->irqs), 2874 GFP_KERNEL); 2875 2876 if (!afe->irqs) 2877 return -ENOMEM; 2878 2879 for (i = 0; i < afe->irqs_size; i++) 2880 afe->irqs[i].irq_data = &irq_data[i]; 2881 2882 /* request irq */ 2883 irq_id = platform_get_irq(pdev, 0); 2884 if (irq_id <= 0) 2885 return dev_err_probe(dev, irq_id < 0 ? irq_id : -ENXIO, 2886 "no irq found"); 2887 2888 ret = devm_request_irq(dev, irq_id, mt8186_afe_irq_handler, 2889 IRQF_TRIGGER_NONE, 2890 "Afe_ISR_Handle", (void *)afe); 2891 if (ret) 2892 return dev_err_probe(dev, ret, "could not request_irq for Afe_ISR_Handle\n"); 2893 2894 ret = enable_irq_wake(irq_id); 2895 if (ret < 0) 2896 return dev_err_probe(dev, ret, "enable_irq_wake %d\n", irq_id); 2897 2898 /* init sub_dais */ 2899 INIT_LIST_HEAD(&afe->sub_dais); 2900 2901 for (i = 0; i < ARRAY_SIZE(dai_register_cbs); i++) { 2902 ret = dai_register_cbs[i](afe); 2903 if (ret) 2904 return dev_err_probe(dev, ret, "dai register i %d fail\n", i); 2905 } 2906 2907 /* init dai_driver and component_driver */ 2908 ret = mtk_afe_combine_sub_dai(afe); 2909 if (ret) 2910 return dev_err_probe(dev, ret, "mtk_afe_combine_sub_dai fail\n"); 2911 2912 /* reset controller to reset audio regs before regmap cache */ 2913 rstc = devm_reset_control_get_exclusive(dev, "audiosys"); 2914 if (IS_ERR(rstc)) 2915 return dev_err_probe(dev, PTR_ERR(rstc), "could not get audiosys reset\n"); 2916 2917 ret = reset_control_reset(rstc); 2918 if (ret) 2919 return dev_err_probe(dev, ret, "failed to trigger audio reset\n"); 2920 2921 /* enable clock for regcache get default value from hw */ 2922 afe_priv->pm_runtime_bypass_reg_ctl = true; 2923 2924 ret = devm_pm_runtime_enable(dev); 2925 if (ret) 2926 return ret; 2927 2928 ret = pm_runtime_resume_and_get(dev); 2929 if (ret) 2930 return dev_err_probe(dev, ret, "failed to resume device\n"); 2931 2932 afe->regmap = devm_regmap_init_mmio(dev, afe->base_addr, 2933 &mt8186_afe_regmap_config); 2934 if (IS_ERR(afe->regmap)) { 2935 ret = PTR_ERR(afe->regmap); 2936 goto err_pm_disable; 2937 } 2938 2939 /* others */ 2940 afe->mtk_afe_hardware = &mt8186_afe_hardware; 2941 afe->memif_fs = mt8186_memif_fs; 2942 afe->irq_fs = mt8186_irq_fs; 2943 afe->get_dai_fs = mt8186_get_dai_fs; 2944 afe->get_memif_pbuf_size = mt8186_get_memif_pbuf_size; 2945 2946 afe->runtime_resume = mt8186_afe_runtime_resume; 2947 afe->runtime_suspend = mt8186_afe_runtime_suspend; 2948 2949 /* register platform */ 2950 dev_dbg(dev, "%s(), devm_snd_soc_register_component\n", __func__); 2951 2952 ret = devm_snd_soc_register_component(dev, 2953 &mt8186_afe_component, 2954 afe->dai_drivers, 2955 afe->num_dai_drivers); 2956 if (ret) { 2957 dev_err(dev, "err_dai_component\n"); 2958 goto err_pm_disable; 2959 } 2960 2961 ret = pm_runtime_put_sync(dev); 2962 if (ret) { 2963 pm_runtime_get_noresume(dev); 2964 dev_err(dev, "failed to suspend device: %d\n", ret); 2965 goto err_pm_disable; 2966 } 2967 afe_priv->pm_runtime_bypass_reg_ctl = false; 2968 2969 regcache_cache_only(afe->regmap, true); 2970 regcache_mark_dirty(afe->regmap); 2971 2972 return 0; 2973 2974 err_pm_disable: 2975 pm_runtime_put_noidle(dev); 2976 pm_runtime_set_suspended(dev); 2977 2978 return ret; 2979 } 2980 2981 static const struct of_device_id mt8186_afe_pcm_dt_match[] = { 2982 { .compatible = "mediatek,mt8186-sound", }, 2983 {}, 2984 }; 2985 MODULE_DEVICE_TABLE(of, mt8186_afe_pcm_dt_match); 2986 2987 static const struct dev_pm_ops mt8186_afe_pm_ops = { 2988 RUNTIME_PM_OPS(mt8186_afe_runtime_suspend, 2989 mt8186_afe_runtime_resume, NULL) 2990 }; 2991 2992 static struct platform_driver mt8186_afe_pcm_driver = { 2993 .driver = { 2994 .name = "mt8186-audio", 2995 .of_match_table = mt8186_afe_pcm_dt_match, 2996 .pm = pm_ptr(&mt8186_afe_pm_ops), 2997 }, 2998 .probe = mt8186_afe_pcm_dev_probe, 2999 }; 3000 3001 module_platform_driver(mt8186_afe_pcm_driver); 3002 3003 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver for 8186"); 3004 MODULE_AUTHOR("Jiaxin Yu <jiaxin.yu@mediatek.com>"); 3005 MODULE_LICENSE("GPL v2"); 3006