1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Mediatek 8173 ALSA SoC AFE platform driver 4 * 5 * Copyright (c) 2015 MediaTek Inc. 6 * Author: Koro Chen <koro.chen@mediatek.com> 7 * Sascha Hauer <s.hauer@pengutronix.de> 8 * Hidalgo Huang <hidalgo.huang@mediatek.com> 9 * Ir Lian <ir.lian@mediatek.com> 10 */ 11 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_address.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/pm_runtime.h> 18 #include <sound/soc.h> 19 #include "mt8173-afe-common.h" 20 #include "../common/mtk-base-afe.h" 21 #include "../common/mtk-afe-platform-driver.h" 22 #include "../common/mtk-afe-fe-dai.h" 23 24 /***************************************************************************** 25 * R E G I S T E R D E F I N I T I O N 26 *****************************************************************************/ 27 #define AUDIO_TOP_CON0 0x0000 28 #define AUDIO_TOP_CON1 0x0004 29 #define AFE_DAC_CON0 0x0010 30 #define AFE_DAC_CON1 0x0014 31 #define AFE_I2S_CON1 0x0034 32 #define AFE_I2S_CON2 0x0038 33 #define AFE_CONN_24BIT 0x006c 34 #define AFE_MEMIF_MSB 0x00cc 35 36 #define AFE_CONN1 0x0024 37 #define AFE_CONN2 0x0028 38 #define AFE_CONN3 0x002c 39 #define AFE_CONN7 0x0460 40 #define AFE_CONN8 0x0464 41 #define AFE_HDMI_CONN0 0x0390 42 43 /* Memory interface */ 44 #define AFE_DL1_BASE 0x0040 45 #define AFE_DL1_CUR 0x0044 46 #define AFE_DL1_END 0x0048 47 #define AFE_DL2_BASE 0x0050 48 #define AFE_DL2_CUR 0x0054 49 #define AFE_AWB_BASE 0x0070 50 #define AFE_AWB_CUR 0x007c 51 #define AFE_VUL_BASE 0x0080 52 #define AFE_VUL_CUR 0x008c 53 #define AFE_VUL_END 0x0088 54 #define AFE_DAI_BASE 0x0090 55 #define AFE_DAI_CUR 0x009c 56 #define AFE_MOD_PCM_BASE 0x0330 57 #define AFE_MOD_PCM_CUR 0x033c 58 #define AFE_HDMI_OUT_BASE 0x0374 59 #define AFE_HDMI_OUT_CUR 0x0378 60 #define AFE_HDMI_OUT_END 0x037c 61 62 #define AFE_ADDA_TOP_CON0 0x0120 63 #define AFE_ADDA2_TOP_CON0 0x0600 64 65 #define AFE_HDMI_OUT_CON0 0x0370 66 67 #define AFE_IRQ_MCU_CON 0x03a0 68 #define AFE_IRQ_STATUS 0x03a4 69 #define AFE_IRQ_CLR 0x03a8 70 #define AFE_IRQ_CNT1 0x03ac 71 #define AFE_IRQ_CNT2 0x03b0 72 #define AFE_IRQ_MCU_EN 0x03b4 73 #define AFE_IRQ_CNT5 0x03bc 74 #define AFE_IRQ_CNT7 0x03dc 75 76 #define AFE_TDM_CON1 0x0548 77 #define AFE_TDM_CON2 0x054c 78 79 #define AFE_IRQ_STATUS_BITS 0xff 80 81 /* AUDIO_TOP_CON0 (0x0000) */ 82 #define AUD_TCON0_PDN_SPDF (0x1 << 21) 83 #define AUD_TCON0_PDN_HDMI (0x1 << 20) 84 #define AUD_TCON0_PDN_24M (0x1 << 9) 85 #define AUD_TCON0_PDN_22M (0x1 << 8) 86 #define AUD_TCON0_PDN_AFE (0x1 << 2) 87 88 /* AFE_I2S_CON1 (0x0034) */ 89 #define AFE_I2S_CON1_LOW_JITTER_CLK (0x1 << 12) 90 #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) 91 #define AFE_I2S_CON1_FORMAT_I2S (0x1 << 3) 92 #define AFE_I2S_CON1_EN (0x1 << 0) 93 94 /* AFE_I2S_CON2 (0x0038) */ 95 #define AFE_I2S_CON2_LOW_JITTER_CLK (0x1 << 12) 96 #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) 97 #define AFE_I2S_CON2_FORMAT_I2S (0x1 << 3) 98 #define AFE_I2S_CON2_EN (0x1 << 0) 99 100 /* AFE_CONN_24BIT (0x006c) */ 101 #define AFE_CONN_24BIT_O04 (0x1 << 4) 102 #define AFE_CONN_24BIT_O03 (0x1 << 3) 103 104 /* AFE_HDMI_CONN0 (0x0390) */ 105 #define AFE_HDMI_CONN0_O37_I37 (0x7 << 21) 106 #define AFE_HDMI_CONN0_O36_I36 (0x6 << 18) 107 #define AFE_HDMI_CONN0_O35_I33 (0x3 << 15) 108 #define AFE_HDMI_CONN0_O34_I32 (0x2 << 12) 109 #define AFE_HDMI_CONN0_O33_I35 (0x5 << 9) 110 #define AFE_HDMI_CONN0_O32_I34 (0x4 << 6) 111 #define AFE_HDMI_CONN0_O31_I31 (0x1 << 3) 112 #define AFE_HDMI_CONN0_O30_I30 (0x0 << 0) 113 114 /* AFE_TDM_CON1 (0x0548) */ 115 #define AFE_TDM_CON1_LRCK_WIDTH(x) (((x) - 1) << 24) 116 #define AFE_TDM_CON1_32_BCK_CYCLES (0x2 << 12) 117 #define AFE_TDM_CON1_WLEN_32BIT (0x2 << 8) 118 #define AFE_TDM_CON1_MSB_ALIGNED (0x1 << 4) 119 #define AFE_TDM_CON1_1_BCK_DELAY (0x1 << 3) 120 #define AFE_TDM_CON1_LRCK_INV (0x1 << 2) 121 #define AFE_TDM_CON1_BCK_INV (0x1 << 1) 122 #define AFE_TDM_CON1_EN (0x1 << 0) 123 124 enum afe_tdm_ch_start { 125 AFE_TDM_CH_START_O30_O31 = 0, 126 AFE_TDM_CH_START_O32_O33, 127 AFE_TDM_CH_START_O34_O35, 128 AFE_TDM_CH_START_O36_O37, 129 AFE_TDM_CH_ZERO, 130 }; 131 132 static const unsigned int mt8173_afe_backup_list[] = { 133 AUDIO_TOP_CON0, 134 AFE_CONN1, 135 AFE_CONN2, 136 AFE_CONN7, 137 AFE_CONN8, 138 AFE_DAC_CON1, 139 AFE_DL1_BASE, 140 AFE_DL1_END, 141 AFE_VUL_BASE, 142 AFE_VUL_END, 143 AFE_HDMI_OUT_BASE, 144 AFE_HDMI_OUT_END, 145 AFE_HDMI_CONN0, 146 AFE_DAC_CON0, 147 }; 148 149 struct mt8173_afe_private { 150 struct clk *clocks[MT8173_CLK_NUM]; 151 }; 152 153 static const struct snd_pcm_hardware mt8173_afe_hardware = { 154 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED | 155 SNDRV_PCM_INFO_MMAP_VALID), 156 .buffer_bytes_max = 256 * 1024, 157 .period_bytes_min = 512, 158 .period_bytes_max = 128 * 1024, 159 .periods_min = 2, 160 .periods_max = 256, 161 .fifo_size = 0, 162 }; 163 164 struct mt8173_afe_rate { 165 unsigned int rate; 166 unsigned int regvalue; 167 }; 168 169 static const struct mt8173_afe_rate mt8173_afe_i2s_rates[] = { 170 { .rate = 8000, .regvalue = 0 }, 171 { .rate = 11025, .regvalue = 1 }, 172 { .rate = 12000, .regvalue = 2 }, 173 { .rate = 16000, .regvalue = 4 }, 174 { .rate = 22050, .regvalue = 5 }, 175 { .rate = 24000, .regvalue = 6 }, 176 { .rate = 32000, .regvalue = 8 }, 177 { .rate = 44100, .regvalue = 9 }, 178 { .rate = 48000, .regvalue = 10 }, 179 { .rate = 88000, .regvalue = 11 }, 180 { .rate = 96000, .regvalue = 12 }, 181 { .rate = 174000, .regvalue = 13 }, 182 { .rate = 192000, .regvalue = 14 }, 183 }; 184 185 static int mt8173_afe_i2s_fs(unsigned int sample_rate) 186 { 187 int i; 188 189 for (i = 0; i < ARRAY_SIZE(mt8173_afe_i2s_rates); i++) 190 if (mt8173_afe_i2s_rates[i].rate == sample_rate) 191 return mt8173_afe_i2s_rates[i].regvalue; 192 193 return -EINVAL; 194 } 195 196 static int mt8173_afe_set_i2s(struct mtk_base_afe *afe, unsigned int rate) 197 { 198 unsigned int val; 199 int fs = mt8173_afe_i2s_fs(rate); 200 201 if (fs < 0) 202 return -EINVAL; 203 204 /* from external ADC */ 205 regmap_update_bits(afe->regmap, AFE_ADDA_TOP_CON0, 0x1, 0x1); 206 regmap_update_bits(afe->regmap, AFE_ADDA2_TOP_CON0, 0x1, 0x1); 207 208 /* set input */ 209 val = AFE_I2S_CON2_LOW_JITTER_CLK | 210 AFE_I2S_CON2_RATE(fs) | 211 AFE_I2S_CON2_FORMAT_I2S; 212 213 regmap_update_bits(afe->regmap, AFE_I2S_CON2, ~AFE_I2S_CON2_EN, val); 214 215 /* set output */ 216 val = AFE_I2S_CON1_LOW_JITTER_CLK | 217 AFE_I2S_CON1_RATE(fs) | 218 AFE_I2S_CON1_FORMAT_I2S; 219 220 regmap_update_bits(afe->regmap, AFE_I2S_CON1, ~AFE_I2S_CON1_EN, val); 221 return 0; 222 } 223 224 static void mt8173_afe_set_i2s_enable(struct mtk_base_afe *afe, bool enable) 225 { 226 unsigned int val; 227 228 regmap_read(afe->regmap, AFE_I2S_CON2, &val); 229 if (!!(val & AFE_I2S_CON2_EN) == enable) 230 return; 231 232 /* input */ 233 regmap_update_bits(afe->regmap, AFE_I2S_CON2, 0x1, enable); 234 235 /* output */ 236 regmap_update_bits(afe->regmap, AFE_I2S_CON1, 0x1, enable); 237 } 238 239 static int mt8173_afe_dais_enable_clks(struct mtk_base_afe *afe, 240 struct clk *m_ck, struct clk *b_ck) 241 { 242 int ret; 243 244 if (m_ck) { 245 ret = clk_prepare_enable(m_ck); 246 if (ret) { 247 dev_err(afe->dev, "Failed to enable m_ck\n"); 248 return ret; 249 } 250 } 251 252 if (b_ck) { 253 ret = clk_prepare_enable(b_ck); 254 if (ret) { 255 dev_err(afe->dev, "Failed to enable b_ck\n"); 256 return ret; 257 } 258 } 259 return 0; 260 } 261 262 static int mt8173_afe_dais_set_clks(struct mtk_base_afe *afe, 263 struct clk *m_ck, unsigned int mck_rate, 264 struct clk *b_ck, unsigned int bck_rate) 265 { 266 int ret; 267 268 if (m_ck) { 269 ret = clk_set_rate(m_ck, mck_rate); 270 if (ret) { 271 dev_err(afe->dev, "Failed to set m_ck rate\n"); 272 return ret; 273 } 274 } 275 276 if (b_ck) { 277 ret = clk_set_rate(b_ck, bck_rate); 278 if (ret) { 279 dev_err(afe->dev, "Failed to set b_ck rate\n"); 280 return ret; 281 } 282 } 283 return 0; 284 } 285 286 static void mt8173_afe_dais_disable_clks(struct mtk_base_afe *afe, 287 struct clk *m_ck, struct clk *b_ck) 288 { 289 clk_disable_unprepare(m_ck); 290 clk_disable_unprepare(b_ck); 291 } 292 293 static int mt8173_afe_i2s_startup(struct snd_pcm_substream *substream, 294 struct snd_soc_dai *dai) 295 { 296 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 297 298 if (snd_soc_dai_active(dai)) 299 return 0; 300 301 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 302 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 0); 303 return 0; 304 } 305 306 static void mt8173_afe_i2s_shutdown(struct snd_pcm_substream *substream, 307 struct snd_soc_dai *dai) 308 { 309 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 310 311 if (snd_soc_dai_active(dai)) 312 return; 313 314 mt8173_afe_set_i2s_enable(afe, false); 315 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 316 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M, 317 AUD_TCON0_PDN_22M | AUD_TCON0_PDN_24M); 318 } 319 320 static int mt8173_afe_i2s_prepare(struct snd_pcm_substream *substream, 321 struct snd_soc_dai *dai) 322 { 323 struct snd_pcm_runtime * const runtime = substream->runtime; 324 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 325 struct mt8173_afe_private *afe_priv = afe->platform_priv; 326 int ret; 327 328 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S1_M], 329 runtime->rate * 256, NULL, 0); 330 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S2_M], 331 runtime->rate * 256, NULL, 0); 332 /* config I2S */ 333 ret = mt8173_afe_set_i2s(afe, substream->runtime->rate); 334 if (ret) 335 return ret; 336 337 mt8173_afe_set_i2s_enable(afe, true); 338 339 return 0; 340 } 341 342 static int mt8173_afe_hdmi_startup(struct snd_pcm_substream *substream, 343 struct snd_soc_dai *dai) 344 { 345 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 346 struct mt8173_afe_private *afe_priv = afe->platform_priv; 347 348 if (snd_soc_dai_active(dai)) 349 return 0; 350 351 mt8173_afe_dais_enable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 352 afe_priv->clocks[MT8173_CLK_I2S3_B]); 353 return 0; 354 } 355 356 static void mt8173_afe_hdmi_shutdown(struct snd_pcm_substream *substream, 357 struct snd_soc_dai *dai) 358 { 359 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 360 struct mt8173_afe_private *afe_priv = afe->platform_priv; 361 362 if (snd_soc_dai_active(dai)) 363 return; 364 365 mt8173_afe_dais_disable_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 366 afe_priv->clocks[MT8173_CLK_I2S3_B]); 367 } 368 369 static int mt8173_afe_hdmi_prepare(struct snd_pcm_substream *substream, 370 struct snd_soc_dai *dai) 371 { 372 struct snd_pcm_runtime * const runtime = substream->runtime; 373 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 374 struct mt8173_afe_private *afe_priv = afe->platform_priv; 375 376 unsigned int val; 377 378 mt8173_afe_dais_set_clks(afe, afe_priv->clocks[MT8173_CLK_I2S3_M], 379 runtime->rate * 128, 380 afe_priv->clocks[MT8173_CLK_I2S3_B], 381 runtime->rate * runtime->channels * 32); 382 383 val = AFE_TDM_CON1_BCK_INV | 384 AFE_TDM_CON1_LRCK_INV | 385 AFE_TDM_CON1_1_BCK_DELAY | 386 AFE_TDM_CON1_MSB_ALIGNED | /* I2S mode */ 387 AFE_TDM_CON1_WLEN_32BIT | 388 AFE_TDM_CON1_32_BCK_CYCLES | 389 AFE_TDM_CON1_LRCK_WIDTH(32); 390 regmap_update_bits(afe->regmap, AFE_TDM_CON1, ~AFE_TDM_CON1_EN, val); 391 392 /* set tdm2 config */ 393 switch (runtime->channels) { 394 case 1: 395 case 2: 396 val = AFE_TDM_CH_START_O30_O31; 397 val |= (AFE_TDM_CH_ZERO << 4); 398 val |= (AFE_TDM_CH_ZERO << 8); 399 val |= (AFE_TDM_CH_ZERO << 12); 400 break; 401 case 3: 402 case 4: 403 val = AFE_TDM_CH_START_O30_O31; 404 val |= (AFE_TDM_CH_START_O32_O33 << 4); 405 val |= (AFE_TDM_CH_ZERO << 8); 406 val |= (AFE_TDM_CH_ZERO << 12); 407 break; 408 case 5: 409 case 6: 410 val = AFE_TDM_CH_START_O30_O31; 411 val |= (AFE_TDM_CH_START_O32_O33 << 4); 412 val |= (AFE_TDM_CH_START_O34_O35 << 8); 413 val |= (AFE_TDM_CH_ZERO << 12); 414 break; 415 case 7: 416 case 8: 417 val = AFE_TDM_CH_START_O30_O31; 418 val |= (AFE_TDM_CH_START_O32_O33 << 4); 419 val |= (AFE_TDM_CH_START_O34_O35 << 8); 420 val |= (AFE_TDM_CH_START_O36_O37 << 12); 421 break; 422 default: 423 val = 0; 424 } 425 regmap_update_bits(afe->regmap, AFE_TDM_CON2, 0x0000ffff, val); 426 427 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 428 0x000000f0, runtime->channels << 4); 429 return 0; 430 } 431 432 static int mt8173_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd, 433 struct snd_soc_dai *dai) 434 { 435 struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai); 436 437 dev_info(afe->dev, "%s cmd=%d %s\n", __func__, cmd, dai->name); 438 439 switch (cmd) { 440 case SNDRV_PCM_TRIGGER_START: 441 case SNDRV_PCM_TRIGGER_RESUME: 442 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 443 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 0); 444 445 /* set connections: O30~O37: L/R/LS/RS/C/LFE/CH7/CH8 */ 446 regmap_write(afe->regmap, AFE_HDMI_CONN0, 447 AFE_HDMI_CONN0_O30_I30 | 448 AFE_HDMI_CONN0_O31_I31 | 449 AFE_HDMI_CONN0_O32_I34 | 450 AFE_HDMI_CONN0_O33_I35 | 451 AFE_HDMI_CONN0_O34_I32 | 452 AFE_HDMI_CONN0_O35_I33 | 453 AFE_HDMI_CONN0_O36_I36 | 454 AFE_HDMI_CONN0_O37_I37); 455 456 /* enable Out control */ 457 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0x1); 458 459 /* enable tdm */ 460 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0x1); 461 462 return 0; 463 case SNDRV_PCM_TRIGGER_STOP: 464 case SNDRV_PCM_TRIGGER_SUSPEND: 465 /* disable tdm */ 466 regmap_update_bits(afe->regmap, AFE_TDM_CON1, 0x1, 0); 467 468 /* disable Out control */ 469 regmap_update_bits(afe->regmap, AFE_HDMI_OUT_CON0, 0x1, 0); 470 471 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 472 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF, 473 AUD_TCON0_PDN_HDMI | AUD_TCON0_PDN_SPDF); 474 return 0; 475 default: 476 return -EINVAL; 477 } 478 } 479 480 static int mt8173_memif_fs(struct snd_pcm_substream *substream, 481 unsigned int rate) 482 { 483 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream); 484 struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, AFE_PCM_NAME); 485 struct mtk_base_afe *afe = snd_soc_component_get_drvdata(component); 486 struct mtk_base_afe_memif *memif = &afe->memif[asoc_rtd_to_cpu(rtd, 0)->id]; 487 int fs; 488 489 if (memif->data->id == MT8173_AFE_MEMIF_DAI || 490 memif->data->id == MT8173_AFE_MEMIF_MOD_DAI) { 491 switch (rate) { 492 case 8000: 493 fs = 0; 494 break; 495 case 16000: 496 fs = 1; 497 break; 498 case 32000: 499 fs = 2; 500 break; 501 default: 502 return -EINVAL; 503 } 504 } else { 505 fs = mt8173_afe_i2s_fs(rate); 506 } 507 return fs; 508 } 509 510 static int mt8173_irq_fs(struct snd_pcm_substream *substream, unsigned int rate) 511 { 512 return mt8173_afe_i2s_fs(rate); 513 } 514 515 /* BE DAIs */ 516 static const struct snd_soc_dai_ops mt8173_afe_i2s_ops = { 517 .startup = mt8173_afe_i2s_startup, 518 .shutdown = mt8173_afe_i2s_shutdown, 519 .prepare = mt8173_afe_i2s_prepare, 520 }; 521 522 static const struct snd_soc_dai_ops mt8173_afe_hdmi_ops = { 523 .startup = mt8173_afe_hdmi_startup, 524 .shutdown = mt8173_afe_hdmi_shutdown, 525 .prepare = mt8173_afe_hdmi_prepare, 526 .trigger = mt8173_afe_hdmi_trigger, 527 }; 528 529 static struct snd_soc_dai_driver mt8173_afe_pcm_dais[] = { 530 /* FE DAIs: memory intefaces to CPU */ 531 { 532 .name = "DL1", /* downlink 1 */ 533 .id = MT8173_AFE_MEMIF_DL1, 534 .playback = { 535 .stream_name = "DL1", 536 .channels_min = 1, 537 .channels_max = 2, 538 .rates = SNDRV_PCM_RATE_8000_48000, 539 .formats = SNDRV_PCM_FMTBIT_S16_LE, 540 }, 541 .ops = &mtk_afe_fe_ops, 542 }, { 543 .name = "VUL", /* voice uplink */ 544 .id = MT8173_AFE_MEMIF_VUL, 545 .capture = { 546 .stream_name = "VUL", 547 .channels_min = 1, 548 .channels_max = 2, 549 .rates = SNDRV_PCM_RATE_8000_48000, 550 .formats = SNDRV_PCM_FMTBIT_S16_LE, 551 }, 552 .ops = &mtk_afe_fe_ops, 553 }, { 554 /* BE DAIs */ 555 .name = "I2S", 556 .id = MT8173_AFE_IO_I2S, 557 .playback = { 558 .stream_name = "I2S Playback", 559 .channels_min = 1, 560 .channels_max = 2, 561 .rates = SNDRV_PCM_RATE_8000_48000, 562 .formats = SNDRV_PCM_FMTBIT_S16_LE, 563 }, 564 .capture = { 565 .stream_name = "I2S Capture", 566 .channels_min = 1, 567 .channels_max = 2, 568 .rates = SNDRV_PCM_RATE_8000_48000, 569 .formats = SNDRV_PCM_FMTBIT_S16_LE, 570 }, 571 .ops = &mt8173_afe_i2s_ops, 572 .symmetric_rate = 1, 573 }, 574 }; 575 576 static struct snd_soc_dai_driver mt8173_afe_hdmi_dais[] = { 577 /* FE DAIs */ 578 { 579 .name = "HDMI", 580 .id = MT8173_AFE_MEMIF_HDMI, 581 .playback = { 582 .stream_name = "HDMI", 583 .channels_min = 2, 584 .channels_max = 8, 585 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 586 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 587 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 588 SNDRV_PCM_RATE_192000, 589 .formats = SNDRV_PCM_FMTBIT_S16_LE, 590 }, 591 .ops = &mtk_afe_fe_ops, 592 }, { 593 /* BE DAIs */ 594 .name = "HDMIO", 595 .id = MT8173_AFE_IO_HDMI, 596 .playback = { 597 .stream_name = "HDMIO Playback", 598 .channels_min = 2, 599 .channels_max = 8, 600 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 601 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 602 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 603 SNDRV_PCM_RATE_192000, 604 .formats = SNDRV_PCM_FMTBIT_S16_LE, 605 }, 606 .ops = &mt8173_afe_hdmi_ops, 607 }, 608 }; 609 610 static const struct snd_kcontrol_new mt8173_afe_o03_mix[] = { 611 SOC_DAPM_SINGLE_AUTODISABLE("I05 Switch", AFE_CONN1, 21, 1, 0), 612 }; 613 614 static const struct snd_kcontrol_new mt8173_afe_o04_mix[] = { 615 SOC_DAPM_SINGLE_AUTODISABLE("I06 Switch", AFE_CONN2, 6, 1, 0), 616 }; 617 618 static const struct snd_kcontrol_new mt8173_afe_o09_mix[] = { 619 SOC_DAPM_SINGLE_AUTODISABLE("I03 Switch", AFE_CONN3, 0, 1, 0), 620 SOC_DAPM_SINGLE_AUTODISABLE("I17 Switch", AFE_CONN7, 30, 1, 0), 621 }; 622 623 static const struct snd_kcontrol_new mt8173_afe_o10_mix[] = { 624 SOC_DAPM_SINGLE_AUTODISABLE("I04 Switch", AFE_CONN3, 3, 1, 0), 625 SOC_DAPM_SINGLE_AUTODISABLE("I18 Switch", AFE_CONN8, 0, 1, 0), 626 }; 627 628 static const struct snd_soc_dapm_widget mt8173_afe_pcm_widgets[] = { 629 /* inter-connections */ 630 SND_SOC_DAPM_MIXER("I03", SND_SOC_NOPM, 0, 0, NULL, 0), 631 SND_SOC_DAPM_MIXER("I04", SND_SOC_NOPM, 0, 0, NULL, 0), 632 SND_SOC_DAPM_MIXER("I05", SND_SOC_NOPM, 0, 0, NULL, 0), 633 SND_SOC_DAPM_MIXER("I06", SND_SOC_NOPM, 0, 0, NULL, 0), 634 SND_SOC_DAPM_MIXER("I17", SND_SOC_NOPM, 0, 0, NULL, 0), 635 SND_SOC_DAPM_MIXER("I18", SND_SOC_NOPM, 0, 0, NULL, 0), 636 637 SND_SOC_DAPM_MIXER("O03", SND_SOC_NOPM, 0, 0, 638 mt8173_afe_o03_mix, ARRAY_SIZE(mt8173_afe_o03_mix)), 639 SND_SOC_DAPM_MIXER("O04", SND_SOC_NOPM, 0, 0, 640 mt8173_afe_o04_mix, ARRAY_SIZE(mt8173_afe_o04_mix)), 641 SND_SOC_DAPM_MIXER("O09", SND_SOC_NOPM, 0, 0, 642 mt8173_afe_o09_mix, ARRAY_SIZE(mt8173_afe_o09_mix)), 643 SND_SOC_DAPM_MIXER("O10", SND_SOC_NOPM, 0, 0, 644 mt8173_afe_o10_mix, ARRAY_SIZE(mt8173_afe_o10_mix)), 645 }; 646 647 static const struct snd_soc_dapm_route mt8173_afe_pcm_routes[] = { 648 {"I05", NULL, "DL1"}, 649 {"I06", NULL, "DL1"}, 650 {"I2S Playback", NULL, "O03"}, 651 {"I2S Playback", NULL, "O04"}, 652 {"VUL", NULL, "O09"}, 653 {"VUL", NULL, "O10"}, 654 {"I03", NULL, "I2S Capture"}, 655 {"I04", NULL, "I2S Capture"}, 656 {"I17", NULL, "I2S Capture"}, 657 {"I18", NULL, "I2S Capture"}, 658 { "O03", "I05 Switch", "I05" }, 659 { "O04", "I06 Switch", "I06" }, 660 { "O09", "I17 Switch", "I17" }, 661 { "O09", "I03 Switch", "I03" }, 662 { "O10", "I18 Switch", "I18" }, 663 { "O10", "I04 Switch", "I04" }, 664 }; 665 666 static const struct snd_soc_dapm_route mt8173_afe_hdmi_routes[] = { 667 {"HDMIO Playback", NULL, "HDMI"}, 668 }; 669 670 static const struct snd_soc_component_driver mt8173_afe_pcm_dai_component = { 671 .name = "mt8173-afe-pcm-dai", 672 .dapm_widgets = mt8173_afe_pcm_widgets, 673 .num_dapm_widgets = ARRAY_SIZE(mt8173_afe_pcm_widgets), 674 .dapm_routes = mt8173_afe_pcm_routes, 675 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_pcm_routes), 676 .suspend = mtk_afe_suspend, 677 .resume = mtk_afe_resume, 678 }; 679 680 static const struct snd_soc_component_driver mt8173_afe_hdmi_dai_component = { 681 .name = "mt8173-afe-hdmi-dai", 682 .dapm_routes = mt8173_afe_hdmi_routes, 683 .num_dapm_routes = ARRAY_SIZE(mt8173_afe_hdmi_routes), 684 .suspend = mtk_afe_suspend, 685 .resume = mtk_afe_resume, 686 }; 687 688 static const char *aud_clks[MT8173_CLK_NUM] = { 689 [MT8173_CLK_INFRASYS_AUD] = "infra_sys_audio_clk", 690 [MT8173_CLK_TOP_PDN_AUD] = "top_pdn_audio", 691 [MT8173_CLK_TOP_PDN_AUD_BUS] = "top_pdn_aud_intbus", 692 [MT8173_CLK_I2S0_M] = "i2s0_m", 693 [MT8173_CLK_I2S1_M] = "i2s1_m", 694 [MT8173_CLK_I2S2_M] = "i2s2_m", 695 [MT8173_CLK_I2S3_M] = "i2s3_m", 696 [MT8173_CLK_I2S3_B] = "i2s3_b", 697 [MT8173_CLK_BCK0] = "bck0", 698 [MT8173_CLK_BCK1] = "bck1", 699 }; 700 701 static const struct mtk_base_memif_data memif_data[MT8173_AFE_MEMIF_NUM] = { 702 { 703 .name = "DL1", 704 .id = MT8173_AFE_MEMIF_DL1, 705 .reg_ofs_base = AFE_DL1_BASE, 706 .reg_ofs_cur = AFE_DL1_CUR, 707 .fs_reg = AFE_DAC_CON1, 708 .fs_shift = 0, 709 .fs_maskbit = 0xf, 710 .mono_reg = AFE_DAC_CON1, 711 .mono_shift = 21, 712 .hd_reg = -1, 713 .enable_reg = AFE_DAC_CON0, 714 .enable_shift = 1, 715 .msb_reg = AFE_MEMIF_MSB, 716 .msb_shift = 0, 717 .agent_disable_reg = -1, 718 }, { 719 .name = "DL2", 720 .id = MT8173_AFE_MEMIF_DL2, 721 .reg_ofs_base = AFE_DL2_BASE, 722 .reg_ofs_cur = AFE_DL2_CUR, 723 .fs_reg = AFE_DAC_CON1, 724 .fs_shift = 4, 725 .fs_maskbit = 0xf, 726 .mono_reg = AFE_DAC_CON1, 727 .mono_shift = 22, 728 .hd_reg = -1, 729 .enable_reg = AFE_DAC_CON0, 730 .enable_shift = 2, 731 .msb_reg = AFE_MEMIF_MSB, 732 .msb_shift = 1, 733 .agent_disable_reg = -1, 734 }, { 735 .name = "VUL", 736 .id = MT8173_AFE_MEMIF_VUL, 737 .reg_ofs_base = AFE_VUL_BASE, 738 .reg_ofs_cur = AFE_VUL_CUR, 739 .fs_reg = AFE_DAC_CON1, 740 .fs_shift = 16, 741 .fs_maskbit = 0xf, 742 .mono_reg = AFE_DAC_CON1, 743 .mono_shift = 27, 744 .hd_reg = -1, 745 .enable_reg = AFE_DAC_CON0, 746 .enable_shift = 3, 747 .msb_reg = AFE_MEMIF_MSB, 748 .msb_shift = 6, 749 .agent_disable_reg = -1, 750 }, { 751 .name = "DAI", 752 .id = MT8173_AFE_MEMIF_DAI, 753 .reg_ofs_base = AFE_DAI_BASE, 754 .reg_ofs_cur = AFE_DAI_CUR, 755 .fs_reg = AFE_DAC_CON0, 756 .fs_shift = 24, 757 .fs_maskbit = 0x3, 758 .mono_reg = -1, 759 .mono_shift = -1, 760 .hd_reg = -1, 761 .enable_reg = AFE_DAC_CON0, 762 .enable_shift = 4, 763 .msb_reg = AFE_MEMIF_MSB, 764 .msb_shift = 5, 765 .agent_disable_reg = -1, 766 }, { 767 .name = "AWB", 768 .id = MT8173_AFE_MEMIF_AWB, 769 .reg_ofs_base = AFE_AWB_BASE, 770 .reg_ofs_cur = AFE_AWB_CUR, 771 .fs_reg = AFE_DAC_CON1, 772 .fs_shift = 12, 773 .fs_maskbit = 0xf, 774 .mono_reg = AFE_DAC_CON1, 775 .mono_shift = 24, 776 .hd_reg = -1, 777 .enable_reg = AFE_DAC_CON0, 778 .enable_shift = 6, 779 .msb_reg = AFE_MEMIF_MSB, 780 .msb_shift = 3, 781 .agent_disable_reg = -1, 782 }, { 783 .name = "MOD_DAI", 784 .id = MT8173_AFE_MEMIF_MOD_DAI, 785 .reg_ofs_base = AFE_MOD_PCM_BASE, 786 .reg_ofs_cur = AFE_MOD_PCM_CUR, 787 .fs_reg = AFE_DAC_CON1, 788 .fs_shift = 30, 789 .fs_maskbit = 0x3, 790 .mono_reg = AFE_DAC_CON1, 791 .mono_shift = 30, 792 .hd_reg = -1, 793 .enable_reg = AFE_DAC_CON0, 794 .enable_shift = 7, 795 .msb_reg = AFE_MEMIF_MSB, 796 .msb_shift = 4, 797 .agent_disable_reg = -1, 798 }, { 799 .name = "HDMI", 800 .id = MT8173_AFE_MEMIF_HDMI, 801 .reg_ofs_base = AFE_HDMI_OUT_BASE, 802 .reg_ofs_cur = AFE_HDMI_OUT_CUR, 803 .fs_reg = -1, 804 .fs_shift = -1, 805 .fs_maskbit = -1, 806 .mono_reg = -1, 807 .mono_shift = -1, 808 .hd_reg = -1, 809 .enable_reg = -1, 810 .msb_reg = AFE_MEMIF_MSB, 811 .msb_shift = 8, 812 .agent_disable_reg = -1, 813 }, 814 }; 815 816 static const struct mtk_base_irq_data irq_data[MT8173_AFE_IRQ_NUM] = { 817 { 818 .id = MT8173_AFE_IRQ_DL1, 819 .irq_cnt_reg = AFE_IRQ_CNT1, 820 .irq_cnt_shift = 0, 821 .irq_cnt_maskbit = 0x3ffff, 822 .irq_en_reg = AFE_IRQ_MCU_CON, 823 .irq_en_shift = 0, 824 .irq_fs_reg = AFE_IRQ_MCU_CON, 825 .irq_fs_shift = 4, 826 .irq_fs_maskbit = 0xf, 827 .irq_clr_reg = AFE_IRQ_CLR, 828 .irq_clr_shift = 0, 829 }, { 830 .id = MT8173_AFE_IRQ_DL2, 831 .irq_cnt_reg = AFE_IRQ_CNT1, 832 .irq_cnt_shift = 20, 833 .irq_cnt_maskbit = 0x3ffff, 834 .irq_en_reg = AFE_IRQ_MCU_CON, 835 .irq_en_shift = 2, 836 .irq_fs_reg = AFE_IRQ_MCU_CON, 837 .irq_fs_shift = 16, 838 .irq_fs_maskbit = 0xf, 839 .irq_clr_reg = AFE_IRQ_CLR, 840 .irq_clr_shift = 2, 841 842 }, { 843 .id = MT8173_AFE_IRQ_VUL, 844 .irq_cnt_reg = AFE_IRQ_CNT2, 845 .irq_cnt_shift = 0, 846 .irq_cnt_maskbit = 0x3ffff, 847 .irq_en_reg = AFE_IRQ_MCU_CON, 848 .irq_en_shift = 1, 849 .irq_fs_reg = AFE_IRQ_MCU_CON, 850 .irq_fs_shift = 8, 851 .irq_fs_maskbit = 0xf, 852 .irq_clr_reg = AFE_IRQ_CLR, 853 .irq_clr_shift = 1, 854 }, { 855 .id = MT8173_AFE_IRQ_DAI, 856 .irq_cnt_reg = AFE_IRQ_CNT2, 857 .irq_cnt_shift = 20, 858 .irq_cnt_maskbit = 0x3ffff, 859 .irq_en_reg = AFE_IRQ_MCU_CON, 860 .irq_en_shift = 3, 861 .irq_fs_reg = AFE_IRQ_MCU_CON, 862 .irq_fs_shift = 20, 863 .irq_fs_maskbit = 0xf, 864 .irq_clr_reg = AFE_IRQ_CLR, 865 .irq_clr_shift = 3, 866 }, { 867 .id = MT8173_AFE_IRQ_AWB, 868 .irq_cnt_reg = AFE_IRQ_CNT7, 869 .irq_cnt_shift = 0, 870 .irq_cnt_maskbit = 0x3ffff, 871 .irq_en_reg = AFE_IRQ_MCU_CON, 872 .irq_en_shift = 14, 873 .irq_fs_reg = AFE_IRQ_MCU_CON, 874 .irq_fs_shift = 24, 875 .irq_fs_maskbit = 0xf, 876 .irq_clr_reg = AFE_IRQ_CLR, 877 .irq_clr_shift = 6, 878 }, { 879 .id = MT8173_AFE_IRQ_DAI, 880 .irq_cnt_reg = AFE_IRQ_CNT2, 881 .irq_cnt_shift = 20, 882 .irq_cnt_maskbit = 0x3ffff, 883 .irq_en_reg = AFE_IRQ_MCU_CON, 884 .irq_en_shift = 3, 885 .irq_fs_reg = AFE_IRQ_MCU_CON, 886 .irq_fs_shift = 20, 887 .irq_fs_maskbit = 0xf, 888 .irq_clr_reg = AFE_IRQ_CLR, 889 .irq_clr_shift = 3, 890 }, { 891 .id = MT8173_AFE_IRQ_HDMI, 892 .irq_cnt_reg = AFE_IRQ_CNT5, 893 .irq_cnt_shift = 0, 894 .irq_cnt_maskbit = 0x3ffff, 895 .irq_en_reg = AFE_IRQ_MCU_CON, 896 .irq_en_shift = 12, 897 .irq_fs_reg = -1, 898 .irq_fs_maskbit = -1, 899 .irq_clr_reg = AFE_IRQ_CLR, 900 .irq_clr_shift = 4, 901 }, 902 }; 903 904 static const struct regmap_config mt8173_afe_regmap_config = { 905 .reg_bits = 32, 906 .reg_stride = 4, 907 .val_bits = 32, 908 .max_register = AFE_ADDA2_TOP_CON0, 909 .cache_type = REGCACHE_NONE, 910 }; 911 912 static irqreturn_t mt8173_afe_irq_handler(int irq, void *dev_id) 913 { 914 struct mtk_base_afe *afe = dev_id; 915 unsigned int reg_value; 916 int i, ret; 917 918 ret = regmap_read(afe->regmap, AFE_IRQ_STATUS, ®_value); 919 if (ret) { 920 dev_err(afe->dev, "%s irq status err\n", __func__); 921 reg_value = AFE_IRQ_STATUS_BITS; 922 goto err_irq; 923 } 924 925 for (i = 0; i < MT8173_AFE_MEMIF_NUM; i++) { 926 struct mtk_base_afe_memif *memif = &afe->memif[i]; 927 struct mtk_base_afe_irq *irq_p; 928 929 if (memif->irq_usage < 0) 930 continue; 931 932 irq_p = &afe->irqs[memif->irq_usage]; 933 934 if (!(reg_value & (1 << irq_p->irq_data->irq_clr_shift))) 935 continue; 936 937 snd_pcm_period_elapsed(memif->substream); 938 } 939 940 err_irq: 941 /* clear irq */ 942 regmap_write(afe->regmap, AFE_IRQ_CLR, 943 reg_value & AFE_IRQ_STATUS_BITS); 944 945 return IRQ_HANDLED; 946 } 947 948 static int mt8173_afe_runtime_suspend(struct device *dev) 949 { 950 struct mtk_base_afe *afe = dev_get_drvdata(dev); 951 struct mt8173_afe_private *afe_priv = afe->platform_priv; 952 953 /* disable AFE */ 954 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0); 955 956 /* disable AFE clk */ 957 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 958 AUD_TCON0_PDN_AFE, AUD_TCON0_PDN_AFE); 959 960 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 961 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 962 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 963 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK1]); 964 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 965 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 966 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 967 return 0; 968 } 969 970 static int mt8173_afe_runtime_resume(struct device *dev) 971 { 972 struct mtk_base_afe *afe = dev_get_drvdata(dev); 973 struct mt8173_afe_private *afe_priv = afe->platform_priv; 974 int ret; 975 976 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 977 if (ret) 978 return ret; 979 980 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 981 if (ret) 982 goto err_infra; 983 984 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 985 if (ret) 986 goto err_top_aud_bus; 987 988 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK0]); 989 if (ret) 990 goto err_top_aud; 991 992 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_BCK1]); 993 if (ret) 994 goto err_bck0; 995 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S1_M]); 996 if (ret) 997 goto err_i2s1_m; 998 ret = clk_prepare_enable(afe_priv->clocks[MT8173_CLK_I2S2_M]); 999 if (ret) 1000 goto err_i2s2_m; 1001 1002 /* enable AFE clk */ 1003 regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, AUD_TCON0_PDN_AFE, 0); 1004 1005 /* set O3/O4 16bits */ 1006 regmap_update_bits(afe->regmap, AFE_CONN_24BIT, 1007 AFE_CONN_24BIT_O03 | AFE_CONN_24BIT_O04, 0); 1008 1009 /* unmask all IRQs */ 1010 regmap_update_bits(afe->regmap, AFE_IRQ_MCU_EN, 0xff, 0xff); 1011 1012 /* enable AFE */ 1013 regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); 1014 return 0; 1015 1016 err_i2s1_m: 1017 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S1_M]); 1018 err_i2s2_m: 1019 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_I2S2_M]); 1020 err_bck0: 1021 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_BCK0]); 1022 err_top_aud: 1023 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD]); 1024 err_top_aud_bus: 1025 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_TOP_PDN_AUD_BUS]); 1026 err_infra: 1027 clk_disable_unprepare(afe_priv->clocks[MT8173_CLK_INFRASYS_AUD]); 1028 return ret; 1029 } 1030 1031 static int mt8173_afe_init_audio_clk(struct mtk_base_afe *afe) 1032 { 1033 size_t i; 1034 struct mt8173_afe_private *afe_priv = afe->platform_priv; 1035 1036 for (i = 0; i < ARRAY_SIZE(aud_clks); i++) { 1037 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); 1038 if (IS_ERR(afe_priv->clocks[i])) { 1039 dev_err(afe->dev, "%s devm_clk_get %s fail\n", 1040 __func__, aud_clks[i]); 1041 return PTR_ERR(afe_priv->clocks[i]); 1042 } 1043 } 1044 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK0], 22579200); /* 22M */ 1045 clk_set_rate(afe_priv->clocks[MT8173_CLK_BCK1], 24576000); /* 24M */ 1046 return 0; 1047 } 1048 1049 static int mt8173_afe_pcm_dev_probe(struct platform_device *pdev) 1050 { 1051 int ret, i; 1052 int irq_id; 1053 struct mtk_base_afe *afe; 1054 struct mt8173_afe_private *afe_priv; 1055 struct snd_soc_component *comp_pcm, *comp_hdmi; 1056 1057 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(33)); 1058 if (ret) 1059 return ret; 1060 1061 afe = devm_kzalloc(&pdev->dev, sizeof(*afe), GFP_KERNEL); 1062 if (!afe) 1063 return -ENOMEM; 1064 1065 afe->platform_priv = devm_kzalloc(&pdev->dev, sizeof(*afe_priv), 1066 GFP_KERNEL); 1067 afe_priv = afe->platform_priv; 1068 if (!afe_priv) 1069 return -ENOMEM; 1070 1071 afe->dev = &pdev->dev; 1072 1073 irq_id = platform_get_irq(pdev, 0); 1074 if (irq_id <= 0) 1075 return irq_id < 0 ? irq_id : -ENXIO; 1076 1077 afe->base_addr = devm_platform_ioremap_resource(pdev, 0); 1078 if (IS_ERR(afe->base_addr)) 1079 return PTR_ERR(afe->base_addr); 1080 1081 afe->regmap = devm_regmap_init_mmio(&pdev->dev, afe->base_addr, 1082 &mt8173_afe_regmap_config); 1083 if (IS_ERR(afe->regmap)) 1084 return PTR_ERR(afe->regmap); 1085 1086 /* initial audio related clock */ 1087 ret = mt8173_afe_init_audio_clk(afe); 1088 if (ret) { 1089 dev_err(afe->dev, "mt8173_afe_init_audio_clk fail\n"); 1090 return ret; 1091 } 1092 1093 /* memif % irq initialize*/ 1094 afe->memif_size = MT8173_AFE_MEMIF_NUM; 1095 afe->memif = devm_kcalloc(afe->dev, afe->memif_size, 1096 sizeof(*afe->memif), GFP_KERNEL); 1097 if (!afe->memif) 1098 return -ENOMEM; 1099 1100 afe->irqs_size = MT8173_AFE_IRQ_NUM; 1101 afe->irqs = devm_kcalloc(afe->dev, afe->irqs_size, 1102 sizeof(*afe->irqs), GFP_KERNEL); 1103 if (!afe->irqs) 1104 return -ENOMEM; 1105 1106 for (i = 0; i < afe->irqs_size; i++) { 1107 afe->memif[i].data = &memif_data[i]; 1108 afe->irqs[i].irq_data = &irq_data[i]; 1109 afe->irqs[i].irq_occupyed = true; 1110 afe->memif[i].irq_usage = i; 1111 afe->memif[i].const_irq = 1; 1112 } 1113 1114 afe->mtk_afe_hardware = &mt8173_afe_hardware; 1115 afe->memif_fs = mt8173_memif_fs; 1116 afe->irq_fs = mt8173_irq_fs; 1117 1118 platform_set_drvdata(pdev, afe); 1119 1120 pm_runtime_enable(&pdev->dev); 1121 if (!pm_runtime_enabled(&pdev->dev)) { 1122 ret = mt8173_afe_runtime_resume(&pdev->dev); 1123 if (ret) 1124 goto err_pm_disable; 1125 } 1126 1127 afe->reg_back_up_list = mt8173_afe_backup_list; 1128 afe->reg_back_up_list_num = ARRAY_SIZE(mt8173_afe_backup_list); 1129 afe->runtime_resume = mt8173_afe_runtime_resume; 1130 afe->runtime_suspend = mt8173_afe_runtime_suspend; 1131 1132 ret = devm_snd_soc_register_component(&pdev->dev, 1133 &mtk_afe_pcm_platform, 1134 NULL, 0); 1135 if (ret) 1136 goto err_pm_disable; 1137 1138 comp_pcm = devm_kzalloc(&pdev->dev, sizeof(*comp_pcm), GFP_KERNEL); 1139 if (!comp_pcm) { 1140 ret = -ENOMEM; 1141 goto err_pm_disable; 1142 } 1143 1144 ret = snd_soc_component_initialize(comp_pcm, 1145 &mt8173_afe_pcm_dai_component, 1146 &pdev->dev); 1147 if (ret) 1148 goto err_pm_disable; 1149 1150 #ifdef CONFIG_DEBUG_FS 1151 comp_pcm->debugfs_prefix = "pcm"; 1152 #endif 1153 1154 ret = snd_soc_add_component(comp_pcm, 1155 mt8173_afe_pcm_dais, 1156 ARRAY_SIZE(mt8173_afe_pcm_dais)); 1157 if (ret) 1158 goto err_pm_disable; 1159 1160 comp_hdmi = devm_kzalloc(&pdev->dev, sizeof(*comp_hdmi), GFP_KERNEL); 1161 if (!comp_hdmi) { 1162 ret = -ENOMEM; 1163 goto err_cleanup_components; 1164 } 1165 1166 ret = snd_soc_component_initialize(comp_hdmi, 1167 &mt8173_afe_hdmi_dai_component, 1168 &pdev->dev); 1169 if (ret) 1170 goto err_cleanup_components; 1171 1172 #ifdef CONFIG_DEBUG_FS 1173 comp_hdmi->debugfs_prefix = "hdmi"; 1174 #endif 1175 1176 ret = snd_soc_add_component(comp_hdmi, 1177 mt8173_afe_hdmi_dais, 1178 ARRAY_SIZE(mt8173_afe_hdmi_dais)); 1179 if (ret) 1180 goto err_cleanup_components; 1181 1182 ret = devm_request_irq(afe->dev, irq_id, mt8173_afe_irq_handler, 1183 0, "Afe_ISR_Handle", (void *)afe); 1184 if (ret) { 1185 dev_err(afe->dev, "could not request_irq\n"); 1186 goto err_cleanup_components; 1187 } 1188 1189 dev_info(&pdev->dev, "MT8173 AFE driver initialized.\n"); 1190 return 0; 1191 1192 err_cleanup_components: 1193 snd_soc_unregister_component(&pdev->dev); 1194 err_pm_disable: 1195 pm_runtime_disable(&pdev->dev); 1196 return ret; 1197 } 1198 1199 static void mt8173_afe_pcm_dev_remove(struct platform_device *pdev) 1200 { 1201 snd_soc_unregister_component(&pdev->dev); 1202 1203 pm_runtime_disable(&pdev->dev); 1204 if (!pm_runtime_status_suspended(&pdev->dev)) 1205 mt8173_afe_runtime_suspend(&pdev->dev); 1206 } 1207 1208 static const struct of_device_id mt8173_afe_pcm_dt_match[] = { 1209 { .compatible = "mediatek,mt8173-afe-pcm", }, 1210 { } 1211 }; 1212 MODULE_DEVICE_TABLE(of, mt8173_afe_pcm_dt_match); 1213 1214 static const struct dev_pm_ops mt8173_afe_pm_ops = { 1215 SET_RUNTIME_PM_OPS(mt8173_afe_runtime_suspend, 1216 mt8173_afe_runtime_resume, NULL) 1217 }; 1218 1219 static struct platform_driver mt8173_afe_pcm_driver = { 1220 .driver = { 1221 .name = "mt8173-afe-pcm", 1222 .of_match_table = mt8173_afe_pcm_dt_match, 1223 .pm = &mt8173_afe_pm_ops, 1224 }, 1225 .probe = mt8173_afe_pcm_dev_probe, 1226 .remove_new = mt8173_afe_pcm_dev_remove, 1227 }; 1228 1229 module_platform_driver(mt8173_afe_pcm_driver); 1230 1231 MODULE_DESCRIPTION("Mediatek ALSA SoC AFE platform driver"); 1232 MODULE_AUTHOR("Koro Chen <koro.chen@mediatek.com>"); 1233 MODULE_LICENSE("GPL v2"); 1234